Power Analysis Countermeasures Research Articles

Proposal of a lightweight differential power analysis countermeasure method on elliptic curves for low-cost devices

Proposal of a lightweight differential power analysis countermeasure method on elliptic curves for low-cost devices

Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption

Present complementary metal–oxide–semiconductor (CMOS) technology with scaled channel lengths exhibits higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier-based secure differential power analysis (DPA) countermeasures at scaled channel lengths show large energy consumption, with increased vulnerability. Additionally, spin-transfer torque magnetic tunnel junction (STT-MTJ) and CMOS-based logic-in-memory (LiM) cells demonstrate high energy consumption due to the large write current requirement of the STT-MTJ and poor MOS device performance at scaled channel lengths. This paper for the first time leverages emerging tunnel field effect transistor (TFET) steep-slope device characteristics and compatible non-volatile STT-MTJ devices for enhanced hardware security with ultra-low energy consumption at lower supply voltages. TFET-based sense amplifier-based logic (SABL) gates are proposed that achieve 3× lower energy consumption than the Si FinFET SABL designs. Further, utilizing TFET SABL gates, a TFET PRIDE S-box is designed that exhibits higher DPA resilience with 3.2× lower energy consumption than the FinFET designs. With the resulting lower static power consumption, TFET SABL-based cryptosystems are thus less vulnerable to static power side-channel attacks. Additionally, the proposed STT-MTJ and TFET LiM gates achieve 4× lower energy consumption than the STT-MTJ and FinFET designs. Lastly, these gates are explored in a logic encryption/locking technique that shows 3.1× lower energy consumption than the STT-MTJ and FinFET-based design.

Multiple countermeasures on unrolled architecture PRINCE against power analysis and its evaluation

AbstractLightweight block ciphers, which can be implemented with low cost, are suitable for improving the safety of small devices. PRINCE is a typical lightweight block cipher and suitable for unrolled architecture implementation. In addition, PRINCE can be achieved low latency and embedded in a small area. However, it has been reported that PRINCE with unrolled architecture implementation is vulnerable to power analysis. Regarding countermeasure against power analysis, the threshold implementation and rotating S‐boxes masking are popular countermeasures, these require large implementation overhead though. Therefore, this study proposes a low‐overhead power analysis countermeasure method for PRINCE with unrolled architecture. Moreover, evaluation experiments using a field‐programmable gate array verify the effectiveness of the proposed method. In experiments, the proposed method improved tamper resistance and reduced implementation overhead in comparison with the conventional method.

Efficient and Secure Implementation of NTRUEncrypt Using Signed Sliding Window Method

NTRUEncrypt is a public key cryptosystem based on hard problems over lattices. The dominant operation in NTRUEncrypt is convolution, i.e., multiplication over a quotient ring of polynomials. Based on the fact that a convolution has a highly regular structure, Lee et al. proposed the sliding window method for fast convolution of binary polynomials in 2013, which was then extended to ternary polynomials for ideal lattices by Akleylek, Alkim, and Tok in 2016. These sliding window methods reduce the cost of a convolution operation using look-up tables that store partial computation results related to repeated coefficient patterns. In this paper, we propose a signed sliding window method with side-channel resistance for NTRUEncrypt. The proposed method considers both positive and negative nonzero coefficients when constructing look-up tables. The new method not only accelerates convolution but also enables the application of power analysis countermeasures effectively. According to the experimental results, the constant-time implementation of the proposed method with timing and power analysis countermeasures accelerates the previously developed secure convolution method by up to 20%.

An Efficient Low-Latency Point-Multiplication Over Curve25519

The elliptic curve cryptography (ECC) has gained attention mainly due to its lower complexity compared to other asymmetric methods while providing the same security level. The most performance critical operation in ECC is the point multiplication. Thus, its efficient implementation is desirable. One of the most secure and lightweight ECC curves, which satisfies all standard security criteria, is the Curve25519. In this paper, a low latency Karatsuba-Ofman-based field multiplier (KOM) and an efficient point multiplication over Curve25519 have been proposed. The improvements have been achieved mainly due to the proposed low latency pipelined KOM and efficient scheduling of field operations. Moreover, an enhanced architecture exploiting a number of well-known differential power analysis (DPA) countermeasures have been implemented. To evaluate this work against the previous ones, FPGA has been exploited to implement the point multiplication architectures. The FPGA implementation results of the enhanced and regular architectures show at least 64% and 33% improvement in A s T ( $slice\_{}count \times time$ ) compared to those in the previous work, respectively. However, A d T ( $DSP\_{}count \times time$ ) metrics in both architectures seem to be similar to the previous work. Furthermore, the time complexity of both enhanced and regular architectures decreases 89% using Zynq-7020.

Automatic Application of Power Analysis Countermeasures

We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channels. This information is obtained either by dynamic analysis, evaluating an information theoretic metric over the power traces acquired during the execution of the input program, or by static analysis. As information leakage implies a loss of security, the compiler then identifies (groups of) instruction instances to protect with a software countermeasure such as random precharging or Boolean masking. As software protection incurs significant overhead in terms of cryptosystem runtime and memory usage, the compiler protects the minimum number of instruction instances to achieve a desired level of security. The compiler is evaluated on two block ciphers, AES and Clefia; our experiments demonstrate that the compiler can automatically identify and protect the most important instruction instances. To date, these software countermeasures have been inserted manually by security experts, who are not necessarily the main cryptosystem developers. Our compiler offers significant productivity gains for cryptosystem developers who wish to protect their implementations from side-channel attacks.

Research of Differential Power Analysis Countermeasures

Research of Differential Power Analysis Countermeasures

A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine

The differential power analysis (DPA) has become a big threat to crypto chips since it can efficiently disclose the secret key without much effort. Several methods have been proposed in literatures to resist the DPA attack, but they largely increase the hardware cost and severely degrade the throughput. In this brief, a security problem based on ring oscillators is resolved by a new architecture with self-generated true random sequence. The true random-based architecture is implemented with an Advanced Encryption Standard (AES) crypto engine using UMC 90-nm CMOS technology. The DPA-resistant AES engine can achieve 2.97-Gb/s throughput at an operating frequency of 255 MHz with a 0.104- cell area. The proposed DPA countermeasure circuit has only 6.2% area and 18.5% power overhead without throughput degradation.

An Efficient DPA Countermeasure for the EtaT Pairing Algorithm over GF(2n) Based on Random Value Addition

This paper presents an efficient differential power analysis (DPA) countermeasure for the pairing algorithm over GF(). The proposed algorithm is based on a random value addition (RVA) mechanism. An RVA-based DPA countermeasure for the pairing computation over GF() was proposed in 2008. This paper examines the security of this RVA-based DPA countermeasure and defines the design principles for making the countermeasure more secure. Finally, the paper proposes an efficient RVA-based DPA countermeasure for the secure computation of the pairing over GF(). The proposed countermeasure not only overcomes the security flaws in the previous RVAbased method but also exhibits the enhanced performance. Actually, on the 8-bit ATmega128L and 16-bit MSP430 processors, the proposed method can achieve almost 39% and 43% of performance improvements, respectively, compared with the best-known countermeasure.

Modified Doubling Attack by Exploiting Chosen Ciphertext of Small Order

Power analysis can be used to attack many implementations of cryptosystems, e.g., RSA and ECC, and the doubling attack is a collision based power analysis performed on two chosen ciphertexts. In this paper, we introduced a modified doubling attack to threaten RSA and ECC implementations by exploiting only one chosen ciphertext of small order. To attack the RSA implementations we selected an input of order two while to attack the ECC implementations we exploited one chosen invalid point of small order on a cryptographically weak curve rather than on the original curve. We showed that several existing power analysis countermeasures for RSA and ECC implementations are still vulnerable to the proposed attack. To prevent the proposed attack, we suggested countermeasures for RSA as well as for ECC.

Power Analysis Attacks and Countermeasures on ηT Pairing over Binary Fields

Since many efficient algorithms for implementing pairings have been proposed such as ηT pairing and the Ate pairing, pairings could be used in constraint devices such as smart cards. However, the secure implementation of pairings has not been thoroughly investigated. In this paper, we investigate the security of ηT pairing over binary fields in the context of side-channel attacks. We propose efficient and secure ηT pairing algorithms using randomized projective coordinate systems for computing the pairing.