Power Amplifier Prototype Research Articles

High-Efficiency RF Pulsewidth Modulation of Class-E Power Amplifiers

A new switch-mode power-amplifier (SMPA) topology particularly suitable for energy efficient amplification of RF pulsewidth modulation (RF-PWM) signals is derived. It is analytically shown that high efficiency can be maintained over a wide power dynamic range if the imaginary part of the Class-E load impedance is varied along with the duty cycle (pulsewidth). Using the theory developed, an explicit design procedure is presented that allows practical realization of the proposed topology from the circuit and component specifications. Following the design procedure, and using in-house (Chalmers University, Goteborg, Sweden) SiC varactor diodes to implement the tunable imaginary load impedance, a 2-GHz 10-W peak output power GaN HEMT circuit demonstrator is realized. RF-PWM input signals for characterization of the prototype power amplifier (PA) is generated with a dedicated 65-nm CMOS modulator. The measurements show that a drain efficiency >; 70% can be obtained over an 6.5-dB dynamic range, which verifies the theory presented and demonstrates the feasibility of the proposed PA topology.

Power Efficiency and Linearity Enhancement Using Optimized Asymmetrical Doherty Power Amplifiers

This paper investigates the virtues of the asymmetrical Doherty power amplifier (PA) for improving the average power efficiency, linearity, and peak envelope power. It commences with an in-depth study of the effects of increasing the size of the peaking amplifier's transistor and its conduction angle on the Doherty PA's RF performance. In particular, the impact of the extended current profile of the peaking amplifier and reduced turn-on effects on the soft-turn characteristic are thoroughly analyzed, and their impacts on the average efficiency and peak power are deduced. Furthermore, the aggravation of the memory effects that accompany the gm3-based nonlinear distortion cancellation is experimentally demonstrated. Two asymmetrical Doherty PAs prototypes are fabricated using 80 W and 150 W laterally diffused metal oxide semiconductor field-effect transistors to individually improve average efficiency and linearity. When driven with a four carrier wideband code division multiple access (4C-WCDMA) signal, the asymmetrical Doherty PA allowed for excellent drain efficiency of approximately 50%, along with high linearity of approximately -50 dBc , using a memory polynomial digital predistorter at an average output power of 50 W. To the best of the authors' knowledge, this achieved efficiency is the highest reported in the literature for a high-power Doherty PA implemented in LDMOS technology.

Analytical approach to optimise the efficiency of switching mode power amplifiers loaded with distributed matching networks

This study describes the design methodology of optimising the power-added efficiency (PAE) of switching mode power amplifiers (SMPAs). To maximise efficiency, design optimisation of the harmonic loading networks using an analytical analysis approach is proposed. Indeed, by carefully designing a distributed harmonic control network at the output of the SMPA, the insertion loss through the load network can be minimised. To validate the PAE optimisation approach, two 10 W inverse class F power amplifiers (PAs) were designed, manufactured and tested at a frequency of 2.45 GHz using a GaN HEMT transistor. The first PA prototype was matched with a standard distributed harmonic loading network and the second with the proposed distributed harmonic loading network. The measured PAE and gain for the second prototype were improved by 3% and 0.17 dB to reach 73% and 14 dB, respectively.

Concurrent dual-band SiGe HBT power amplifier for Wireless applications

This paper presents an investigation of a concurrent low-cost dual-band power amplifier (PA) fabricated in SiGe technology, able to simultaneously operate at two frequencies of 2.45 and 3.5-GHz, including an evaluation of its system level performance potentiality. Taking into account the technology novelty and the lack of device characterization and modeling, a hybrid (MIC) approach has been adopted both for a fast prototyping of the PA and for the evaluation of the device potentiality based on an extensive linear and nonlinear characterization. The comparison of PA performance in single-band or concurrent mode operation will be presented. In particular, the measured PA prototype shows an output power of 17.2 and 17-dBm at a 1-dB compression point, at 2.45 and 3.5-GHz, respectively, for CW single-mode operation, with a power added efficiency around 20%. System-level analysis predicts that, when the PA is operated under the 20-MHz Orthogonal Frequency-Division Multiplexing (OFDM) concurrent signals, the maximum output power levels to maintain the Error Vector Magnitude (EVM) within 5% are 11 and 3.5-dBm at 2.45 and 3.5-GHz, respectively. Moreover, new concepts and possible new system architectures for the development of the next generation of the multi-band transceiver front-end will be provided with an extensive system-level evaluation of the amplifier.

Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.

Load–Pull Wideband Class-E Amplifier

A new technique to design wideband Class-E power amplifiers (PAs) based on the synthesis of specific load admittances at fundamental and harmonics is shown. This technique symplifies the design of wideband Class-E amplifiers by making it independent on any specific load network, implementation, and intrinsic transistor output capacitance COUT. Simulations and actual measurements on a 15-W VHF wideband Class-E PA prototype designed using this method show 35% fractional bandwidth with 80% drain efficiency

8 GHz, 10 W solid-state power amplifier for microwave digital radio

An 8 GHz, 10 W GaAs FET prototype power amplifier has been developed to replace the TWT in the Northern Telecom's digital microwave radio system. For a single bit stream of 91.04 Mbit/s, the residual bit error rate at 40 dBm output level was 1.0×10−32 compared with 1.0×10−23 for TWT; the AM/AM conversion ratio was 0.375 dB/dB and AM/PM was 0.84°/dB. The total mean time between failure of the amplifier was 350 000 h.