Power Amplifier Cells Research Articles

Characterization and Analysis of Hot Carrier Degradation Under DC and Large-Signal RF Stress in a PDSOI Floating-Body NFET-Based Power Amplifier Cell Under WiFi Operating Conditions

This paper presents an extensive experimental analysis of hot carrier degradation (HCD) due to DC and large-signal RF stress on a power amplifier (PA) cell in the sub-7GHz frequency band. The reported PA cell is fabricated in a 45-nm RFSOI technology and consists of a single n-channel floating body partially depleted SOI FET. The impact of HCD on the class, conduction angle ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\theta $ </tex-math></inline-formula> ), and performance of the PA cell is analyzed under DC and large-signal RF stress conditions. Generation of defects and their types, i.e., whether oxide or interface traps, are understood using a combination of RF and DC stress conditions. Our detailed analysis distinguishes HCD mechanisms dominated by oxide and interface traps by studying time slope exponents, changes in the subthreshold swing, threshold voltage, and peak transconductance. The impact of RF stress on the PA cell lifetime is also extracted using a semiempirical model.

Superior mm-Wave Large Signal Power Amplifier Reliability of p-Type FET in a 45-nm Partially-Depleted Silicon-On-Insulator RF Technology

In this letter, we have explored the DC, small and large-signal RF reliability of the Power Amplifier (PA) cell for mm-wave applications under DC and RF stress. The PA cell comprises of a single transistor that employs 45RFSOI technology. For the first time here, a PA cell consisting of p-channel partially depleted Silicon-On-Insulator (PD-SOI) FET has been investigated for large-signal reliability behavior. At the same stress conditions, the impact of hot carrier degradation (HCD) on a p-channel FET (PFET) PA cell is also compared with the n-channel FET (NFET) PA cell. As the reliability of the PFET PA cell is superior than NFETs, a deeper investigation of hot carrier degradation and its impact on PA cell reliability is carried out. The PA cell is subjected to extensive RF characterization for varying DC stress and RF power at the gate terminal. The behavior of the time slope exponent of the PFET PA cell is studied to understand the nature of defects. Accelerated aging experiments using DC bias at drain/gate terminals and RF power at the gate terminal is performed. These results show that the RF reliability of the PFET PA cell is superior than its counterpart NFET PA cell at mm-wave frequencies.

A 60 GHz 8-Way Combined Power Amplifier in 0.18 μm SiGe BiCMOS

A 60 GHz fully-integrated 8-way combined power amplifier (PA) is developed in a standard 0.18 μm SiGe BiCMOS technology. The 8-way power splitter and combiner are co-optimized with transformer based baluns inside the eight differential PA cells, and hence resulting in minimum loss and high gain, linearity and efficiency. The measurement shows that the PA can achieve a gain of 22.2 dB around 60 GHz and 3-dB bandwidth from 53.5 GHz to 66.5 GHz, which covers all the channels specified in IEEE 802.11ad standard. It also attains a 1-dB power compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) of 21.8 dBm and saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> ) of 22.6 dBm, with power-added-efficiency of 10.7% and 12%, respectively.

A 28 GHz Single-Input Linear Chireix (SILC) Power Amplifier in 130 nm SiGe Technology

This article presents an integrated high-efficiency 28 GHz power amplifier (PA) employing a combination of Chireix outphasing and Doherty architectures in order to simultaneously achieve power back-off efficiency and linearity with a single RF input signal and no predistortion. The amplifier consists of a dual-input high-efficiency outphasing PA and a simple input network which serves as a power splitter and feeds the same signal to the inputs of the main and auxiliary PA cells that are biased in class-AB and class-C regions, respectively, similar to the Doherty architecture. The operation of the PA cells together with the Chireix combiner result in back-off efficiency enhancement plus systematic AM-AM and AM-PM variations which are used to correct the distortions caused by transistors, resulting in a linear response. The implemented PA demonstrates 19 dBm saturation power (Psat) with 34.4% peak power-added efficiency (PAE) and 6 dB back-off PAE of >23% at 27.5 GHz. The modulated signal performance using a 100 MHz 64QAM OFDM signal shows an average output power of 11.9 dBm with PAE >20%, EVM < 5%, and ACLR < −33 dBc without using predistortion.

A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement

This paper presents a subharmonic switching (SHS) digital power amplifier (PA) architecture that enhances power efficiency in the power back-off (PBO) region. The proposed technique can be combined with the class-G operation. By using either SHS or dual-power supply switching, it can provide several peak efficiency points, located at 0, -3.5, -9.5, and, -13 dB PBO. By judiciously choosing the optimal operation mode between SHS and dual supplies for each PA cell at different output power levels, we can further improve the efficiency between peaks. The SHS PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS to validate the effectiveness of the proposed technique, which achieves a 26.8-dBm peak output power with a 49.3% peak drain efficiency (DE) at 2.25 GHz and a 27% DE at -13-dB PBO.

A 280–310 GHz InAlAs/InGaAs mHEMT Power Amplifier MMIC with 6.7–8.3 dBm Output Power

This letter presents a broadband power amplifier (PA) millimeter-wave integrated circuit (MMIC) demonstrating 6.7-8.3-dBm measured output power from 280 to 310 GHz at -5-dBm input power. The measured small-signal gain is 15-20 dB for 266-330 GHz, which is the maximum frequency that could be measured. A dc power of 521 mW is required for this four-stage amplifier circuit using four cascode amplifier cells in parallel. The cascode PA cell is implemented with thin-film microstrip lines on the wafer front side using two two-finger devices with 10-μm finger width in parallel. Due to the compact cascode cell topology, the total gate width of 160 μm is realized requiring only 400 μm × 800 μm chipsize for the four-stage amplifier without pads. The reported output power represents the state of the art for mHEMT-based PA MMICs between 280 and 310 GHz.

Frequency Reconfigurable mm-Wave Power Amplifier With Active Impedance Synthesis in an Asymmetrical Non-Isolated Combiner: Analysis and Design

A frequency reconfigurable millimeter-wave (mm-wave) power amplifier (PA), which can be programmed to operate efficiently for a wide swathe of the spectrum, approaching an universal transmitter, can enable a wide range of novel applications in high-speed communication, sensing, and imaging. Classical techniques to allow large operating range either rely on broadband higher order output combining networks or tunable passives, both of which tradeoff directly with output power and efficiency. In this paper, we present an active impedance synthesis methodology that exploits the interaction of multiple unit PA cells in an asymmetrical non-isolated combiner to synthesize complex mm-wave impedances in a programmable fashion. This allows the interacting power cells to see their optimal load-pull impedances for high-efficiency frequency-reconfigurable operation in an efficient combiner network with no lossy variable passives. Compared to a symmetrical combiner, this enables the network to break the strong tradeoffs between output power, efficiency, and frequency reconfigurability, allowing it to achieve N times the Bode-Fano bound compared with an N-way symmetrical architecture. As a proof of concept, an integrated PA, which is in a 0.13-μm SiGe process, is demonstrated to achieve P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 23.6 dBm at a power-added efficiency (PAE) of 27.7% at 55 GHz with a frequency reconfigurable P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> , <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sub> dB bandwidth of 25 GHz (40-65 GHz) and a PAE, <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sub> dB bandwidth of 20 GHz (40-60 GHz). Multi-Gbps data rates are demonstrated with non-constant envelope modulations across the frequencies 40-60 GHz.

A Recursive Switched-Capacitor House-of-Cards Power Amplifier

A fully integrated CMOS power amplifier (PA) that efficiently generates high-voltage RF waveforms directly from a 4.8-V supply using only low-voltage thin-oxide transistors is introduced. High-voltage operation is achieved via implicit ~100% efficient dc–dc conversion enabled by stacking and flying individual class-D PA cells in a House-of-Cards (HoC) topology. By dynamically reconfiguring digitally controlled HoC slices to support different voltage conversion ratios and capacitively coupling their outputs, a Doherty-like high-efficiency backoff profile is achieved without using any magnetic impedance inverter. A test chip, implemented in 65-nm low-power CMOS, operates directly from 4.8 V using only 1.2-V transistors, and attains above 40% battery-to-RF efficiency at both 23-dBm peak power and at 6-dB backoff at 720 MHz. When applying a 10-MHz 16-quadrature amplitude modulation signal, the PA achieves an error vector magnitude of 3.6%-rms without using any predistortion techniques with an average output power and power-added efficiency of 15.7 dBm and 26.5%.

A Digital Polar CMOS Power Amplifier With a 102-dB Power Dynamic Range Using a Digitally Controlled Bias Generator

A digitally modulated CMOS power amplifier (DPA) for a polar transmitter with a high dynamic range is presented. To improve local oscillator (LO) leakage, which limits the minimum output power of the DPA, the unit amplifier cell of the DPA employs a balanced mixer-type LO canceller at the power stage and a virtual ground is introduced in the layout of the output-power combining networks. A high dynamic range of the output power is simply achieved by adjusting gate-bias voltage of a cascode transistor in each power amplifier (PA) cell using a digitally controlled bias generator. This architecture allows a few-mA drain current at a low Tx power level without degrading the linearity. An array of unit PA cells is segmented to have a 10-bit amplitude resolution, and the bias generator is designed to have 8-bit control of the average output power. The peak output power is 24.4 dBm with an overall efficiency of 43% at 800 MHz. The total output dynamic range is 102.8 dB. A simple static pre-distortion helps the DPA achieve an average efficiency of 35% with a root mean square error vector magnitude of 3.59% while delivering linear output power of 22 dBm for WCDMA. The range of the digital transmit-power control for the WCDMA signal is 49.7 dB. This chip is fabricated in a 65-nm RF CMOS process.