Power-added Efficiency Research Articles

GaN/SiC V-band 10 W high-power amplifier for inter-satellite communications

Abstract This manuscript presents a millimeter-wave GaN high-power amplifier (HPA) intended for next generation inter-satellite links (ISLs). The proposed architecture achieves a fractional bandwidth wider than 18% in the V-band spectrum, to deliver a 10 Gbit/s throughput compatible with multi-thousand-km ISLs. Core of the HPA is the monolithic microwave integrated circuits (MMIC ) power amplifier which covers the whole 59–71 GHz band with high efficiency through innovative topologies and a cutting-edge gallium nitride on silicon carbide (GaN-on-SiC) process. The MMIC is then parallelized by means of a 1-to-8 splitter/combiner to obtain a V-band 10 W GaN HPA. Measurement results show a peak small-signal gain of 25.6 dB, 6.5% peak power-added efficiency, and a maximum P1dB of 40.3 dBm.

Understanding and Quantifying the Benefit of Graded Aluminum Gallium Nitride Channel High-Electron Mobility Transistors

Graded AlGaN channel High-Electron Mobility Transistor (HEMT) technology is emerging as a strong candidate for millimeter-wave applications, as superior efficiency and linearity performances can be achieved. In this paper, graded channel AlGaN/GaN HEMTs are investigated with the aim of further understanding the benefit of the graded AlGaN channel compared to more conventional GaN channel HEMTs. Our study employed a comprehensive simulation workflow including an extensive calibration of direct current (DC), S-parameter, large signal, and linearity characteristics at 30 GHz. Through device modeling and implementation of circuit-level simulation using Advanced Design System (ADS, 2023) software, both linearity and large signal performances could be mimicked remarkably. In agreement with previous studies, the results show that graded channel technology allows for a modified electron confinement leading to a 3D electron gas (3DEG). Consequently, the electric field peak inside of the channel is reduced without degrading the radio frequency (RF) performance, as the electron velocity is improved, thus offering a more linear transconductance and better linearity performances. As a result, for graded AlGaN channel HEMTs, a 6 dB output power back-off from peak power-added efficiency (PAE) is needed to achieve a carrier with a third-order intermodulation (C/IM3) ratio of 30 dBc against 9 dB for conventional AlGaN/GaN HEMTs with a lower associated PAE.

A novel 5.1–7.1 GHz front-end power amplifier for wireless applications with [formula omitted] dB Error Vector Magnitude

A Power Amplifier (PA) is proposed for WiFi-6E applications, specifically designed to support WLAN 802.11ax standard to achieve significant linear power. The proposed PA is designed to operate in the entire 5 GHz and 6 GHz frequency bands. The design involves a two-stage configuration, initial stage adopts a linear driver, while the subsequent amplification stage is structured as a differential cascode. UMC 65 nm CMOS process technology is used to design a PA in commercial Cadence platform. The layout occupies core area of 0.24 mm2. Proposed PA delivers a power gain of 20 dB, Power Added Efficiency (PAE) of 19% and 1 dB compression point (P1dB) is of 24.5 dB is achieved for continuous wave (CW) signal. For the 802.11ax source, the recorded average power output (Pavg) is 17.1 dBm at an Error Vector Magnitude (EVM) ≤−35 dB, across the 5–7 GHz. The PA delivers Pavg of 10 dBm at worst corner case in PVT variation analysis. While the majority of recent works in WLAN PA confines the investigation to 5 GHz band, this paper broadens the scope by extending the study by up to 7.050 GHz in 6 GHz band. The incorporation of 6GHz band enables WiFi-6E to utilize up to 1,200 MHz of unencumbered spectrum, significantly enhancing the available bandwidth relative to earlier WiFi standards. The increased bandwidth facilitates high data rate applications, such as streaming and gaming.

Internally Harmonic Matched Compact GaN Power Amplifier with 78.5% PAE for 2.45 GHz Wireless Power Transfer Systems

In this paper, a high-efficiency compact power amplifier is designed and fabricated with a 0.25 μm GaN high electron mobility transistor (HEMT) to meet the demands of a high integration level and high efficiency for microwave wireless power transfer (WPT) systems. The proposed power amplifier (PA) is implemented using an internally matched method to achieve a compact circuit size. The output second and third harmonic impedances can be optimized through output matching circuits, eliminating the need for additional harmonic matching networks. This approach simplifies the design of matching circuits and reduces the circuit size. Furthermore, the input third harmonic has been controled for improving the efficiency of DC-to-RF conversion. The total size of the proposed PA is 13.4 × 13.5 mm2. The test results obtained from the continuous wave (CW) testing indicate that the output power of the power amplifier at 2.45 GHz reaches 43.75 dBm. Additionally, the large-signal gain is measured at 15.75 dB, and the power-added efficiency (PAE) achieves a value of 78.5%.

An active two-stage class-J power amplifier design for smart grid’s 5G wireless networks

<span>The wireless communication networks in the smart grid’s advanced metering infrastructure (AMI) applications need 5G technology to support large data transmission efficiently. As the 5G wireless communication network’s overall bandwidth (BW) and efficiency depend on its power amplifier (PA), in this work, a two-stage class-J power amplifier’s design methodology that operates at 3.5 GHz centre frequency by utilizing the CGH40010F model gallium nitride (GaN) transistor is presented. The proposed design methodology involves proper designing of input, output, and interstage matching networks to achieve class-J operation with improved power gain over desired BW using the advanced design system (ADS) electronic design automation (EDA) tool and estimating its integration feasibility through active element-based design approach using the Mentor Graphics EDA tool. The proposed PA provides 54% drain efficiency (D.E), 53% power added efficiency (PAE) with a small signal gain of 27 dB at 3.5 GHz and 41 dBm power output with 21 dB of improved power gain across a BW of around 400 MHz using 28 V power supply into 50 Ω load. By replacing the two-stage PA's passive elements with active elements, its layout size is estimated to be (15.5×29.2) μm2 . The results of the proposed PA exhibit its integration feasibility and suitability for the smart grid’s 5G wireless networks.</span>

A 60 GHz Power Amplifier with Neutralization Capacitors and Compensation Inductors

In this paper, we present a high power-added efficiency (PAE) and high gain per stage 60 GHz power amplifier (PA). The proposed PA consists of a two-stage common-source amplifier that incorporates neutralization capacitors and compensation inductors to enhance both gain and efficiency. The gain characteristics are analyzed, demonstrating that the proposed design improves both gain and efficiency. Implemented in 65 nm CMOS technology, the PA achieves a saturated output power of 13.4 dBm at 60 GHz, with a maximum PAE of 26.7% from a 1 V supply. The output 1 dB compression point is 10.5 dBm, with a PAE of 16%. The PA occupies a core chip area of 0.094 mm2.

23.5–27.5 GHz Band Doherty Power Amplifier Integrated Circuit Using 28 nm Bulk CMOS Process Based on Dynamic Power Dividing Network

This paper presents a Doherty power amplifier (DPA) integrated circuit (IC) designed to have enhanced gain, efficiency, and AM-AM characteristics through a dynamic power dividing technique, which can control the power dividing ratio according to the input power. Since this multi-purpose dynamic power dividing network also provides the phase offset and impedance matching at the interstage network needed for appropriate DPA operation, the active IC area could be reduced. To verify the proposed technique and its analysis, the DPA was implemented with a 28 nm bulk CMOS process for the fifth-generation (5G) new radio (NR) millimeter-wave frequency band of 23.5–27.5 GHz. The measured results showed a gain of 20.3–21.9 dB, saturated output power of 14.0–15.2 dBm, power added efficiency (PAE) of 22.8–26.7% at the peak power, and PAE of 14.6–17.6% at the 6 dB output power back-off (OBO).

A High Efficiency Broadband Gallium Nitride Power Amplifier with Harmonic Control technology

ABSTRACT In order to meet the requirements of high efficiency and broadband for the wireless communication system, a high efficiency and broadband gallium nitride power amplifier (PA) is designed and verified. Using the step-matching structure, its bandwidth has been improved. Furthermore, its input matching network is constructed by connecting several microband lines serially to reduce the matching Q value. Meanwhile, the harmonic control network is designed as the output matching network, which is built by a quarter-wave (λ/4) line open circuit and short circuit microwave lines in parallel. Thus, its drain efficiency (DE)can be improved. This design is simulated and tested at 2.2–3 GHz with the gallium nitride (GaN) process. After measuring, it attains an output power (Pout) of 39.5–41.5 dBm, Gain of 10.5–12.5 dB, DE of 65.1%–78.3% with power added efficiency (PAE) of 64.8%–76.2%.

The degradation mechanism of high power S-band AlGaN/GaN HEMTs under high temperature

Abstract The radio frequency (RF) degradation mechanism under high temperature is proposed in this paper. The saturated output power (P sat), power added efficiency (PAE) and gain of the HEMTs deteriorate significantly under high power dissipation operation conditions, which contribute to an elevation of the junction temperature (T j). The high T j causes a negative shift of the threshold voltage and a reduction of electron mobility, as well as enhancing the trapping effects of the devices. As a result, the P sat and PAE of the high-power HEMTs (P sat = 152 W) decreased by 0.76 dB and 8.3%, respectively, which is more severe compared to low-power HEMTs (P sat = 20 W), where P sat and PAE reduced by 0.16 dB and 3.1% when the operation temperature was increased from 25 °C to 150 °C. By increasing the gate-to-drain distance from 1.625 to 2.175 μm, drain current stability and high temperature reverse bias reliability are improved. The results demonstrate that the trapping effect can be suppressed by decreasing the electric field under the gate; therefore, the RF output characteristics are boosted by 1.2 W, 1 dB and 2.6% for a device with gate width of 11.52 mm.

Smith Chart-Based Design of High-Frequency Broadband Power Amplifiers

This paper presents a comprehensive study on the design and performance of a high-power amplifier (PA) covering a broad frequency band from 0.1 to 4.8 GHz. Leveraging a 10 W GaN device, the amplifier achieves output power levels surpassing 10 W across the entire frequency band. Furthermore, the power-added efficiency (PAE) of the amplifier ranges from 47% to 59%, indicating its energy-efficient operation. With consistent gain characteristics varying between 7 and 15 dB, the design ensures reliable signal amplification for diverse applications. Notably, the approach introduces a simplified output matching network based on an LC network, prioritizing practicality without sacrificing performance. Additionally, comprehensive guidance is provided on utilizing the Smith chart for streamlined amplifier design, enabling engineers with an accessible methodology. Through a meticulous analysis, this work contributes to advancing the field of high-power amplification, offering enhanced performance and usability for next-generation wireless communication systems.

INCAPE23-Design of Class E CMOS Power Amplifier with Integrated Active Inductor for 5G Applications

This paper presents a design of class E power amplifier (PA) with integrated active inductor for 5G applications. A high Q-factor active inductor (AI) is proposed utilizing CMOS 0.18-µm technology. A Gyrator-C based is employed to realize an active inductor with a double cascode resistive feedback configuration. The biasing voltage of 1.21 V, current source of 0.5 mA and supply voltage of 2.5 V is used. In order to obtain high efficiency, the proposed AI is implemented in a class E power amplifier by replacing on of the spiral inductors. According to the simulation results, the proposed AI can reach a high Q-factor of 50,000 and an inductance of 2.03 nH at 3.5 GHz. The power added efficiency (PAE) of CMOS class E PA with integrated AI, according to simulation result, is 72 % at 3.5 GHz. The intended PA's PAE was dramatically raised by the class E AI that was built.

A 132–170 GHz high-gain driving amplifier utilizing asymmetric broadside coupled line in 40-nm CMOS

This paper presents a driving amplifier (DA) utilizing the proposed asymmetric broadside coupled line. In contrast to conventional coupled line, the balun devised with proposed asymmetric coupled line and enhanced wideband balance compensation technique is utilized, thereby achieving wideband impedance matching and mitigating insertion loss. Additionally, the utilization of the lossy over-neutralization technique substantially enhances the power gain of amplifiers operating in the upper millimeter-wave band (150 GHz–300 GHz). The DA is fabricated utilizing a 40-nm CMOS process without aluminum layers. The fabricated amplifier demonstrates a compact total area of 0.135 mm2 (0.031 λ2), with a core area of 0.027 mm2 (0.0061 λ2). It achieves a high gain of 19.4 dB, high power of 11.05 dBm, and high power-added efficiency (PAE) of 11.05% at 160 GHz. Moreover, both the 3-dB power gain bandwidth and the 3-dB saturated power bandwidth extend from 132 GHz to 170 GHz, covering a bandwidth of 38 GHz. This configuration underscores the robust performance of the DA in the upper millimeter-wave band.

Improved DC and RF Characteristics of GaN-Based Double-Channel HEMTs by Ultra-Thin AlN Back Barrier Layer.

In order to improve the off-state and breakdown characteristics of double-channel GaN HEMTs, an ultra-thin barrier layer was chosen as the second barrier layer. The strongly polarized and ultra-thin AlN sub-barrier and the InAlN sub-barrier are great candidates. In this article, the two epitaxial structures, AlGaN/GaN/AlN/GaN (sub-AlN) HEMTs and AlGaN/GaN/InAlN/GaN (sub-InAlN) HEMTs, were compared to select a more suitable sub-barrier layer. Through TEM images of the InAlN barrier layer, the segregation of In components can be seen, which decreases the mobility of the second channel. Thus, the sub-AlN HEMTs have a higher output current density and transconductance than those of the sub-InAlN HEMTs. Because the high-quality AlN barrier layer shields the gate leakage current, a 294 V breakdown voltage was achieved by the sub-AlN HEMTs, which is higher than the 121 V of the sub-InAlN HEMTs. The current gain cut-off frequency (fT) and maximum oscillation frequency (fmax) of the sub-AlN HEMTs are higher than that of the sub-InAlN HEMTs from low to high bias voltage. The power-added efficiency (PAE) and output power density (Pout) of the sub-AlN HEMTs are 57% and 11.3 W/mm at 3.6 GHz and 50 V of drain voltage (Vd), respectively. For the sub-InAlN HEMTs, the PAE and Pout are 41.4% and 8.69 W/mm, because of the worse drain lag ratio. Thus, the Pout of the sub-AlN HEMTs is higher than that of the sub-InAlN HEMTs.

An enhanced broadband class-J mode power amplifier for 5G smart meter applications.

Background: With the tremendous increase in the usage of smart meters for industrial/ household purposes, their implementation is considered a crucial challenge in the Internet of Things (IoT) world, leading to a demand for emerging 5G technology. In addition, a large amount of data has to be communicated by smart meters efficiently, which needs a significant enhancement in bandwidth. The power amplifier (PA) plays a major role in deciding the efficiency and bandwidth of the entire communication system. Among the various modes of PAs, a newly developed Class-J mode PA has been proven to achieve high efficiency over a wide bandwidth by maintaining linearity. Methods: This paper proposes a Class-J mode PA design methodology using a CGH40010F-GaN device that operates at a 3.5 GHz frequency to meet the requirements of 5G wireless communication technology for the replacement of existing 4G/LTE technology used for advanced metering infrastructure (AMI) in smart grids. This research's main objective is to design the proper matching networks (M.Ns) to achieve Class-J mode operation that satisfies the bandwidth requirements of 5G smart grid applications. With the target impedances obtained using the load-pull simulation, lumped element matching networks are analyzed and designed in 3 ways using the ADS EDA tool. Results: The simulation results reveal that the proposed Class-J PA provides a maximum drain efficiency (D.E) of 82%, power added efficiency (PAE) of 67% with 13 dB small-signal gain at 3.5 GHz, and output power of 40 dBm (41.4 dBm peak) with a power gain of approximately 7 dB over a bandwidth of approximately 400 MHz with a 28 V power supply into a 50 Ω load. Conclusion: The efficiency and bandwidth of the proposed Class-J PA can be enhanced further by fine-tuning the matching network design to make it more suitable for 5G smart meter/grid applications.

A computational analysis of the impact of thin undoped channels in surface-related current collapse of AlGaN/GaN HEMTs

Abstract This study provides an insight into the impact of thin purely undoped GaN channel thickness (t ch) on surface-related trapping effects in AlGaN/GaN high electron mobility transistors. Our TCAD study suggests that in cases where parasitic gate leakage is the driving trapping mechanism that promotes the injection of electrons from the Schottky gate contact into surface states, this effect can be alleviated by reducing t ch of the undoped GaN channel. We show that by decreasing t ch from 130 to 10 nm, devices exhibit a reduction in gate-related current collapse under the specific class-B RF operating bias conditions as a consequence of a substantial decrease in the off-state gate leakage with reducing t ch. Large-signal simulations revealed an increase by 3 W mm−1 and about 12% output power and power-added efficiency due to the decrease of gate-related collapse. This work, for the first time, highlights the role of a proper purely undoped GaN t ch selection to alleviate gate-related surface trapping in the design of GaN-based microwave power amplifiers.

Multi-switch-controlled multi-mode TRFE with a high-linearity ATRSW for 2.4-GHz ISM applications

This paper presents a multi-switch-controlled multi-mode transceiver front end (TRFE) designed for the 2.4-GHz industrial–scientific–medical (ISM) band, with a particular focus on enhancing the linearity of the transmit/receive switch (TRSW) on the antenna side. Considering the distinct power levels in the RX/TX paths, the TRSW is designed to be asymmetric. This design not only elevates IP-0.1dB by over 50 % compared to the conventional symmetric topology, but also absorbing its function into the input matching network (IMN) of the low noise amplifier (LNA), thereby minimally impacting the noise figure (NF) of the RX chain. For the TX path, the high-pass component of the power amplifier (PA) output matching network (OMN) is repurposed, with a singular inductor being redeployed to serve as an inductive ESD safeguard. Moreover, the driving stage employs a passive gain-boosting technique, which elevates the gain by 3 dB compared to the traditional cascode structure. For verification, this TRFE is fabricated in 0.18-μm CMOS with a die size of 1.53 mm2. It achieves a NF of 2.4 dB and a RX gain of 16.7 dB under a 3.3-V supply. A TX gain of 26.2 dB and a saturation output power of 23.3 dBm with a peak power-added efficiency (PAE) of 38.8 % are also demonstrated.

On-state performance enhancement of AlGaN/GaN Fin-HEMTs by using arcuate sidewalls

In this study, AlGaN/GaN Fin-HEMTs with different nanochannel geometric parameters were fabricated and comprehensively characterized. In the arcuate Fin-HEMTs, where the sidewalls arcuate from the source to the drain side, enhancements in the drain current density and transconductance were observed. By extracting and analyzing parameters obtained from small-signal measurements and conducting an analysis of gate capacitance, it was demonstrated that the enhancement can be attributed to the modulation of gate capacitance. This enhances the control capability of the gate over channel carriers, resulting in increased transconductance of the device. Due to the enhanced transconductance, the fT and fmax of the arcuate Fin-HEMTs are both enhanced. Notably, the arcuate Fin-HEMTs achieved a power-added efficiency of 71.4% at a frequency of 3.6 GHz and a drain voltage of 20 V. Meanwhile, the linearity of the arcuate Fin-HEMTs is improved compared with the conventional Fin-HEMTs.

High-power and efficiency W-band InAlGaN/AlN/GaN high-electron-mobility transistors for future high-capacity wireless communications

This study describes high-power and high-efficiency W-band InAlGaN/AlN/GaN high-electron-mobility transistors (HEMTs) for future sub-terahertz wireless communications. A low-thermal-budget selective-area growth (SAG) process was developed to obtain low contact resistance with low trap states. Transmission lines and substrate structures were optimized to obtain high-thermal conductivity and low substrate resonance. Consequently, a high output power of 28.7 dBm (742 mW), output power density of 4.6 W mm−1, and power-added efficiency (PAE) of 28.0% were achieved with pre-matched InAlGaN/AlN/GaN HEMTs at 90 GHz, which were superior combination of output power and PAE compared to the conventional high-temperature SAG process.

Inverse Class‐E power amplifier with broadband capability at different switch‐off duty ratio

AbstractThe paper explores the investigation of an inverse Class‐E amplifier featuring a series output filter across various switch‐off duty ratios D. Analysis of different duty ratios as a design parameter reveals their impact on peak switch voltage, output power capability, and maximum operating frequency. Notably, it is demonstrated that adjusting the D ratio affects these parameters, with specific emphasis on achieving a maximum normalized switch voltage lower than 2 and an output power capability exceeding 0.1 for D = 0.7. Furthermore, the paper considers both parasitic shunt capacitance and series inductor in the load network, a departure from previous works that solely focused on the series inductor. The proposed circuit is highlighted for its ease of implementation compared with conventional reactance compensation circuits employing parallel resonant circuits, which are challenging to form directly. An innovative approach is introduced to showcase the broadband performance of the inverse Class‐E amplifier. The measured drain efficiency and output power versus input power at 430 MHz are 82% and 45.3 dBm, respectively. A similar performance can be achieved within the frequency range of 380–600 MHz by proper tuning at saturated power. The measurement results demonstrate a maximum high power‐added efficiency (PAE) of 79% and drain efficiency of 82% within this frequency range, accompanied by a gain exceeding 12.0 dB and output power surpassing 44 dBm.

Compact Internally Matched High-Power Power Amplifier with a Wide Frequency Band of 0.8–2 GHz

In this paper, a GaN high-electron-mobility transistor (HEMT) compact high-power wide-band power amplifier with an operation frequency from 0.8 GHz to 2 GHz is proposed. In order to realize a compact design, an internally matched method is employed. A wide-band matching strategy with an LC network and a multi-stage wide-band power combiner/divider is introduced in this design to achieve a wide bandwidth. A power combination structure is applied to have high output power. Wire-spiral inductance and film capacitors are employed to construct the compact matching network. The equivalent inductance of the bonding wire is also involved in the matching network. Experimental results show that the PAE (power-added efficiency) during the whole operation’s bandwidth (0.8 GHz to 2.0 GHz) is from 40% to 57%. The output power can reach from 48.3 dBm to 49.8 dBm with a circuit size of 30.8×27.4mm2.