Potential-induced Degradation Stress Research Articles

Method to Study Potential‐Induced Degradation of Perovskite Solar Cells and Modules in an Inert Environment

The efficiency of perovskite solar cells (PSCs) is advancing rapidly, yet their sensitivity to ambient conditions poses challenges. An additional degradation mechanism, potential‐induced degradation (PID), can emerge during field operation, but the understanding of PID within perovskite devices is limited. To exclude environmental stressors, this study is conducted in an inert environment at room temperature. PSCs and mini‐modules are subjected to a 324 h PID stress test at −1000 V, revealing relative efficiency losses of around 29% and 24% for the PSCs and mini‐modules, respectively, exposing subtle degradation differences. These degradation rates are notably lower than reported in the literature, suggesting possible additional degradation pathways arising from suboptimal encapsulation combined with ambient conditions. Subsequently, half of the stressed samples are subject to +1000 V for 523 h and recover to a reduced efficiency loss of 15% and 7.7% for the PSCs and module, respectively. In contrast, storing the stressed samples on the shelf increased the efficiency losses to 32% (PSCs) and 41% (module). Therefore, the post‐PID rates differ significantly between both groups, whereas both effects of voltage recovery and progressed degradation are more pronounced in modules compared to cells. This study contributes to a robust method for PID research.

Mitigation of Potential‐Induced Degradation in Glass‐Encapsulated Perovskite Solar Cells Using a NiOx Barrier Layer

While the efficiency of perovskite solar cells has been increasing rapidly in recent years, studies on potential‐induced degradation (PID) in these devices have so far been very limited. Herein, the first successful mitigation of PID in glass‐encapsulated perovskite solar cells is reported. A thin NiOx blocking layer between the indium tin oxide and the self‐assembled monolayer is proposed to suppress the PID in these solar cells. Two groups of devices are fabricated, with and without the presence of the NiOx layer. When −1000 V is applied between the short‐circuited solar cell and the front glass pane, the original devices without NiOx only retain about 27% of the initial efficiency, and the modified devices with NiOx retained ≈65% after an extended stress duration of 96 h. The Na+ ions from the glass pane occupy NiOx vacancies under high voltage stress and, as a result, the Nax ion migration toward the perovskite layer is heavily suppressed due to the introduction of NiOx. The modified devices also demonstrate good long‐term stability, retaining more than 80% of initial efficiency after the PID stress test. The results of this work are helpful on the journey toward successful commercialization of perovskite solar cells.

Second-stage potential-induced degradation of n-type front-emitter crystalline silicon photovoltaic modules and its recovery

We investigate the second-stage potential-induced degradation (PID) of n-type front-emitter (n-FE) crystalline silicon (c-Si) photovoltaic (PV) modules. The PID of n-FE c-Si PV modules is known to occur in three stages under negative bias stress. The second-stage PID is characterized by a reduction in fill factor (FF), due to the invasion of sodium (Na) into the depletion region of a p+–n junction and the resulting increase in recombination current. The second-stage PID shows a curious independence from a negative bias voltage for the PID stress. This may indicate that the Na inducing the FF reduction comes not from the cover glass but originally existed on and/or near the cell surface. The FF reduction is recovered quite rapidly, within a few seconds, by applying a positive bias to the degraded cell. The recovered n-FE c-Si PV modules show more rapid degradation if they receive the negative bias stress again, which can be explained by Na remaining in the p+ emitter.

Impact of different backsheets and encapsulant types on potential induced degradation (PID) of silicon PV modules

Photovoltaic (PV) modules during field exposure are subject to many durability and reliability issues, such as potential induced degradation (PID). The shunting type PID (PID-s) can significantly affect module performance. Most of the current studies on PID-s focus on understanding its mechanisms and mitigating its effects by modifying the glass, cell, or encapsulant component. Since the backsheet type influences the water vapor transmission rate, the conductivity of the encapsulant is significantly influenced by the backsheet type, and hence the level of voltage drop in the encapsulant layer during the PID stress test. The higher the conductivity of the encapsulant, the lower the voltage drop in the encapsulant and the worse the PID. Therefore, in the current work, the influence of four different backsheet types (PVF, PVDF, PA, ECTFE) and two different encapsulant types (EVA and POE) on PID is investigated. With multiple construction combinations of these materials, a set of 1-cell modules were fabricated and stressed for PID using an environmental chamber at −1000 V and 85 °C/85 %RH for 288 h. The performance and defect level changes were obtained using several pre- and post-stress characterizations, including IV and EL. The results indicate a power degradation in the range between 0 % and 9 %, depending on the backsheet-encapsulant combination. The results of this study are pertinent to understanding the influence of substrate relative to PID in PV modules. Moreover, these results can also help the manufacturers to select the best backsheet-encapsulant combination to minimize the persisting PID issues in the field.

Monitoring the natural recovery of potential induced degradation in poly-crystalline photovoltaic modules

Potential induced degradation (PID) is a defect that has a severe effect on the performance of photovoltaic (PV) modules in field conditions. It is caused by leakage currents and the accumulation of sodium ions (Na+) between the anti-reflective coating and the encapsulation. In the experiment reported on here, PID was artificially induced through a PID stress test, where the surface of a poly-crystalline p‑type module was covered with an aluminium sheet connected to the positive terminal of a high voltage power supply (1000 V), while the short-circuited module terminals was biased to the negative terminal. This stress test was applied to two similar poly-crystalline p‑type modules, A and B, for 48 hours and 20 hours respectively. The duration of the stress test determines the degree of PID severity induced. The length of the test resulted in Module A’s power decreasing by 88% and Module B’s by 40%. Electroluminescence and current-voltage measurements were taken at regular intervals over a period of more than a year to monitor the natural recovery of the modules. These measurements show that the natural recovery of severe PID modules is possible, but slow. After the test period, the maximum power of Module A and Module B had recovered to 63% and 96% of the original level. PID experienced in the field is generally less severe than for the modules in this study, so PID recovery could be achieved by adopting a process of setting affected strings at open-circuit in turns.

Suppression of potential-induced degradation in monofacial PERC solar cells with gradient-designed capping layer

The potential-induced degradation (PID) of p-type crystalline silicon passivated emitter and rear cell (PERC) is a critical issue causing severe output power loss. In this paper, a gradient-designed capping layer consisting of silicon nitride/silicon oxynitride/silicon oxide (SiNx/SiNxOy/SiOx) is proposed as the surface coating for p-type PERC solar cells. The capping layer improves the short wavelength spectral response due to its better anti-reflection effect. An impressive efficiency of 23.52% has been achieved on mass production line. A long-term PID evolution up to 672 h is performed for glass/back sheet PERC cell modules under stringent conditions with the ambient temperature of 85 °C, relative humidity of 85%, and the applied voltage of 1500 V. The current–voltage (light I-V, dark I-V) parameters of the modules were measured, as well as the electroluminescence, to evaluate the effect of sodium ion migration in PERC solar cells. It is shown that monofacial PERC solar modules suffer from shunt of PN junction under PID stress, which can be obviously suppressed by gradient-designed capping layers. The optimized PERC solar modules show excellent PID resistance, showing great potential for lower levelized cost of energy (LCOE) of photovoltaic power generation.

Accelerated stress testing of potential induced degradation susceptibility of PV modules under different climatic conditions

Potential Induced Degradation (PID) is one of the severe failure modes observed in the field with high system voltage, high humidity and high operating temperature. PV module needs to be tested for PID susceptibility as per site conditions before installation in the field. In this paper the effect of temperature, humidity, and voltage on leakage current, as well as PID, has been analyzed for multi-crystalline silicon and HIT module technologies. Also, reported the effect of PID stress on PV modules in terms of electrical degradation and visual defects. For the studied multi-crystalline module, deviation of degradation between one cycle and three cycles of PID stress for the Isc is 98%, Voc is 18% and Pmax degradation is 87%. This paper also reported a case study about the designing of accelerated stress testing of the PID of the PV module for different climatic zones of India. The stress testing condition was designed at harsh conditions of temperature and humidity for representative sites of climatic zones. It was found that the required testing time for PV module in the case of Hot & humid climatic zone is more as compared to other climatic zones.

Unraveling the cause of degradation in Cu(In,Ga)Se2 photovoltaics under potential induced degradation

AbstractCopper indium gallium diselenide (CIGS) based technology is actively competing in the global photovoltaic market with high conversion efficiency. Commercial CIGS modules are anticipated to perform on rated output in the field condition for 20 years. Potential induced degradation (PID) is considered as one of the critical concerns among all the current reliability assessment issues. PID accelerated tests have been performed on pre‐commercial CIGS modules to investigate reduction in electrical performance. We report the severe reduction in electrical performance after PID is correlated to the microstructural and chemical properties of the constituent materials. Under extreme PID stress, the cell surface reveals various defects including crater formation. The aim of this article is to explore the consequences of PID induced craters on the efficiency of CIGS solar cells by investigating material degradation kinetics. In this perspective, we present the root cause of PID in CIGS thin‐film modules in relation to microstructural defects by detailed investigation using J‐V analysis, field emission scanning electron microscope (FESEM), Raman spectroscopy, X‐Ray diffraction (XRD), X‐ray photoelectron spectroscopy (XPS) and photoluminescence spectroscopy (PL). This analysis can provide more effective and sustainable research strategies to cultivate more efficient and reliable CIGS technologies in the long run.

Temperature coefficient of the characteristic values of the charge-accumulation-type potential-induced-degraded n-type mono-crystalline silicon photovoltaic cell

Herein, the potential-induced degradation (PID) phenomenon, which can be attributed to charge-accumulation in Si photovoltaic cells, is investigated. This is achieved by performing temperature dependence measurements of the characteristic values of an n-type mono-crystalline Si photovoltaic cell, after being subjected to PID stress. The results indicate that after 7 h of PID stress, the open-circuit voltage Voc, short-circuit current density, maximum power density Pmax, and fill factor (FF) decrease by approximately 5%, 11%, 16%, and 0.7%, respectively, and eventually stabilize. The temperature coefficient (TC) of Pmax decreases from −0.413% °C−1 to −0.471% °C−1 after 7 h of PID stress and then stabilizes. These results can be explained by the fact that the charge-accumulation-type PID stress does not affect the p–n junction. It only affects the passivation layer of the cells. Thus, before and after the PID stress, the TC of Pmax is mainly determined by the TC of Voc and FF.

Detection of Potential Induced Degradation in mono and multi-crystalline silicon photovoltaic modules

Potential induced degradation (PID) is a performance limiting defect that profoundly impacts the power output of Photovoltaic (PV) modules. PID occurs because of leakage current between the solar cells and the aluminium frame. The leakage current develops due to high potential difference between the string voltage and the ground. In this work, PID is induced in a mono-crystalline and a multi-crystalline module and the severity is determined by current-voltage (I–V) measurements and Electroluminescence (EL) imaging. The Power dropped by 12.6% and 18.7% after 96 h of PID stress. The extracted parameters from the I–V curves show that the shunt resistance decreases and series resistance increases after the induction of PID. EL imaging was done at 10% of short circuit current (Isc) (low injection levels), manifesting as checkerboard like intensity distribution and distinct bimodal intensity histogram. The results of this study demonstrate different PID detection characterisation techniques in PV modules.

Potential-Induced Degradation Depends on Leakage Current and Light/Electrical Bias in Cu(In,Ga)Se2 Devices

Potential-induced degradation (PID) of encapsulated Cu(In,Ga)Se2 (CIGS) solar cells was studied for different substrates: soda-lime glass (SLG), SLG with an Al2O3 diffusion barrier, and borosilicate glass (BSG). The Al2O3 and BSG samples increased the time to PID failure by 5x and 30x, respectively. The relationship between PID and coulombs transferred from the substrate to the device through leakage current differed depending on the sample type. When the (unrepresentative) dark PID stress test was interrupted to characterize devices with light/electrical bias, PID was partially reversed. In addition, applying high voltage stress to open-circuit devices was less damaging, relative to forward-biased and short-circuited cells. Light/electrical bias may therefore reduce PID by driving alkali metal cations away from the p-n junction to diminish their degrading effects. These results show that device light/electrical bias should be carefully controlled during CIGS PID testing, as it affects PID in addition to leakage current.

Temperature dependence of potential-induced degraded p-type mono-crystalline silicon photovoltaic cell characteristics

In this paper, the temperature dependence of the characteristic parameters for a p-type mono-crystalline silicon photovoltaic cell before and after a potential-induced degradation (PID) stress, is measured and compared. It is demonstrated that a 9 h PID stress causes both a drastic decrease in the value of shunt resistance by ∼35 times and a decrease in the open-circuit voltage, Voc by ∼34%. Consequently the maximum power density, Pmax is decreased by ∼62%. The temperature coefficient (TC) of Pmax increases from −0.459 to −0.330 caused by a 0 to 3 h PID stress and then decreases to −0.471%/°C caused by a 3 to 9 h PID stress. Before PID stress, the TC of Pmax was determined mainly by the TC of Voc. However, after PID stress, the TC of Pmax was determined both by the TCs of Voc as well as by the fill factor.

Microstructural Analysis of Local Silicon Corrosion of Bifacial Solar Cells as Root Cause of Potential‐Induced Degradation at the Rear Side

Industrial bifacial PERC solar cells show a new type of potential induced degradation (PID) at the rear side. After PID stress, cells exhibit power losses about 12 %rel. The origin of the losses is traced back to a local silicon corrosion, forming hole shaped damages within the passivation layers at the rear side. More details can be found in article number 1900334 by Kai Sporleder, Christian Hagendorf, and co-workers.

Physics of potential-induced degradation in bifacial p-PERC solar cells

The combination of increasing operational voltages beyond 1000 V in photovoltaic (PV) installations and the emergence of new PV technologies requires a critical assessment of the susceptibility to potential-induced degradation (PID). Since this failure mode can trigger significant and rapid power losses, it is considered among the most critical failure modes with a high financial impact. Insights in the physical mechanism of the performance loss and its driving factors are critical to develop adapted characterization methods and mitigation solutions. PID in p-type solar cells is triggered by sodium (Na) that diffuses into stacking faults of the silicon lattice, causing shunt paths through the pn-junction. In addition, it is hypothesised that for bifacial p-PERC solar cells positive charges, such as Na+, accumulate in/on the negatively charged AlOx rear passivation layer due to the potential difference between the glass and the rear cell surface. This significantly increases surface recombination. However, the degradation behaviour observed in bifacial monocrystalline p-PERC solar cells under PID stress from both sides (bifacial PID stress) does not match with just one of the degradation mechanisms. A comprehensive test matrix was carried out to understand the physical origin of PID in front emitter bifacial p-PERC solar cells in a glass/glass packaging. The results show that bifacial p-PERC solar cells under bifacial PID stress suffer from both shunting of the pn-junction and increased surface recombination at their rear side. Hereby, we prove that the glass/glass packaging in combination with bifacial solar cells can significantly increase the severity of PID.

Influence of sodium on the potential-induced degradation for n-type crystalline silicon photovoltaic modules

We precisely investigate sodium (Na)-induced potential-induced degradation (PID) in n-type front-emitter (n-FE) crystalline silicon (c-Si) photovoltaic (PV) modules, in which open-circuit voltage (Voc) and fill factor deteriorate. Secondary ion mass spectrometry shows Na introduction into n-FE cells by a negative-bias PID stress and a reduction in Na density by positive-bias application. Scanning electron microscopy and energy dispersive X-ray analysis reveal the formation of Na-based protrusions on the cell surface. Silicon nitride (SiNx) disappears at the position of protrusions, which is the root cause for the serious and unrecoverable PID of n-FE c-Si PV modules.

Analysis of Potential-Induced Degradation in Soda-Lime Glass and Borosilicate-Glass Cu(In,Ga)Se2 Samples

Potential-induced degradation (PID) is investigated in small-size Cu(In,Ga)Se2 (CIGS) submodules of individual cells. Samples with conventional soda-lime glass (SLG) and low-alkaline glass (borosilicate glass, BSG) were analyzed applying positive and negative 1000 V bias at 85 °C and low relative humidity after a heat-soaking phase. During the heat-soaking phase, BSG samples showed degradation, with variations in their dark current–voltage ( I–V ) curve parameters compared with the stability of SLG samples. During the PID stress phase, back-grounded SLG samples with −1000 V applied to the cell experienced fast degradation, with complete failure in 25 h, whereas, BSG samples only showed changes because of the dark heat environment. When grounded on their front face, SLG samples remained stable during more than 150 h of PID testing, beginning degradation after longer applications of stress. The analysis of the dark I–V curves of SLG samples through the single-diode model showed that an increase in saturation current J 0 occurs first, attributed to Na+ ions migrating into the CdS/ZnO layer; later, a decrease in shunt resistance occurs. The application of the model in BSG samples showed an increase in series resistance evaluated at 25 °C. When the bias is reversed, SLG samples gradually recover their performance.

Imaging charge carriers in potential-induced degradation defects of c-Si solar cells by scanning capacitance microscopy

We report on nm-resolution imaging of charge-carrier distribution around local potential-induced degradation (PID) shunting defects using scanning capacitance microscopy. We imaged on cross sections of heavily field-degraded module areas, cored out and selected by mm-scale photoluminescence imaging. We found localized areas with abnormal carrier behavior induced by the PID defects: the apparent n-type carrier extends vertically into the absorber to ∼1–2 μm from the cell surface, and laterally in similar lengths; in defect-free areas, the n-type carrier extends ∼0.5 μm, which is consistent with the junction depth. For comparison, we also investigated areas of the same module exhibiting the least PID stress, and we found no such heavily damaged junction area. Instead, we found slightly abnormal carrier behavior, where the carrier-type inversion in the absorber did not occur, but the p-type carrier concentration changed slightly in a much smaller lateral length of ∼300 nm. These nano-electrical findings may indicate a possible mechanism that the existing extended defects, which may not be significantly harmful to cell performance, can be changed by PID to heavily damaged junction areas.

In-Situ Characterization of Potential-Induced Degradation in Crystalline Silicon Photovoltaic Modules Through Dark I–V Measurements

A temperature correction methodology for in-situ dark I–V (DIV) characterization of conventional p-type crystalline silicon photovoltaic (PV) modules undergoing potential-induced degradation (PID) is proposed. We observe that the DIV-derived module power temperature coefficient $(\gamma _{{\rm{dark}}})$ varies as a function of the extent of PID. To investigate the relationship between $\gamma _{{\rm{dark}}}$ and DIV-derived module power $(P_{{\rm{dark}}}(T_{s})$ , measured in situ and at the stress temperature) two parameters are defined: change in the DIV-derived module temperature coefficient $(\Delta\gamma _{{\rm{dark}}})$ and DIV-derived module power degradation at the PID stress temperature $(\Delta P_{{\rm{dark}}}(T_{s}))$ . It is determined that there is a linear relationship between $\Delta\gamma _{{\rm{dark}}}$ and $\Delta P_{{\rm{dark}}}(T_{s})$ . Based on this finding, we can easily determine the module $\gamma _{{\rm{dark}}}$ at various stages of PID by monitoring $P_{{\rm{dark}}}(T_{s})$ in situ . We then further develop a mathematical model to translate $P_{{\rm{dark}}}(T_{s})$ to that at 25 °C $(P_{{\rm{dark}}}({\text{25}}\, ^\circ {\text{C}}))$ , which is correlated with the module power measured at the standard testing conditions ( P STC). Our experiments demonstrate that, for various degrees of PID, the temperature correction methodology offers a relative accuracy of ±3% for predicting $P_{{\rm{STC}}}$ . Furthermore, it reduces the root-mean-square error (RMSE) by around 70%, compared with the $P_{{\rm{STC}}}$ estimation without the temperature correction.

Toward a PID Test Standard: Understanding and Modeling of Laboratory Tests and Field Progression

Currently, the IEC 62804 potential-induced degradation (PID) test specification draft is in final discussion. The goal of the proposed method is to establish a reproducible and, with respect to field behavior, meaningful PID test. In this study, parameters with a high impact on the reproducibility of the test are evaluated, and the meaning of the test results with regard to PID behavior of fielded models is discussed. PID-prone modules were exposed to ultraviolet (UV) light and sunlight prior to testing. It is revealed that irradiation leads to an increased PID susceptibility and should, therefore, be taken into consideration when designing test methods. For the environmental chamber test described in IEC 62804, results are presented that indicate that humidity characteristics during the test run have a strong impact on the resulting PID stress and, therefore, need to be well controlled. In order to understand the PID stress of fielded modules, a model simulating PID progression was developed. This model is used to identify capabilities and limits of tests currently in use. It is shown that recovery from PID has an important impact on overall PID susceptibility of a module. In addition, a comparison between outdoor measurements and simulation results is presented to validate model predictions.

Potential-induced Degradation at Interdigitated Back Contact Solar Cells

Potential-induced degradation (PID) is characterized by the power loss of solar modules under high voltage stress across the module layer stack between framing/glass surface and solar cells. Standard silicon solar cells with a front side emitter may suffer from PID through massive shunting (PID-s) under high voltage stress conditions. PID was also reported in the past for cell concepts with a local emitter at the back side. For this case the underlying physical mechanism is not fully understood.In this contribution the PID effect is investigated for interdigitated back contact solar cells (IBC cells). Parts of the front side of the cells are exposed to high-voltage stress using a recently developed cell test setup at variable temperature, voltage and polarity. Cells are investigated by means of electroluminescence (EL), IR-thermography, illuminated and dark I-V measurements before as well as after PID tests. Cell fragments are investigated after PID stressing using the electron beam induced current (EBIC) method in combination with scanning electron microscopy (SEM).PID tests with a positive voltage respect to the grounded cell cause a locally degraded EL signal in the region where the PID stress was applied. In contrast, PID tests with the opposite polarity do not affect the EL behavior at all. I-V curves and thermography images indicate that PID stress does not significantly increase Rshunt. The local decrease of the EL intensity indicates increased non-radiative recombination. SEM/EBIC reveals neither local shunts nor distinct local degradation of the EBIC signal that could be attributed to PID tests with positive voltage.The results indicate a degradation process related to a degradation of the front side passivation layer (PID-p), in contrast to the well-known PID-s effect. Based on the results a model concept for PID-p of IBC solar cells is proposed. Accordingly, the potential impact on the module power output under the influence of high voltage stress is assessed.