Potential Speedup Research Articles

Quantum-speed-limit time for multiqubit open systems

Quantum-speed-limit (QSL) time captures the intrinsic minimal time interval for a quantum system evolving from an initial state to a target state. In single qubit open systems, it was found that the memory (non-Markovian) effect of environment plays an essential role in shortening QSL time or, say, increasing the capacity for potential speedup. In this paper, we investigate the QSL time for multiqubit open systems. We find that for a certain class of states the memory effect still acts as the indispensable requirement for cutting the QSL time down, while for another class of states this takes place even when the environment is of no memory. In particular, when the initial state is in product state $|111\ensuremath{\cdots}1\ensuremath{\rangle}$, there exists a sudden transition from no capacity for potential speedup to potential speedup in a memoryless environment. In addition, we also display evidence for the subtle connection between QSL time and entanglement that weak entanglement may shorten QSL time even more.

A practical introduction to butterfly and adaptive resampling in Sequential Monte Carlo

Parallel and distributed computing technologies offer great potential for speed-up of Monte Carlo algorithms. However, in the development of most existing algorithms it has been implicitly assumed that implementation would be on a serial machine, so algorithm structure is often not well-suited to parallel architectures. In recent work the authors have studied the theoretical properties of sequential Monte Carlo algorithms involving a \\buttery" resampling method, whose conditional independence structure is intended to better match parallel and distributed architectures, with resampling broken down into stages, allowing sampling tasks for subsets of the particles to be handled concurrently. This paper provides a more practical overview of these methods, including consideration of adaptive resampling schemes, numerical results and an accessible account of theoretical properties.

Contracting Symmetric Tensors Using Fewer Multiplications

We present more computationally-efficient algorithms for contracting symmetric tensors. Tensor contractions are reducible to matrix multiplication, but permutational symmetries of the data, which are expressed by the tensor representation, provide an opportunity for more efficient algorithms. Previously known methods have exploited only tensor symmetries that yield identical computations that are directly evident in the contraction expression. We present a new ‘symmetry preserving’ algorithm that uses an algebraic reorganization in order to exploit considerably more symmetry in the computation of the contraction than the conventional approach. The new algorithm requires fewer multiplications but more additions per multiplication than previous approaches. The applications of this result include the capability to multiply a symmetric matrix by a vector, as well as compute the rank-2 symmetric vector outer product in half the number of scalar multiplications, albeit with more additions. The symmetry preserving algorithm can also be adapted to perform the complex versions of these operations, namely the product of a Hermitian matrix and a vector and the rank-2 Hermitian vector outer product, in 3/4 of the overall operations. Consequently, the number of operations needed for the direct algorithm to compute the eigenvalues of a Hermitian matrix is reduced by the same factor. Our symmetry preserving tensor contraction algorithm can also be adapted to the antisymmetric case and is therefore applicable to the tensor-contraction computations employed in quantum chemistry. For these applications, notably the coupled-cluster method, our algorithm yields the highest potential speed-ups, since in many higher-order contractions the reduction in the number of multiplications achieved by our algorithm enables an equivalent reduction in overall contraction cost. We highlight that for three typical coupled-cluster contractions taken from methods of three different orders, our algorithm achieves 2X, 4X, and 9X improvements in arithmetic cost over the standard approach.

2‐matrix‐based finite element linear solver for fast transient thermal analysis of high‐performance ICs

SummaryIn this article, we propose 2‐based finite element (FE) solver for transient thermal analysis of high‐performance integrated circuits (ICs). 2‐matrix is a special subclass of hierarchical matrix or ‐matrix, which was shown to provide a data‐sparse way to approximate the matrices and their inverses with almost linear space and time complexities. In this work, we show that 2‐based mathematical framework can also be applied to FE‐based transient analysis of thermal parabolic partial differential equations. We show how the thermal matrix can be approximated by 2‐representations with controlled error. Then, we demonstrate that both storage and time complexities of the new solver are bounded by , where N is the matrix size. The method can be applied to any thermal structures for both steady and transient analysis. The numerical results from 3D ICs demonstrate the linear scalability of the proposed method in terms of both memory footprint and CPU time. The comparison with existing product‐quality LU solvers, CSPARSE and UMFPACK, on a number of 3D IC thermal matrices, shows that the new method is much more memory efficient than these methods, which however prevents the demonstration of the potential speedup of the proposed method over those methods. Copyright © 2014 John Wiley & Sons, Ltd.

Efficient Mode Decision Schemes for HEVC Inter Prediction

The emerging High Efficiency Video Coding (HEVC) standard reduces the bit rate by almost 40% over the preceding state-of-the-art Advanced Video Coding (AVC) standard with the same objective quality but at about 40% encoding complexity overhead. The main reason for HEVC complexity is inter prediction that accounts for 60%-70% of the whole encoding time. This paper analyzes the rate-distortion-complexity characteristics of the HEVC inter prediction as a function of different block partition structures and puts the analysis results into practice by developing optimized mode decision schemes for the HEVC encoder. The HEVC inter prediction involves three different partition modes: square motion partition, symmetric motion partition (SMP), and asymmetric motion partition (AMP) out of which the decision of SMPs and AMPs are optimized in this paper. The key optimization techniques behind the proposed schemes are: 1) a conditional evaluation of the SMP modes; 2) range limitations primarily in the SMP sizes and secondarily in the AMP sizes; and 3) a selection of the SMP and AMP ranges as a function of the quantization parameter. These three techniques can be seamlessly incorporated in the existing control structures of the HEVC reference encoder without limiting its potential parallelization, hardware acceleration, or speed-up with other existing encoder optimizations. Our experiments show that the proposed schemes are able to cut the average complexity of the HEVC reference encoder by 31%-51% at a cost of 0.2%-1.3% bit rate increase under the random access coding configuration. The respective values under the low-delay B coding configuration are 32%-50% and 0.3%-1.3%.

Analysis of speedups in parallel evolutionary algorithms and [formula omitted] EAs for combinatorial optimization

Evolutionary algorithms are popular heuristics for solving various combinatorial problems as they are easy to apply and often produce good results. Island models parallelize evolution by using different populations, called islands, which are connected by a graph structure as communication topology. Each island periodically communicates copies of good solutions to neighboring islands in a process called migration. We consider the speedup gained by island models in terms of the parallel running time for problems from combinatorial optimization: sorting (as maximization of sortedness), shortest paths and Eulerian cycles. The results show in which settings and up to what degree evolutionary algorithms can be parallelized efficiently. Our results include offspring populations in (1+λ) EAs as a special case. Potential speedups depend on many design choices such as the search operators, representations and fitness functions used on the islands, and also the parameters of the island model. In particular, we show that a natural instance for Eulerian cycles leads to exponential vs. logarithmic speedups, depending on the frequency of migration.

Potential thread-level-parallelism exploration with superblock reordering

The growing number of processing cores in a single CPU is demanding more parallelism from sequential programs. But in the past decades few work has succeeded in automatically exploiting enough parallelism, which casts a shadow over the many-core architecture and the automatic parallelization research. However, actually few work was tried to understand the nature, or amount, of the potentially available parallelism in programs. In this paper we will analyze at runtime the dynamic data dependencies among superblocks of sequential programs. We designed a meta re-arrange buffer to measure and exploit the available parallelism, with which the superblocks are dynamically analyzed, reordered and dispatched to run in parallel on an ideal many-core processor, while the data dependencies and program correctness are still maintained. In our experiments, we observed that with the superblock reordering, the potential speedup ranged from 1.08 to 89.60. The results showed that the potential parallelism of normal programs was still far from fully exploited by existing technologies. This observation makes the automatic parallelization a promising research direction for many-core architectures.

Compressed Threshold Pivoting for Sparse Symmetric Indefinite Systems

A key technique for controlling numerical stability in sparse direct solvers is threshold partial pivoting. When selecting a pivot, the entire candidate pivot column below the diagonal must be up-to-date and must be scanned. If the factorization is parallelized across a large number of cores, communication latencies can be the dominant computational cost. In this paper, we propose two alternative pivoting strategies for sparse symmetric indefinite matrices of full rank that significantly reduce communication by compressing the necessary data into a small matrix that can be used to select pivots. Once pivots have been chosen, they can be applied in a communication-efficient fashion. For an $n\times p$ submatrix on $P$ processors, we show our methods perform a factorization using $O(\log P)$ messages instead of the $O(p\log P)$ for threshold partial pivoting. The additional costs in terms of operations and communication bandwidth are relatively small. A stability proof is given and numerical results using a range of symmetric indefinite matrices arising from practical problems are used to demonstrate the practical robustness. Timing results on large random examples illustrate the potential speedup on current multicore machines.

Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)

Data hazards cause severe pipeline performance degradation for data-intensive computing processes. To improve the performance under a pessimistic assumption on the pipeline efficiency, a high-speed and energy-efficient VLSBM is proposed that successively performs a speculating and correcting phase. To reduce the critical path, the VLSBM partial products are partitioned into the (n-z)-bit least significant part (LSP) and the self-reliant (n+z)-bit most significant part (MSP), and an estimation function stochastically predicts the carry to the MSP, thereby allowing independent calculation of the partial-product accumulation of parts. When a carry prediction is accurate, the data dependence is hidden and the correcting phase is bypassed, thereby ensuring the potential speed-up of the pipelined datapath. If a prediction is inaccurate, the speculation is flushed and the correcting phase is executed to obtain the exact multiplication. The simulation results verify the effectiveness of the proposed VLSBM. When applied to a DSP algorithm with a data hazard (or dependence) probability P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> , 0 ≤ P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ≤ 1, the results show that the proposed VLSBM outperforms the original Booth multiplier and the fastest conventional well-pipelined modified Booth multiplier when P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> > 0.32. For the case of high P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> with P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ≈ 1, the proposed VLSBM improves approximately 1.47 times speedup against the fastest conventional pipelined Booth multiplier (@UMC 90 nm CMOS) and, furthermore, approximately 25.4% of energy per multiplication and 7% of area are saved. By examining multiplications during three multimedia application processes (i.e., JPEG compression, object detection, and H.264/AVC decoding), the proposed VLSBM improves the speed-up ratio by approximately 1.0 to 1.4 times, and reduces the cycle count ratio by approximately 1.3 to 1.8 times in comparison to the fastest conventional two-stage pipelined Booth multiplier.

Visualizing 3D/4D environmental data using many-core graphics processing units (GPUs) and multi-core central processing units (CPUs)

Visualizing 3D/4D environmental data is critical to understanding and predicting environmental phenomena for relevant decision making. This research explores how to best utilize graphics process units (GPUs) and central processing units (CPUs) collaboratively to speed up a generic geovisualization process. Taking the visualization of dust storms as an example, we developed a systematic 3D/4D geovisualization framework including preprocessing, coordinate transformation interpolation, and rendering. To compare the potential speedup of using GPUs versus that of using CPUs, we have implemented visualization components based on both multi-core CPUs and many-core GPUs. We found that (1) multi-core CPUs and many-core GPUs can improve the efficiency of mathematical calculations and rendering using multithreading techniques; (2) given the same amount of data, when increasing the size of blocks of GPUs for coordinate transformation, the executing time of interpolation and rendering drops consistently after reaching a peak; (3) the best performances obtained by GPU-based implementations in all the three major processes, are usually faster than CPU-based implementations whereas the best performance of rendering with GPUs is very close to that with CPUs; and (4) as the GPU on-board memory limits the capabilities of processing large volume data, preprocessing data with CPUs is necessary when visualizing large volume data which exceed the on-board memory of GPUs. However, the efficiency may be significantly hampered by the relative high-latency of the data exchange between CPUs and GPUs. Therefore, visualization of median size 3D/4D environmental data using GPUs is a better solution than that of using CPUs.

A Critical Comparison of Reduced and Conventional EOS Algorithms

Summary Phase-equilibrium calculations can be a time-consuming part of process simulators and compositional reservoir simulations. Various authors have presented encouraging speed improvements based on reduced methods that can lower the computational cost by reducing the number of independent variables and thus generating a smaller system of equations to solve. This paper presents a careful comparison of conventional and reduced algorithms, showing that they can be expressed as linear transformations of each other. Consequently, the two sets of algorithms exhibit identical convergence behavior, and the performance gain of the reduced methods is entirely caused by reducing the cost of linear-algebra operations. Performance benchmarks show much smaller speed-up numbers than seen in previously published material. Highly optimized linear-algebra operations significantly limit the opportunity for further speed improvement from reduced methods. Only a marginal speed-up potential is observed for mixtures with 15 components or less. This suggests that reduced methods may be less attractive for reservoir simulation than previously thought.

Using dual presolving reductions to reformulate cumulative constraints

Dual presolving reductions are a class of reformulation techniques that remove feasible or even optimal solutions while guaranteeing that at least one optimal solution remains, as long as the original problem was feasible. Presolving and dual reductions are important components of state-of-the-art mixed-integer linear programming solvers. In this paper, we introduce them both as unified, practical concepts in constraint programming solvers. Building on the existing idea of variable locks, we formally define and justify the use of dual information for cumulative constraints during a presolving phase of a solver. In particular, variable locks are used to decompose cumulative constraints, detect irrelevant variables, and infer variable assignments and domain reductions. Since the computational complexity of propagation algorithms typically depends on the number of variables and/or domain size, such dual reductions are a source of potential computational speed-up. Through experimental evidence on resource constrained project scheduling problems, we demonstrate that the conditions for dual reductions are present in well-known benchmark instances and that a substantial proportion of them can be solved to optimality in presolving --- without search. While we consider this result very promising, we do not observe significant change in overall run-time from the use of our novel dual reductions

Finding good optimization sequences covering program space

The compiler optimizations we enable and the order in which we apply them on a program have a substantial impact on the program execution time. Compilers provide default optimization sequences which can give good program speedup. As the default sequences have to optimize programs with different characteristics, they embed in them multiple subsequences which can optimize different classes of programs. These multiple subsequences may falsely interact with each other and affect the potential program speedup achievable. Instead of searching for a single universally optimal sequence, we can construct a small set of good sequences such that for every program class there exists a near-optimal optimization sequence in the good sequences set. If we can construct such a good sequences set which covers all the program classes in the program space, then we can choose the best sequence for a program by trying all the sequences in the good sequences set. This approach completely circumvents the need to solve the program classification problem. Using a sequence set size of around 10 we got an average speedup up to 14% on PolyBench programs and up to 12% on MiBench programs. Our approach is quite different from either the iterative compilation or machine-learning-based prediction modeling techniques proposed in the literature so far. We use different training and test datasets for cross-validation as against the Leave-One-Out cross-validation technique.

Velocity–pressure coupling on GPUs

We explore the possibilities to accelerate simulations in computational fluid dynamics by additional graphics processing units (GPUs). By examining some examples of stationary incompressible flows from the industrial practice we demon- strate that the potential speedup obtained by deploying GPU accelerated linear solvers alone is limited if standard segregated algorithms are used. However, recently pre- sented velocity-pressure coupling algorithms are an attractive alternative to these seg- regated algorithms. We present an efficient AMG solver for the coupled linear system of mixed elliptic-hyperbolic character and show that the GPU-accelerated version of this linear solver accelerates the velocity-pressure coupling scheme by almost 50 % compared to a competitive CPU implementation. Compared to standard segregated methods, the computing time of the whole simulation is reduced by up to 75 %.

Negative quasi-probability as a resource for quantum computation

A central problem in quantum information is to determine the minimal physical resources that are required for quantum computational speed-up and, in particular, for fault-tolerant quantum computation. We establish a remarkable connection between the potential for quantum speed-up and the onset of negative values in a distinguished quasi-probability representation, a discrete analogue of the Wigner function for quantum systems of odd dimension. This connection allows us to resolve an open question on the existence of bound states for magic state distillation: we prove that there exist mixed states outside the convex hull of stabilizer states that cannot be distilled to non-stabilizer target states using stabilizer operations. We also provide an efficient simulation protocol for Clifford circuits that extends to a large class of mixed states, including bound universal states.

Families of Algorithms for Reducing a Matrix to Condensed Form

In a recent paper it was shown how memory traffic can be diminished by reformulating the classic algorithm for reducing a matrix to bidiagonal form, a preprocess when computing the singular values of a dense matrix. The key is a reordering of the computation so that the most memory-intensive operations can be “fused.” In this article, we show that other operations that reduce matrices to condensed form (reduction to upper Hessenberg form and reduction to tridiagonal form) can be similarly reorganized, yielding different sets of operations that can be fused. By developing the algorithms with a common framework and notation, we facilitate the comparing and contrasting of the different algorithms and opportunities for optimization on sequential architectures. We discuss the algorithms, develop a simple model to estimate the speedup potential from fusing, and showcase performance improvements consistent with the what the model predicts.

Fast 3D PIV with direct sparse cross-correlations

The extension of the well-assessed high-accuracy algorithms for two-dimensional-two components particle image velocimetry (PIV) to the case of three-dimensional (3D) data involves a considerable increase of the computational cost. Tomographic PIV is strongly affected by this issue, relying on 3D cross-correlation to estimate the velocity field. In this study, a number of solutions are presented, enabling a more efficient calculation of the velocity field without any significant loss of accuracy. A quick estimation of the predictor displacement field is proposed, based on voxels binning in the first steps of the process. The corrector displacement field is efficiently computed by restricting the search area of the correlation peak. In the initial part of the process, the calculation of a reduced cross-correlation map by using Fast Fourier Transform on blocks is suggested, in order to accelerate the processing by avoiding redundant calculations in case of overlapping interrogations windows. Eventually, direct cross-correlations with a search radius of only 1 pixel in the neighborhood of the estimated peak are employed; the final iterations are consistently faster, since direct correlations can better enjoy the sparsity of the distributions, reducing the number of operations to be performed. Furthermore, three different approaches to reduce the number of redundant calculations for overlapping windows are presented, based on pre-calculations of the contributions to the cross-correlations coefficients along segments, planes or blocks. The algorithms are tested both on synthetic and real images, showing that a potential speed-up of up to 800 times can be obtained, depending on the complexity of the flow field to be analyzed. The challenging application on a real swirling jet results in a speed-up of an order of magnitude.

Power Limitations and Dark Silicon Challenge the Future of Multicore

Since 2004, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to which the shift to multicore parts is partially a response, may soon limit multicore scaling just as single-core scaling has been curtailed. This paper models multicore scaling limits by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads for the next five technology generations. For device scaling, we use both the ITRS projections and a set of more conservative device scaling parameters. To model single-core scaling, we combine measurements from over 150 processors to derive Pareto-optimal frontiers for area/performance and power/performance. Finally, to model multicore scaling, we build a detailed performance model of upper-bound performance and lower-bound core power. The multicore designs we study include single-threaded CPU-like and massively threaded GPU-like multicore chip organizations with symmetric, asymmetric, dynamic, and composed topologies. The study shows that regardless of chip organization and topology, multicore scaling is power limited to a degree not widely appreciated by the computing community. Even at 22 nm (just one year from now), 21% of a fixed-size chip must be powered off, and at 8 nm, this number grows to more than 50%. Through 2024, only 7.9× average speedup is possible across commonly used parallel workloads for the topologies we study, leaving a nearly 24-fold gap from a target of doubled performance per generation.

Model-Driven Design for the Visual Analysis of Heterogeneous Data

As heterogeneous data from different sources are being increasingly linked, it becomes difficult for users to understand how the data are connected, to identify what means are suitable to analyze a given data set, or to find out how to proceed for a given analysis task. We target this challenge with a new model-driven design process that effectively codesigns aspects of data, view, analytics, and tasks. We achieve this by using the workflow of the analysis task as a trajectory through data, interactive views, and analytical processes. The benefits for the analysis session go well beyond the pure selection of appropriate data sets and range from providing orientation or even guidance along a preferred analysis path to a potential overall speedup, allowing data to be fetched ahead of time. We illustrate the design process for a biomedical use case that aims at determining a treatment plan for cancer patients from the visual analysis of a large, heterogeneous clinical data pool. As an example for how to apply the comprehensive design approach, we present Stack'n'flip, a sample implementation which tightly integrates visualizations of the actual data with a map of available data sets, views, and tasks, thus capturing and communicating the analytical workflow through the required data sets.

Dark Silicon and the End of Multicore Scaling

A key question for the microprocessor research and design community is whether scaling multicores will provide the performance and value needed to scale down many more technology generations. To provide a quantitative answer to this question, a comprehensive study that projects the speedup potential of future multicores and examines the underutilization of integration capacity-dark silicon-is timely and crucial.