Potential Fault Sites Research Articles

Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs

Nanoscale interlayer vias (ILVs) in monolithic 3-D (M3D) ICs have enabled high-density vertical integration of logic and memory tiers. However, the sequential assembly of M3D tiers via wafer bonding is prone to variability in the immature fabrication process and manufacturing defects. The yield degradation due to ILV faults can be mitigated via dedicated test and diagnosis of ILVs using built-in self-test (BIST). Prior work has carried out fault localization for a regular 1-D placement of ILVs in the M3D layout where shorts are assumed to arise only between unidirectional ILVs. However, to minimize wirelength in M3D routing, ILVs may be irregularly placed by a place-and-route tool, and shorts can also occur between an up-going ILV and a down-going ILV. To test and localize faults in realistic ILV layouts, we present a new BIST framework that is optimized for test time and PPA overhead. We also present a graph-theoretic approach for representing potential fault sites in the ILVs and carry out inductive fault analysis to drop noncritical sites. We describe a procedure for optimally assigning ILVs to the BIST pins and determining the BIST configuration for test-cost minimization. Evaluation results for M3D benchmarks demonstrate the effectiveness of the proposed framework.

Effect of Test Coverage and Change Point on Software Reliability Growth Based on Time Variable Fault Detection Probability

In past four decades, many software reliability growth models (SRGMs) have been proposed to enhance the reliability of the software system. During the testing process potential fault sites are sensitized to detect the faults. Fault detection probability increases as learning and maturity of the testing personnel increases. Therefore, in this paper a time variant fault detection probability has been introduced and integrated into s-shaped coverage SRGM. Experimental results shows that the proposed model is better and will be helpful to improve the accuracy of the software reliability estimation.

Bridging fault diagnostic tool based on Δ I DDQ probabilistic signatures, circuit layout parasitics and logic errors

A diagnostic tool for bridging faults combining three different data sources is presented. The first data source is a set of IDDQ measurements used to identify the most probable fault type. The second source is a list of parasitic capacitances extracted from layout and used to create a list of realistic potential bridging fault sites. The third source is logical faults detected at the primary outputs (including scan flip flops), used to limit the number of suspected gates. The combination of these data significantly reduces the number of potential fault sites to consider in the diagnosis process. Simulation results confirm that the number of potential bridging fault sites is reduced from O(N2) to less than O(N), where N is the number of nodes in the circuit. The tool therefore converges quickly towards the solution while using less resources. A new technique is also introduced to estimate the additional delay caused by the diagnosed bridging fault based on the diagnostic results. Performing this estimation allows us to confirm the previous diagnosis results.

A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis

Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine General's phenomenon, in which a fault manifests itself as a non-logical voltage level at the fault site. Previously, explicit enumeration was suggested to deal with such a problem. However, it is often too time-consuming because the CPU time is exponentially proportional to fanout degree of the circuit under diagnosis. To speed up this process, we present an implicit enumeration technique using symbolic simulation. Experimental results show that the CPU time can be improved by several orders of magnitude for the ISCAS85 benchmark circuits while locating the faults accurately.