Post-nitridation Annealing Research Articles

(Invited, Digital Presentation) Clarification of Possible Factors to Determine Flat-Band Voltage in 4H-SiC Gate Stacks with Nitrogen Passivation Processes

Control of flat-band voltage (Vfb) in 4H-SiC gate stacks is inevitable for high-voltage power MOSFET applications, since a sufficiently large threshold voltage (Vth) is required to suppress the false turn on. However, the increase in channel doping concentration to tune Vth results in a drastic reduction of carrier mobility in the inversion channel, due to Coulomb scattering caused by SiO2/4H-SiC interface [1]. Therefore a negative shift of Vfb is not preferred in terms of channel resistance reduction. The SiC surface nitridation process by a post-oxidation annealing (POA) in NO ambient at elevated temperature is an inevitable technique to suppress the interface defects [2]. However, a serious drawback is the fact that a negative shift of Vfb is often observed by employing NO-POA.Two possible mechanisms are to be considered which cause negative Vfb shifts in SiO2/4H-SiC MOS gate stacks: the generation of positive fixed charges, and the formation of interface dipole layers. We systematically investigated the flat-band voltage of SiO2/4H-SiC (0001) n-type MOS capacitors with various oxide thickness, fabricated by conventional dry oxidation followed by NO-POA at 1150℃ for several hours. When fixed charges are existing at the interface, it is natural to observe a linear relationship between the oxide thickness and Vfb, where we can estimate the fixed charge density from the slope. As a result, we found that the fixed charge densities were quite small after sufficient nitridation processes, however, an anomalous negative shift of Vfb in several hundreds of mV irrespective of oxide thickness was observed, which was enlarged by extending NO annealing duration [3]. This anomalous shift would be explainable by assuming a dipole layer formation at the interface by SiC surface nitridation, which may be caused by polar Si3-N tetrapod structure formation with high density aligned at the interface.Next we studied the impact of additional annealing after nitridation on Vfb, since the SiC device processes in general require such additional annealing including metallization processes. We conducted an additional 1 min rapid thermal annealing in N2 after NO-POA (post-nitridation anneal; PNA) at various temperatures from 800 to 1150℃. As a result, positive interface fixed charges were generated more by the PNA at higher temperatures [4], while fixed charge generation was insignificant by the PNA at low temperature such as 800℃ [4]. Note that interface state density did not change significantly by these PNA processes.Besides the influences on the Vfb shift, the interface dipole layer formation naturally affects the SiO2/4H-SiC band alignment. The conduction band offset, which is one of the critical factors to determine the gate leakage current level, must be dependent on the dipole layer strength. The valence-band spectra analysis using x-ray photoelectron spectroscopy and the energy barrier height characterization of Fowler-Nordheim current analysis tell us that the conduction-band offset at SiO2/SiC interface monotonically becomes larger by increasing the amount of nitrogen at the interface, which is consistent with the negative shift of Vfb observed in MOS capacitors [3]. To our surprise, this trend appeared in opposite direction when the gate stacks were fabricated on 4H-SiC (1-100) wafers [5].Finally we examined another way to tune the Vfb of SiC gate stacks by the introduction of additional dipole layer, by depositing of just a few nm-thick Al2O3 layer on top of SiO2 after NO-POA, based on the concept of oxide interface dipole layers reported for various high-k/SiO2 interfaces. As a result we successfully demonstrated ~1V Vfb shift without any deterioration of interface state density only by Al2O3 deposition [6]. This technique is expected as an additional method to achieve larger Vfb.In conclusion, we found that Vfb of nitrogen passivated SiO2/4H-SiC gate stacks is significantly affected by two factors: the positive fixed charges at the interface mainly introduced by post-nitridation annealing, and the interface dipole layer formation due to the polar structures aligned at the interface, or the intentionally introduced dipole layer by depositing a few nm-thick Al2O3 on top of SiO2.[1] M. Noguchi et al., Jpn. J. Appl. Phys. 58, 031004 (2019).[2] J. Rozen et al., J. Appl. Phys. 105, 124506 (2009).[3] T. H. Kil and K. Kita, Appl. Phys. Lett. 116, 122103 (2020).[4] T. H. Kil and K. Kita, 2021 International Workshop on Dielectric Thin Films for Future Electron Devices: Science and Technology (IWDTF), Nov. 2021.[5] T. H. Kil, A. Tamura, S. Shimizu and K. Kita, Appl. Phys. Express 14, 081005 (2021).[6] T. H. Kil, M. Noguchi, H. Watanabe, and K. Kita, Solid-State Electronics 183, 108115 (2021).

Impact of post-nitridation annealing in CO2 ambient on threshold voltage stability in 4H-SiC metal-oxide-semiconductor field-effect transistors

The combination of NO annealing and subsequent post-nitridation annealing (PNA) in CO2 ambient for SiO2/SiC structures has been demonstrated to be effective in obtaining both high channel mobility and superior threshold voltage stability in SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs). N atoms on the SiO2 side of the SiO2/SiC interface incorporated by NO annealing, which are plausible causes of charge trapping sites, could be selectively removed by CO2-PNA at 1300 °C without oxidizing the SiC. CO2-PNA was also effective in compensating oxygen vacancies in SiO2, resulting in high immunity against both positive and negative bias-temperature stresses.

(Invited) Design of SiO2/4H-SiC Formation Process with H2O Annealing to Improve MOSFET Performance

4H-SiC has attractive properties for power devices of high voltage applications, however, the performance of MOSFETs is often severely limited by the poor SiO2/SiC interface quality. One of the common techniques to passivate the interface defects is the nitrogen introduction by NO annealing [1] while introduction of wide variety of impurity elements have also been studied [2]. It has been pointed out that SiC MOS characteristics are significantly different between dry-oxidized and wet-oxidized interfaces, and wet-oxidation of SiC often results in a dramatic reduction of interface defect density [3]. To consider the possible reason of the benefit of oxidation by H2O, it should be noticed that the remained carbon at the interface as the thermal oxidation byproduct causes various kinds of interface defects formation. We found that H2O-oxidation does not leave CO-related defect structures near the interface [4]. At the same time H2O-oxidation results in the formation of less-strained SiO2 at the interface than O2-oxidation, which was clarified from the difference of the Si-O-Si vibration mode frequencies in FTIR spectra [3]. Since the formation of near-interface oxide traps of electrons with long time constants is one of the serious causes of the poor MOSFET channel properties, such improvement of near-interface structure would be an advantage of H2O-oxidation. Based on these considerations, we have demonstrated the benefit of the post-oxidation annealing in H2O (H2O-POA) after a simple dry-oxidation, as the way to improve the performance of NMOSFETs formed on 4H-SiC (0001). In this study the H2O-POA ambient was produced by bubbling of O2 or N2 flowing gas through hot water kept at ~97oC to have H2O vapor pressure of ~0.9 atm. It should be noted that this process effectively works with only < 1nm additional growth of oxide at the interface during H2O-annealing [5]. The peak channel mobility ~ 50 cm2/Vs was observed for the channel of ~ 5×1015 cm-3 doping concentration, or that ~35 cm2/Vs for the channel of ~1.3×1016 cm-3 doping concentration, which were higher values than the typical results of conventional NO-passivation processes. We also investigated the combined passivation process of the NO annealing and the low-temperature H2O-annealing on 4H-SiC (0001), to take the advantages of both the nitrogen passivation and the interface structural modification by H2O-oxidation [6]. After the growth of ~30 nm-thick SiO2 layer in dry-O2, the annealing in NO:N2 =1:2 ambient at 1150oC (NO-POA) and the additional annealing in 0.9 atm-H2O ambient at 800oC (H2O post nitridation annealing; H2O-PNA) were sequentially conducted. From XPS analysis on SiC surface after removal of oxides by HF etching, it was found that most of the surface-terminating nitrogen atoms still remained at the interface after a short-time H2O-PNA to cause the growth of limited amount of SiO2 around a few angstroms. The interface state density (Dit) of SiO2/SiC MOS interface was minimized by such short-time H2O-PNA, while an excess time of PNA resulted in rather increase of Dit probably because a part of the surface-terminating nitrogen atoms was removed by H2O-oxidation. A significant improvement of NMOSFET mobility was also successfully demonstrated for the cases of short-time H2O-PNA. Finally the effects of oxygen partial pressure (pO2) in H2O-annealing ambient were studied for the case of H2O-PNA. The impact of pO2 in the ambient on channel mobility was not significant as long as the amount of additional SiO2 growth during H2O-PNA was limited to around a few angstroms. However, a significant difference was observed when positive gate bias stress was applied to the stack. When ~+3 MV/cm constant voltage stress was applied, increase of flatband voltage shift was clearly observed for the samples annealed with pO2 in PNA ambient above ~0.1 atm, which is suggesting deterioration of SiO2 bulk film quality. In contrast, such deterioration was efficiently suppressed when we employed H2O-PNA ambient without any intentional introduction of O2, probably because O2 in H2O-ambient has a role to assist an additional unwanted reaction to form oxide traps in SiO2 bulk layer. These results indicates that the oxide quality on SiC would be quite sensitive to pO2 when the stack was annealed in H2O-ambient.

Minimization of SiO2/4H-SiC (0001) Interface State Density by Low-Temperature Post-Oxidation-Annealing in Wet Ambient after Nitrogen Passivation

The MOS interface with minimized interface state density and less near-interface oxide traps was demonstrated on 4H-SiC (0001) by the sequential combination of two kinds of annealing processes after conventional dry oxidation: the post-oxidation annealing in NO ambient and the post-nitridation annealing in H2O ambient at low temperature. The H2O annealing conditions should be tuned to limit the amount of the additional growth of SiO2 to <1 ML to minimize the interface defect density.

Effect of Post Nitridation Annealing on Thermally Grown Silicon Oxynitride Characteristics

The ability to block the direct current is one of the main requisite for the gate dielectric in a metal-oxide-field-effect-transistor. Since thickness of oxide is inversely related with oxide capacitance, therefore oxide capacitance can be increased as an alternative to oxide thickness to meet the scaling requirements. Oxynitrides and high-k materials as gate dielectric have been considered as promising candidates to overcome the above problems. At greater physical thickness, these materials have the similar capacitance value which avoids tunneling effect. SiON has been used as a substitute for SiO2 because of its high dielectric permittivity and low density of surface states. In this paper, the effect of post nitridation annealing on thermally grown silicon oxynitride characteristics have been investigated by analyzing high-frequency capacitance-voltage (C-V) and current- voltage characteristics (I-V) of n-Si/SiON/Ti-Pt MOS capacitor. Post nitridation annealing was carried out at 800°C for 15 min in Nitrogen (N2) ambient. Ellipsometery, FESEM, Atomic force microscopy (AFM) and Fourier transform infrared spectroscopy (FTIR) was used to study the effect of post nitridation annealing on the physical characteristics of deposited silicon oxynitride film. Cheung’s approach has been used for evaluating barrier height (ϕbo ) and ideality factor (η). We present a comparative study between the as-deposited and annealed film and it was found that the physical and electrical properties (k, η, ϕbo etc) improved by post nitridation annealing is attributed to the improvement in the interface properties of Si/SiON. Moreover, the value of positive fixed charge density (Q f ~1.8×1012 cm−2) is effective for field-effect passivation of n-type Si surfaces. For both as-deposited and annealed SiON film, the maximum current through the Si/SiON/Ti-Pt device never exceeded a value of 10–8A/cm2 which indicates that the film were very good insulators. These results indicate that the obtained SiON film is an appropriate gate insulator for advanced nano electronic devices.

Reduction of defect states in atomic-layered HfO2 film on SiC substrate using post-nitridation annealing

The changes of the defect states below the conduction band in atomic-layered HfO2 film grown on SiC substrate were examined as a function of the post-nitridation annealing temperature in an NH3 ambient. As the post-nitridation annealing temperature increased up to 600°C, the incorporated nitrogen into the HfO2/SiC interface was gradually increased. The band gap and valence band offset were mostly increased as a function of the post-nitridation annealing temperature and the band alignment of HfO2 films changed. O K-edge absorption features revealed two distinct band edge states below the conduction band edge in HfO2 films, and these defect states were dramatically reduced with increasing of the post-nitridation annealing temperature. The reduction of defect states in HfO2/SiC improved the electrical properties such as the leakage current density, breakdown voltage, and trap charge density in the HfO2 film and interface of HfO2/SiC.

Improved high-k stacks with chemical oxide interfacial layer by DPN/PNA treatment

A decoupled plasma nitridation (DPN) with post nitridation annealing (PNA) treatment method was introduced to improve the performances of MOS devices with high-k (HK)-last/gate-last integration scheme and chemical oxide interface layer (IL). By introducing N to form HfSiON, it was found that DPN + PNA treatments could provide smaller equivalent oxide thickness (EOT) for both nMOS and pMOS devices. It was also found that we could achieve the best overall device performance for the HK-last/gate-last integration scheme with a chemical oxide IL by introducing nitrogen gas with low percentage content during DPN followed by high temperature PNA.

Effects of the post nitridation anneal temperature on performances of the nano MOSFET with ultra-thin (

A post nitridation annealing (PNA) is used to improve performances of the metal oxide semiconductor field effect transistor (MOSFETs) with nano scale channel and pulsed radio frequency decoupled plasma nitrided ultra-thin (<50Å) gate dielectric. Effects of the PNA temperature on the gate leakage and the device performances are investigated in details. For a n-type MOSFET, as the PNA temperature rises from 1000 to 1050°C, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements in performance are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. Most of all, the high temperature PNA does not degrade the gate oxide integrity.

Depth Profile of Nitrogen Atoms in Silicon Oxynitride Films Formed by Low-Electron-Temperature Microwave Plasma Nitridation

Angle-resolved photoelectron spectroscopy study was performed on the depth profile of nitrogen atoms in silicon oxynitride (SiON) films formed by the plasma nitridation of silicon dioxide using low-electron-temperature microwave plasma. The depth profile of nitrogen near the SiON surface was confirmed to increase and its peak position moves into SiON films with an increase in the nitridation time, which improves boron immunity. A new transport and reaction model of plasma nitridation is proposed to explain the time evolution of nitrogen concentration and its depth profile in the films. Here, the density of radical nitrogen atoms decreases exponentially with an increase in the distance from the surface, and the nitrogen concentration incorporated in the SiON film is approximately proportional to the logarithmic time of plasma nitridation. It was newly found that post-nitridation annealing strongly enhances the pile-up of nitrogen atoms at the Si–SiON interface owing to their diffusion from the inward tail of the nitrogen depth profile near the surface. It is deduced that the pile-up of nitrogen atoms induces Si–H bonds at the interface, which become the main trigger for the degradation of the negative bias temperature instability of p-channel metal–oxide–silicon transistors.

Effect of interfacial reactions between atomic-layer-deposited HfO2 films and n-GaAs (100) substrate using postnitridation with NH3 vapor

Using a variety of various physical measurements, the effects of postnitridation annealing using NH3 vapor on the interface between atomic-layer-deposited HfO2 films and n-GaAs (100) substrates were investigated. After the nitridation treatment, from x-ray absorption spectroscopy and high resolution x-ray photoemission spectroscopy data indicate that the incorporation of Ga oxides into HfO2 films was significantly suppressed during the annealing treatment, primarily because of chemical reactions at the interface between Ga2O3 and NH3. Microstructural analyses further confirmed that the HfO2 film was fully crystallized and a thin GaOxNy layer had been formed at the HfO2/GaAs interface during the annealing process. Compared with the energy band alignments before and after the annealing process, the valence band offsets and energy band gaps were not changed substantially, because the interfacial nitride layer effectively blocked the diffusion of Ga oxide into the film.

Atomic Layer Control for Suppressing Extrinsic Defects in Ultrathin SiON Gate Insulator of Advanced Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

By measuring the minimum supply voltage for normal operation of test random access memories, we detected low-density extrinsic defects in silicon-oxynitride (SiON) gate insulators that were formed by state-of-the-art technologies. The density of the detected defects had a strong correlation with optical thickness dopt, which was ellipsometrically measured, regardless of the processing conditions of the SiON films. We propose to maintain the dopt above a threshold value of 1.7 nm to suppress the problems caused by the defects. The optimization of post nitridation annealing (PNA) condition is promising for meeting the criterion without sacrificing device performance. By elaborate investigations based on the Clausius–Mosotti relation, we found that the optical thickness of SiON films is approximately proportional to the atomic area density in the films. On the basis of this finding, we developed a model, which is an extension of the conventional analytical cell-based model, to figure out the physical process of the extrinsic-defect formation. The results analyzed using the model revealed that the extrinsic defects are formed in the SiON films in the case when the number of normal cells in a vertical arrangement becomes equal to or smaller than the threshold value of 3 or 4.

Impact of post-nitridation annealing on ultra-thin gate oxide performance

Decoupled-Plasma Nitridation (DPN) process with high level of nitrogen incorporation is widely used in the state-of-the-art technology, in order to reduce gate leakage current and boron penetration. However, due to the low temperature DPN process, the post-nitridation annealing treatment is required to improve the ultra-thin gate oxide integrity. In this paper, the effect of post-nitridation annealing on DPN ultra-thin gate oxide was investigated. The device performance and reliability were evaluated in three different post-nitridation annealing ambient (N 2/O 2, He, and NO).

Instability of incorporated nitrogen in HfO2 films grown on strained Si0.7Ge0.3 layers

The interfacial characteristics and thermal stability of nitrided HfO2 films grown on strained Si0.7Ge0.3 layers were investigated by medium energy ion scattering, high-resolution x-ray photoelectron spectroscopy, and near-edge x-ray absorption fine structure. N incorporation of HfO2 films grown on Si0.7Ge0.3 layers was strongly related to the diffusion of Si and Ge from strained Si0.7Ge0.3 layers in the interfacial region between HfO2 films and Si0.7Ge0.3 layers by the annealing treatment in NH3 ambient. The chemical states of SiOxNy and GeOxNy were formed in the interfacial region by N incorporation, and SiOxNy was dominant chemical states rather than that of GeOxNy. However, the incorporated N was not stable, which was mostly diffused out during the postnitridation annealing in a N2 ambient. The instability of incorporated N through the additional annealing treatment extensively caused the change in the structure of HfO2.

Band alignment and thermal stability of HfO2 gate dielectric on SiC

The band alignment and thermal stability for HfO2 films on SiC with and without nitridation have been studied by using photoemission spectroscopy. The valence- and conduction-band offsets at HfO2/4H-SiC interfaces were measured to be 1.02 and 1.53 eV, respectively. The atomic source nitridation improves interface thermal stability with nitrogen passivation for the oxygen vacancies in dielectric films and for the defects on SiC surface, but induces band gap reduction for the HfO2 dielectric layer and band alignment shift at the interface. Postnitridation annealing helps to improve the band offsets of dielectric film to have sufficient injection barrier.

Electrical characterization and carrier transportation in Hf-silicate dielectrics using ALD gate stacks for 90 nm node MOSFETs

Metal-oxide-semiconductor capacitors (MOSCs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) incorporating hafnium silicate (Hf-silicate) dielectrics were fabricated by using atomic layer deposition (ALD). The electrical properties of these Hf-silicate thin films with various postnitridation annealing (PNA) temperatures were then examined to find the best nitridation condition. It is found that the best conditions to achieve the lowest gate leakage current and best equivalent oxide thickness (EOT) are when PNA is performed at 800 °C in NH 3 ambient for 60 s. To understand the obtained film, carrier transportation mechanisms, the temperature dependence of the leakage current was measured from 300 K to 500 K for both gate injection and substrate injection. The result reveals that the leakage mechanisms involve Schottky emission at high temperature and low electrical field and Poole–Frenkle emission at low temperature and high electrical field. The barrier heights of poly-Si/Hf-silicate and Hf-silicate/Si interfaces extracted from Schottky emission are 1.1 eV and 1.04 eV, respectively. The interface traps per unit area, the mean density of interface traps per area and energy and the mean capture cross-section are determined about 8.1 × 10 10 cm −2, 2.7 × 10 11 cm −2 eV −1 and 6.4 × 10 −15 cm −2 using charge pumping method.

The effect of postnitridation annealing on the surface property and photocatalytic performance of N-doped TiO 2 under visible light irradiation

Postnitridation annealing has a remarkable effect on the surface property and photocatalytic performance of N-doped TiO 2 for photocatalytic oxidation of ethylene. The activity of N-doped TiO 2 under visible light illumination ( λ > 420 nm ) can be enhanced fourfold by annealing the sample at 400 °C. Characterization results show that the thermal annealing reduces surface oxygen vacancies, removes surface-adsorbed NH 3, and facilitates the adsorption of molecular oxygen on catalyst surface. Such a surface reconstruction contributes to the enhanced photocatalytic activity of the N-doped TiO 2. The postcalcination also improves the photocatalytic stability of the N-doped TiO 2 by stabilizing nitrogen atoms in the TiO 2 lattice. A N-doped TiO 2 sample without postcalcination suffers from a gradual deactivation, due mainly to the passivation of the catalyst surface by oxidized nitrogen species (e.g., hyponitrite, nitrite ions, and nitrate ions) formed during the photocatalytic degradation of ethylene.

Effects of postnitridation annealing on band gap and band offsets of nitrided Hf-silicate films

The effects of film composition and postnitridation annealing on band gap and valence band offset were examined in nitrided Hf-silicate films prepared using direct plasma nitridation. Regardless of the composition of Hf-silicate films, the band gap characteristics were similar after direct plasma nitridation (4.5±0.1eV) and postnitridation annealing (5.6±0.1eV). The decrease in band gap after direct plasma nitridation was caused by the formation of Si–N and Hf–N bonds, while the recovery of band gap by postnitridation annealing was influenced by the dissociation of unstable Hf–N bonds. The difference in valence band offset was strongly related to the chemical states of Si–N bonds.

Impact of In situ Postnitridation Annealing for Successful Fabrication of HfSiON Thin Film

For the successful integration of high-k gate dielectrics into advanced complementary metal–oxide–semiconductor (CMOS) processes, it is important to determine the stability of high-k materials during exposure to an ambient atmosphere. In this work, we investigated the effect of exposure to air on the nitrogen concentration in HfSiON films formed by sequentially combining HfSiO chemical vapor deposition (CVD), plasma nitridation, and postnitridation annealing (PNA). We observed that exposure to air after the nitridation step reduces the nitrogen concentration due to a reaction between the HfSiON surface and the constituents of atmospheric air. We also found that exposure to air for even a short time between nitridation and PNA leads to a significant loss of nitrogen concentration, indicating that in situ PNA is critical for achieving precise control of the nitridation. These results confirmed the importance of using clustered multichamber platforms for successful high-k fabrication.

Improvement in Positive-Bias-Temperature-Instabilities Reliability and Device Performance of TaSiN∕HfSiON Gate Stacks with High Temperature Post-Nitridation Annealing

We have investigated the effect of a post-nitridation-annealing (PNA) temperature on bias-temperature-instabilities (BTI) reliability and device performance of gate stacks formed by atomic layer deposition technology using and precursors. The gate stacks were intended for use in conventional metal gate transistors with a high temperature thermal budget of . Ultrathin effective-oxide-thickness films of about could be achieved with HfSiON gate stacks by using a PNA treatment. Moreover, the positive-BTI lifetimes of the PNA samples were improved by about one order of the magnitude with respect to lifetimes of the PNA samples, ten year lifetimes being readily achieved with at .

Electronic structure and thermal stability of nitrided Hf silicate films using a direct N plasma

The thermal stability and electronic structure of nitrided xHfO2(100−x)SiO2 (HfSiO) (x=30%, 55%, and 70%), prepared using a direct N plasma treatment, were investigated. N 1s spectra of nitrided Hf silicate films indicate that complex chemical states are generated. In particular, energy states with a high binding energy are stable, even after a postnitridation annealing. The quantity of N incorporated into the film is not dependent on the mole fraction of HfO2 in the film, while the thermal stability of the N in the film is significantly influenced by the fraction of HfO2 present. The thermal stability of the N in the film critically affects the composition and thickness of the film: i.e., after the postnitridation annealing, the thickness of the silicate film and the quantity of Hf and N are decreased, as the result of the dissociation of unstable Hf–N bonds.