Post-deposition Thermal Processing Research Articles

Oxygen Transfer from Metal Gate to High-k Gate Dielectric Stack: Interface Structure & Property Changes

Photoelectron spectroscopy and transmission electron microscopy provide clear experimental evidence to show that oxygen initially present in the W gate layer of a metal/high-k gate stack is transferred to the substrate and increases the interfacial oxide during post-deposition thermal processing. Oxide interface layer growth was reduced, but still occurred, if a TaN barrier layer was used to cap the W gate metal, thus minimizing atmospheric oxygen incorporation. Our results suggest that oxygen is incorporated into the W layer (perhaps at grain boundaries and interfaces) during or immediately after its deposition, thus providing a source for subsequent oxidation of the underlying layers. This effect, which may be exhibited by other high workfunction metals besides W, may be an important contributor to the Vfb instability observed in scaled PMOS devices based on the metal/high-k gate stacks.

Indium doping in nanostructured ZnO through low-temperature hydrothermal process

Abstract ZnO nanostructures of rod-like morphology were synthesized through a low-temperature hydrothermal process. Incorporation of indium in the nanostructures during synthesis was not successful due to the formation of In(OH) 3 phase. A post-deposition thermal annealing process in inert atmosphere resulted effective for the dissociation of In(OH) 3 phase and doping of indium into the nanostructures. Effect of indium doping on the structure, morphology and optical absorption of the nanostructures are studied. Beyond a certain concentration, the incorporated indium form phase separated oxide instead of being doped. Incorporated indium occupy the zinc sites in the nanostructures.

Low dielectric loss and enhanced tunability of Ba0.6Sr0.4TiO3 based thin films via material compositional design and optimized film processing methods

Low dielectric loss in conjunction with high tunability are simultaneous requirements for tunable device applications which have proved problematic to achieve. In this work, material compositional design and optimized film processing methods were employed to simultaneously lower the dielectric loss and enhance the dielectric tunability of Ba0.6Sr0.4TiO3 (BST) based thin films without compromising the device impedance matching (εr<500) and control voltage (<10 V) requirements. The films compositional design was achieved by Mg doping BST from 3 to 10 mol %. The Mg doped thin films were fabricated via the metalorganic solution deposition technique using carboxylate-alkoxide precursors and postdeposition annealing in an oxygen ambience at 750 °C for 60 min. The films dielectric loss at these doping levels was identical, tan δ∼0.007. In contrast, the films permittivity (339–220), leakage current density (2.55×10−8–2.43×10−9 A/cm2), tunability (21.3%–5.7%), and grain size (75.2–61.55 nm) were observed to decrease with increasing Mg concentration levels from 3 to 10 mol %, respectively. Device quality values of tunability, 40% and 32%, for the 3 and 7 mol % doped BST films, respectively, were achieved by elevating the applied bias from 237 to 474 kV/cm. This device quality tuning is compatible with voltage requirements of current semiconductor based systems. Our results suggest that the low level acceptor doping from 3 to 7 mol %, optimized precursor solution concentration (0.43 M), and oxygenated postdeposition thermal processing were found to work in concert to lower dielectric loss, limit defect density concentration, optimize film microstructure, and eliminate undesirable film/electrode interfacial phases. As a result, high quality BST thin films, with their resultant high breakdown fields, were realized. It is the excellent film quality (i.e., optimized composition and microstructure), which allowed the enhanced tunability at elevated dc bias to be achieved without risk of dielectric breakdown. The enhanced dielectric and insulating properties of the 3–7 mol % Mg doped BST thin films make them excellent candidates for integration into tunable devices.

Enhanced Dielectric Properties Of Compositionally Modified BST Based Thin Films For Voltage Tunable Microwave Devices

ABSTRACTIn this work, material compositional design and optimized film processing methods, were employed to simultaneously lower the dielectric loss and enhance the dielectric tunability of Ba0.6Sr0.4TiO3 (BST) based thin films without compromising the device impedance matching (εr<500) and device control voltage (<10 V) requirements. The films compositional design was achieved by Mg doping BST from 3 to 10 mol % via the metalorganic solution deposition (MOSD) technique and post-deposition annealing in an oxygen ambience. The films dielectric loss at these doping levels was identical, tanδ ∼0.007 and the permittivity values ranged from 339 to 220. Device quality values of tunability, 40 and 32 %, for the 3 and 7 mol% doped BST films, respectively, were achieved by elevating the applied bias to 474 kV/cm. This device quality tuning is compatible with voltage requirements of current semiconductor based systems. The results suggest that the low level acceptor doping from 3 to 7 mol%, optimized precursor solution concentration (0.43 M), and oxygenated post-deposition thermal processing were found to work in concert to lower dielectric loss, limit defect density concentration, optimize film microstructure, and eliminate undesirable film/electrode interfacial phases. The enhanced dielectric and insulating properties of the 3–7 mol% Mg doped BST thin films make them excellent candidates for integration into tunable devices.

Spectroscopic Studies of Thin Film Electron Trapping Optical Memory Media (CaS: Eu, Sm)

Films of the potential electron trapping optical memory medium CaS: Eu, Sm produced from optimally composed sputtering targets, are themselves optimized by postdeposition thermal processing in a sulfur atmosphere. X-ray diffraction studies and a variety of spectroscopic techniques are used to study the development of crystalline structure and the deployment of the active Eu and Sm species within the CaS host lattice.

CIS and CIGS based photovoltaic structures developed from electrodeposited precursors

In the present study we report the electrodeposition and characterization of CIS and CIGS thin films and a post-deposition thermal processing in vacuum to improve the film stoichiometry by incorporating additional In, Ga and Se. Different kinds of analyses showed that CIS as well as CIGS possess a very thin In-rich surface n-layer. The formation and characterization of solar cell structures from the electrodeposited precursor with the configuration glass/Cr/Mo/CIS(CIGS)/CdS/ZnO/MgF 2 is also reported. The optoelectronic properties such as Voc, Isc, FF, η etc. of the cells are presented.

A study of impurities in some CdS/CdTe photovoltaic cells prepared by wet­chemical methods using secondary ion mass spectrometry and X‐ray photoelectron spectroscopy

Quantitative Secondary Ion Mass Spectrometry has been used to determine the elemental profiles and concentrations of isotopes 12C, 16O, 34S and 35Cl within n-CdS/p-CdTe thin film photovoltaic cells. Chemical Bath Deposition (CBD) was used to deposit the CdS window layers. The annealing process induces the formation of a chloride-rich surface layer on CdS as evidenced from X-ray photoelectron spectroscopy measurements. The carbon impurity in heterostructures appears to influence the chloride-promoted recrystallisation of CdTe. High concentrations of 16O, of the order 1020–1021 atoms cm–3 throughout the cells, are consistent with the formation of oxide material in the post-deposition thermal processing. Isotopic profiles for 12C, 34S and 35Cl have similar maxima (≈1019 atoms cm–3) but concentrate at the CdS–CdTe interface. The relatively high tolerance to high concentrations of impurities in our cells suggests that wet chemical methods may have great potential in the fabrication of large area/low cost devices.

Correlation between magnetic homogeneity, oxygen content, and electrical and magnetic properties of perovskite manganite thin films

Perovskite manganese oxide materials known for the phenomenon of colossal magnetoresistance often exhibit anomalously large 1/f noise and large, temperature-dependent ferromagnetic resonance (FMR) linewidths. We show that in epitaxial films, these anomalies are very sensitive to oxygen partial pressure during film growth and to postdeposition thermal processing in oxygen, suggesting that oxygen stoichiometry plays a key role. We find that the temperature coefficient of resistance (TCR) at the metal–insulator transition increases and the FMR linewidth decreases as we increase the oxygen partial pressure during growth. Postdeposition heat treatment in oxygen leads to further increase in TCR and decrease in FMR linewidth, accompanied by a dramatic reduction in 1/f noise magnitudes.

Is Selective Cvd an Improvement for the Titanium Silicide Process in Sub-Quarter Micron Technology? A Phase Formation Study Using X-Ray Diffraction

ABSTRACTThe C54 phase formation process of titanium silicide was studied after selective chemical vapor despostion (CVD) onto very small silicon structures, to ascertain the efficacy of CVD to form low resistance contacts in sub-quarter micron technology. Because the selective CVD process forms silicide on any exposed silicon in a CMOS device, the process was studied on both polysilicon and Si (100) chips. The structures consisted of arrays of about 106 identical lines, 0.1 2.0 μm in width, depending on the chip. The CVD process employed TiCl4 and SiH4 for the most part as process gases and the depostion temperature ranged from 730–825°C. X-ray diffraction (XRD) was used to document the amount of C54 phase present after deposition. In some cases samples were annealed after deposition and the phase transformation behavior studied by in-situ XRD. The latter technique employed a synchrotron radiation source providng for rapid XRD spectra collection, so that the C49-C54 phase transformation could be examined with great precision in real time during rapid thermal annealing. The results of CVD depositions were compared to titanium silicide formed by sputter deposition of Ti on identical silicon chips, followed by a typical salicide protocol. Although the phase formation is affected by both film thickness and substrate temperature during CVD, the general result is that the C54 formation is more facile using the CVD process, especially for the smallest line dimensions. The findings are discussed with respect to nucleation processes occurring during growth and post-deposition thermal processing.

IS Selective CVD an Improvement for the Titanium Silicide Process in Sub-Quarter Micron Technology? A Phase Formation Study Using X-ray Diffraction

ABSTRACTThe C54 phase formation process of titanium silicide was studied after selective chemical vapor despostion (CVD) onto very small silicon structures, to ascertain the efficacy of CVD to form low resistance contacts in sub-quarter micron technology. Because the selective CVD process forms silicide on any exposed silicon in a CMOS device, the process was studied on both polysilicon and Si (100) chips. The structures consisted of arrays of about 106 identical lines, 0.1 2.0 μm in width, depending on the chip. The CVD process employed TiCl4 and SiH4 for the most part as process gases and the depostion temperature ranged from 730–825°C. X-ray diffraction (XRD) was used to document the amount of C54 phase present after deposition. In some cases samples were annealed after deposition and the phase transformation behavior studied by in-situ XRD. The latter technique employed a synchrotron radiation source providng for rapid XRD spectra collection, so that the C49-C54 phase transformation could be examined with great precision in real time during rapid thermal annealing. The results of CVD depositions were compared to titanium silicide formed by sputter deposition of Ti on identical silicon chips, followed by a typical salicide protocol. Although the phase formation is affected by both film thickness and substrate temperature during CVD, the general result is that the C54 formation is more facile using the CVD process, especially for the smallest line dimensions. The findings are discussed with respect to nucleation processes occurring during growth and post-deposition thermal processing.

Formation of iron or chromium doped epitaxial sapphire thin films on sapphire substrates

This work summarizes results of a simple procedure to incorporate dopants into the near surface region of single-crystal sapphire. We demonstrate the formation of iron-doped and chromium-doped sapphire thin films by solid-phase epitaxial growth. Amorphous alumina films of about 200–350 nm thickness were deposited onto single-crystal sapphire substrates. Fe or Cr ions were introduced into the films during deposition. A post-deposition thermal process was performed in oxidizing ambients at 800–1400 °C to induce epitaxial growth and to incorporate dopants. The epitaxial relationship of the grown film with the substrate was confirmed by both ion channeling and cross-sectional transmission electron microscopy. The growth kinetics were determined by time-resolved reflectivity measurements for different dopant concentrations. Ion channeling angular scans revealed that the Fe or Cr ions are incorporated onto octahedral sites (Al3+ sites) in the corundum structure as expected in equilibrium. External optical transmittance measurements exhibited absorption in the near ultraviolet range associated with the Fe3+ state. The substitution of Cr for Al3+ was also confirmed by the observation of R1 and R2 luminescence lines characteristic of ruby. The doping procedure has potential applications in the fabrication of thin film planar optical waveguides and thin film stress sensors.

The Role of the Lead Zirconate Titanate (PZT)-Pt Interface in the Anomalous Phase Transformation Kinetics in Sputtered Pzt Thin Film Capacitors at Sub-2000 Å Thicknesses

AbstractThe Pt-Lead Zirconate Titanate (PZT) thin film interface plays a key role in determining the electrical properties and phase transformation kinetics of Pt-PZT-Pt thin film capacitor structures. The results of the electrical and material properties of PZT (65/35) films that vary in thickness between 500 Å to 4000 Å deposited by DC-magnetron sputtering under identical deposition conditions, and subjected to the same post-deposition thermal processing conditions shows that the Pt-PZT interface dominates thin film properties at low thicknesses (≦ 2000 Å). The charge storage density (Qc') and maximum polarization (Pmax) shows an anomalous variation with thickness, showing an initial increase followed by a drastic decrease as the film thickness is scaled down to 500Å. Significant interdiffusion at the PZT film-Pt electrode retards the pyrochlore-to-perovskite phase transformation nucleation and growth rate in PZT films of thickness 2000Å and lower. Gate polarity dependence of the time-tobreakdown and the degradation field is observed for all PZT film thicknesses (including 4000Å). This indicates that the ferroelectric film-electrode interface has an important role to play in determining the electrical reliability properties even in the 4000Å thick PZT film, although Qc' and Pmax are not adversely affected at these thicknesses.

Thermal stabilization of device quality films deposited at low temperatures

The effects of postdeposition furnace annealing, at temperatures typical of metal–oxide semiconductor (MOS) fabrication processes, on gate oxides formed by remote plasma-enhanced chemical vapor deposition (remote PECVD) are discussed. SiO2 films were prepared by (1) remote PECVD at substrate temperatures of 200 and 400 °C, and (2) by thermal oxidation of silicon at temperatures from 850 to 1150 °C. Postdeposition thermal processing was carried out in industrial-type diffusion furnaces in both N2/O2 and N2/H2 ambients over a temperature range of 400–1050 °C. Film properties were studied by infrared spectroscopy, ellipsometry, and by measurements of capacitance voltage (C–V) characteristics in MOS device structures. Postdeposition thermal processing at temperatures of 400 °C and above was shown to modify both the structure and electrical properties of deposited SiO2 films. It is shown that changes in the as-deposited film properties occur by two different relaxation mechanisms, one of which is operative in the temperature range up to 750 °C and the other from 750 to 1050 °C, and both of which are different from the viscoelastic relaxation process observed in thermally grown SiO2.

The effect of post-deposition thermal processing on MOS gate oxides formed by remote PECVD

The effects of post-deposition thermal exposure, at temperatures typical of MOS fabrication processes, on gate oxides formed by remote plasma enhanced chemical vapor deposition (RPECVD) is discussed. SiO2 films were prepared by (1) thermal oxidation of silicon at temperatures from 700 to 1150° C, and (2) by RPECVD at a substrate temperature of 350° C. Post deposition thermal processing was achieved by rapid thermal annealing for 100 sec from 850–1200° C. Film properties were studied by infrared spectroscopy (IR), ellipsometry, and by measurements of stress, capacitance voltage characteristics, and dielectric breakdown. Post-formation, thermal processing in the range of 850–1200° C was shown to modify both thermally grown and deposited oxides, but it has been shown that RPECVD films could be stabilized against post-deposition changes by rapid thermal annealing at temperatures of about 900° C for periods of at least 100 sec.

Microwave surface resistance in Tl-based superconducting thin films

We report measurements of microwave surface resistance in Tl-based superconductor thin films made by laser ablation followed by a post-deposition thermal process. The films were measured by using cavity methods. The data at 9.5 and 148 GHz indicate that the residual resistance scales as f2. At 77 K, the 9.5 GHz surface resistance is ten times smaller than oxygen-free high-conductance copper at the same temperature and frequency. The 9.5 GHz measurement also indicates that the film-substrate interface does not cause more microwave loss than the film surface.