post-Moore Era Research Articles

First-principles studies of strain-tunable InN monolayer: applications for switching and optoelectronic devices

Abstract Two-dimensional (2D) materials are attracting significant attention for their potential applications in the post-Moore era. In this work, we systematically investigate the effect of strains on the electronic structure, transport and optoelectronic properties of 2D Indium nitride (InN) monolayer using density functional theory and non-equilibrium Green’s function methods. The results show that strains can modulate the electronic properties. Specifically, biaxial strain triggers the transition from semiconductor to metal and indirect to direct band gap. On this basis, the constructed InN-based nanodevice exhibits current switching ratios up to 1010. In addition, the optoelectronic device based on InN monolayer exhibits a robust photoelectric response in the red light. Meanwhile, biaxial strain can improve the optoelectronic performance of InN-based optoelectronic devices. The compressive strains blue-shift the photocurrent peaks of the InN monolayer, which effectively modulates its detection range in the visible light region. These findings underscore the potential applications in nanotechnology, particularly in nano-switches and optoelectronic devices.

Integrated photonic modular arithmetic processor

Integrated photonic computing has emerged as a promising approach to overcome the limitations of electronic processors in the post-Moore era. However, present integrated photonic computing systems face challenges in achieving high-precision calculations, consequently limiting their potential applications, and their heavy reliance on analog-to-digital (AD) and digital-to-analog (DA) conversion interfaces undermines their performance. Here we propose an innovative photonic computing architecture featuring scalable calculation precision and, to our knowledge, a novel photonic conversion interface. By leveraging the residue number system (RNS) theory, the high-precision calculation is decomposed into multiple low-precision modular arithmetic operations executed through optical phase manipulation. Those operations directly interact with the digital system via our proposed optical digital-to-phase converter (ODPC) and phase-to-digital converter (OPDC). Through experimental demonstrations, we showcase a calculation precision of 9 bits and verify the feasibility of the ODPC/OPDC photonic interface. This approach paves the path towards liberating photonic computing from the constraints imposed by limited precision and AD/DA converters.

A nonvolatile magnon field effect transistor at room temperature

Information industry is one of the major drivers of the world economy. Its rapid growth, however, leads to severe heat problem which strongly hinders further development. This calls for a non-charge-based technology. Magnon, capable of transmitting spin information without electron movement, holds tremendous potential in post-Moore era. Given the cornerstone role of the field effect transistor in modern electronics, creating its magnonic equivalent is highly desired but remains a challenge. Here, we demonstrate a nonvolatile three-terminal lateral magnon field effect transistor operating at room temperature. The device consists of a ferrimagnetic insulator (Y3Fe5O12) deposited on a ferroelectric material [Pb(Mg1/3Nb2/3)0.7Ti0.3O3 or Pb(Zr0.52Ti0.48)O3], with three Pt stripes patterned on Y3Fe5O12 as the injector, gate, and detector, respectively. The magnon transport in Y3Fe5O12 can be regulated by the gate voltage pulses in a nonvolatile manner with a high on/off ratio. Our findings provide a solid foundation for designing energy-efficient magnon-based devices.

Piezo-VFETs: Vacuum Field Emission Transistors Controlled by Piezoelectric MEMS Sensors as an Artificial Mechanoreceptor with High Sensitivity and Low Power Consumption.

As one of the most promising electronic devices in the post-Moore era, nanoscale vacuum field emission transistors (VFETs) have garnered significant attention due to their unique electron transport mechanism featuring ballistic transport within vacuum channels. Existing research on these nanoscale vacuum channel devices has primarily focused on structural design for logic circuits. Studies exploring their application potential in other vital fields, such as sensors based on VFET, are more limited. In this study, for the first time, the design of a vacuum field emission transistor (VFET) coupled with a piezoelectric microelectromechanical (MEMS) sensing unit is proposed as the artificial mechanoreceptor for sensing purposes. With a negative threshold voltage similar to an N-channel depletion-mode metal oxide silicon field effect transistor, the proposed VFET has its continuous current tuned by the piezoelectric potential generated by the sensing unit, amplifying the magnitude of signals resulting from electromechanical coupling. Simulations have been conducted to validate the feasibility of such a configuration. As indictable from the simulation results, the proposed piezoelectric VFET exhibits high sensitivity and an electrically adjustable measurement range. Compared to the traditional combination of piezoelectric MEMS sensors and solid-state field effect transistors (FETs), the piezoelectric VFET design has a significantly reduced power consumption thanks to its continuous current that is orders of magnitude smaller. These findings reveal the immense potential of piezoelectric VFET in sensing applications, building up the basis for using VFETs for simple, effective, and low-power pre-amplification of piezoelectric MEMS sensors and broadening the application scope of VFET in general.

Rational Design of Fluorinated 2D Polymer Film Based on Donor-Accepter Architecture toward Multilevel Memory Device for Neuromorphic Computing.

Fluorine-containing 2D polymer (F-2DP) film is a desired system to regulate the charge transport in organic electronics but rather rarely reports due to the limited fluorine-containing building blocks and difficulties in synthesis. Herein, a novel polar molecule with antiparallel columnar stacking is synthesized and further embedded into an F-2DP system to control over the crystallinity of F-2DP film through self-complementary π-electronic forces. The donor-accepter-accepter'-donor' (D-A-A'-D') structure regulates the charge transportation efficiently, inducing multilevel memory behavior through stepwise charge capture and transfer processes. Thus, the device exhibits ternary memory behavior with low threshold voltage (Vth1 of 1.1V, Vth2 of 2.0V), clearly distinguishable resistance states (1:102:104) and ternary yield (83%). Furthermore, the stepwise formation of the charge complex endows the device with a wider range to regulate the conductive state, which allows its application in brain-inspired neuromorphic computing. Modified National Institute of Standards and Technology recognition can reach an accuracy of 86%, showing great potential in neuromorphic computing applications in the post-Moore era.

A hot-emitter transistor based on stimulated emission of heated carriers

Hot-carrier transistors are a class of devices that leverage the excess kinetic energy of carriers. Unlike regular transistors, which rely on steady-state carrier transport, hot-carrier transistors modulate carriers to high-energy states, resulting in enhanced device speed and functionality. These characteristics are essential for applications that demand rapid switching and high-frequency operations, such as advanced telecommunications and cutting-edge computing technologies1–5. However, the traditional mechanisms of hot-carrier generation are either carrier injection6–11 or acceleration12,13, which limit device performance in terms of power consumption and negative differential resistance14–17. Mixed-dimensional devices, which combine bulk and low-dimensional materials, can offer different mechanisms for hot-carrier generation by leveraging the diverse potential barriers formed by energy-band combinations18–21. Here we report a hot-emitter transistor based on double mixed-dimensional graphene/germanium Schottky junctions that uses stimulated emission of heated carriers to achieve a subthreshold swing lower than 1 millivolt per decade beyond the Boltzmann limit and a negative differential resistance with a peak-to-valley current ratio greater than 100 at room temperature. Multi-valued logic with a high inverter gain and reconfigurable logic states are further demonstrated. This work reports a multifunctional hot-emitter transistor with significant potential for low-power and negative-differential-resistance applications, marking a promising advancement for the post-Moore era.

(Invited) Biofabricated Carbon Nanotube Electronics: Toward Energy-Efficient Switches in Multi-Dimensional Integration

High-performance Si devices are approaching their physical boundaries during the continuous miniaturization following Moore's Law. New semiconductor materials are in urgent necessity, among which, carbon nanotubes（CNTs）are suggested by the International Technology Roadmap for Semiconductors（ITRS）as potential candidate to continue Moore's Law due to its quasi-one-dimensional structure and excellent electrical properties.To unleash the advantages of CNTs in the post-Moore era, optimizing materials morphology, interfaces composition, and integrated structure proves to be pivotal, which constitutes the basic idea of our research. Regarding material morphology, we have fabricated evenly spaced parallel CNT materials with a spacing down to 10nm, by employing the DNA-directed high-precision assembly method. At CNT interface, we have realized fast on/off switching high-performance switches by engineering the interfacial compositions. Individual CNT displays 1G0 conductance with subthreshold swing superior to conventional Si transistors. Furthermore, we built the preliminary foundation to integrate CNT transistors into multi-dimensional circuits. Based on the control of material, interface, and integration structure, our work elucidates the potential of constructing energy-efficient computing circuit using carbon nanotube electronics.

Data-Driven Weather Forecasting and Climate Modeling from the Perspective of Development

Accurate and rapid weather forecasting and climate modeling are universal goals in human development. While Numerical Weather Prediction (NWP) remains the gold standard, it faces challenges like inherent atmospheric uncertainties and computational costs, especially in the post-Moore era. With the advent of deep learning, the field has been revolutionized through data-driven models. This paper reviews the key models and significant developments in data-driven weather forecasting and climate modeling. It provides an overview of these models, covering aspects such as dataset selection, model design, training process, computational acceleration, and prediction effectiveness. Data-driven models trained on reanalysis data can provide effective forecasts with an accuracy (ACC) greater than 0.6 for up to 15 days at a spatial resolution of 0.25°. These models outperform or match the most advanced NWP methods for 90% of variables, reducing forecast generation time from hours to seconds. Data-driven climate models can reliably simulate climate patterns for decades to 100 years, offering a magnitude of computational savings and competitive performance. Despite their advantages, data-driven methods have limitations, including poor interpretability, challenges in evaluating model uncertainty, and conservative predictions in extreme cases. Future research should focus on larger models, integrating more physical constraints, and enhancing evaluation methods.

Out-of-Plane Ferroelectricity in Two-Dimensional 1T‴-MoS2 Above Room Temperature.

Two-dimensional (2D) molybdenum disulfide (MoS2), one of the most extensively studied van der Waals (vdW) materials, is a significant candidate for electronic materials in the post-Moore era. MoS2 exhibits various phases, among which the 1T‴ phase possesses noncentrosymmetry. 1T‴-MoS2 was theoretically predicted to be ferroelectric a decade ago, but this has not been experimentally confirmed until now. Here, we have prepared high-purity 2D 1T‴-MoS2 crystals and experimentally confirmed the room-temperature out-of-plane ferroelectricity. The noncentrosymmetric crystal structure in 2D 1T‴-MoS2 was convinced by atomically resolved transmission electron microscopic imaging and second harmonic generation (SHG) measurements. Further, the ferroelectric polarization states in 2D 1T‴-MoS2 can be switched using piezoresponse force microscopy (PFM) and electrical gating in field-effect transistors (FETs). The ferroelectric-to-paraelectric transition temperature is measured to be about 350 K. Theoretical calculations have revealed that the ferroelectricity of 2D 1T‴-MoS2 originates from the intralayer charge transfer of S atoms within the layer. The discovery of intrinsic ferroelectricity in the 1T‴ phase of MoS2 further enriches the properties of this important vdW material, providing more possibilities for its application in the field of next-generation electronic devices.

Designing semiconductor materials and devices in the post-Moore era by tackling computational challenges with data-driven strategies.

In the post-Moore's law era, the progress of electronics relies on discovering superior semiconductor materials and optimizing device fabrication. Computational methods, augmented by emerging data-driven strategies, offer a promising alternative to the traditional trial-and-error approach. In this Perspective, we highlight data-driven computational frameworks for enhancing semiconductor discovery and device development by elaborating on their advances in exploring the materials design space, predicting semiconductor properties and optimizing device fabrication, with a concluding discussion on the challenges and opportunities in these areas.

Photocurrent Ambipolar Behavior in Phase Junction of a Ga2O3 Porous Nanostructure for Solar-Blind Light Control Logic Devices.

Photoelectrochemical (PEC) devices are the most similar artificial devices to the nervous system, which is expected to solve the problem of complex computer/nervous system interface (solid-liquid interface) and multifunctional integration (photoelectric fusion) required in the post-Moore era. Based on the different photocurrent ambipolar behavior and different deep ultraviolet solar-blind spectral photoresponse characteristics of α-Ga2O3 and β-Ga2O3, we designed and constructed the Ga2O3 porous nanostructure PEC device with an adjustable photocurrent bipolar behavior through constructing an α/β phase junction core-shell structure by adjusting the thickness and the surface state of the shell layer. The switching point of the α/β-Ga2O3 ambipolar photocurrent shifts toward negative values with the increase of β-Ga2O3 shell layer thicknesses, and adjustable Boolean logic gates are prepared using the voltage as the input source with a high accuracy manipulated by solar-blind deep ultraviolet light. The controllable solar-blind logic gates based on the ambipolar photocurrent behavior of α/β-Ga2O3 presented in this study offer a new path for the photoelectric device multifunctional integration needed in the post-Moore era, which can be used in the creation of Ga2O3 half adders and full adders, as well as in the construction of four-input OR gates.

Advanced Packaging Trends in the Semiconductor Industry

Advanced packaging is an important technology that is now taking over from advanced processes to help the semiconductor industry continue to grow. The researcher found that the personnel in contact with the semiconductor industry chain have already had a preliminary understanding of advanced packaging, however, the future development trend of the advanced packaging industry still lacks a comprehensive knowledge. Therefore, the research topic of this paper is the development trend of advanced packaging industry. The research methodology of this paper is as follows: firstly, to understand the concept and development trend of advanced packaging, secondly, to list the factors driving the development of advanced packaging, and finally, to understand the development direction of international enterprises in advanced packaging. This paper finds that after the chip process technology has entered the "post-Moore era", advanced packaging has been widely used in the fields of high-end logic chips, memories, RF chips, image processing chips, touch chips and so on. Advanced packaging technology tends to be diversified in function, stacking and connection. According to Yole, a market research organization, the global share of advanced packaging in the IC packaging and testing market will continue to increase. At the same time, Yole predicts that the global compound annual growth rate of traditional packaging will be only 1.9% from 2019 to 2025, which is much lower than the growth rate of advanced packaging. Advanced packaging is the key path to improve system performance in the post-Moore era.

2D Bi-doped SnSe ferroelectric memristor integrating all-in-one sensing-memory-computing

Two-dimensional (2D) layered ferroelectric materials are an emerging semiconductor expected to satisfy people's pursuit of post-Moore era of the small-size, high-efficiency, and intellectualization. However, the asymmetric coercive-field of reported 2D ferroelectrics which was not conducive to the linearity and symmetry of conductance regulation, limiting their application. Here, we have confirmed Bi-doped can greatly enhance the symmetry of a coercive voltage (±2.4 V) of 2D-layered SnSe, and designed a multifunctional memristor whose conductance is regulated by the ferroelectric polarization direction. As the synaptic long/short-term plasticity (PPF, PTP, symmetrical STDP), the bio-fire and temporal/spatial integration functions of neurons might be emulated by changing the parameters of electrical pulses. Furthermore, under the synergistic effect of photoelectric field, the “OR/AND” logic computing and store in situ was experimentally demonstrated, meanwhile, 8-level nonvolatile photoresponses and the “LOVE” information of the 3-bit octal number combination was locally sensed, demodulated and stored. This work can provide a new way for the future development of smart hardware in photoelectric neuromorphic and edge computing systems.

Nonvolatile behavior of resistive switching memory in Ag/WOx/TiOy/ITO device based on WOx/TiOy heterojunction

Two-terminal structure memristors are the most promising electronic devices that could play a significant role in artificial intelligence applications of the next generation and the post-Moore era. In this work, we fabricated the memristive device by depositing a heterojunction WOx/TiOy functional layer onto an indium tin oxide substrate using magnetron sputtering. The Ag/WOx/TiOy/ITO device exhibits improved memory behavior of bipolar resistive switching (RS) nonvolatile compared to TiOy-based single-layer memristors, enabling it to meet high-density information storage requirements. Moreover, our device exhibited the coexistence of the negative differential resistance effect and the behavior of the RS memory. Through a comprehensive analysis of conductivity on the curve of current–voltage (I–V), a physical model based on the mechanism of space charge-limited current, ohmic conduction, and Schottky emission was suggested to explain the behavior device RS memory. This study's findings demonstrate that including a heterojunction bilayer WOx/TiOy as a functional layer can significantly improve the performance of memristive devices. This advancement expands the potential application of ferroelectric metallic oxide heterojunctions within the field of memristors.

Carbon nanotube integrated circuit technology: purification, assembly and integration

Abstract As the manufacturing process of silicon-based integrated circuits (ICs) approaches its physical limit, the quantum effect of silicon-based field-effect transistors (FETs) has become increasingly evident. And the burgeoning carbon-based semiconductor technology has become one of the most disruptive technologies in the post-Moore era. As one-dimensional nanomaterials, carbon nanotubes (CNTs) are far superior to silicon at the same technology nodes of FETs because of their excellent electrical transport and scaling properties, rendering them the most competitive material in the next-generation ICs technology. However, certain challenges impede the industrialization of CNTs, particularly in terms of material preparation, which significantly hinders the development of CNT-based ICs. Focusing on CNT-based ICs technology, this review summarizes its main technical status, development trends, existing challenges, and future development directions.

Time-space multiplexed photonic-electronic digital multiplier

Optical computing has shown immense application prospects in the post-Moore era. However, as a crucial component of logic computing, the digital multiplier can only be realized on a small scale in optics, restrained by the limited functionalities and inevitable loss of optical nonlinearity. In this paper, we propose a time-space multiplexed architecture to realize large-scale photonic-electronic digital multiplication. We experimentally demonstrate an 8×2-bit photonic-electronic digital multiplier, and the multiplication with a 32-bit number is further executed at 25 Mbit/s to demonstrate its extensibility and functionality. Moreover, the proposed architecture has the potential for on-chip implementation, and a feasible integration scheme is provided. We believe the time-space multiplexed photonic-electronic digital multiplier will open up a promising avenue for large-scale photonic digital computing.

Study on the Manufacturability of XDFOI Package with Organic RDLs (XDFOI-O)

The concept of chiplet has been proposed in the post Moore era, while how to achieve the layout of multiple chips of different processes and sizes in the manufacturing process is a coming problem that needs to be considered. Different layouts may significantly affect the manufacturability during the packaging process. Prospective finite element analysis (FEA) can evaluate various layouts by optimizing the layout and increasing the placement of dummy chips as stiffeners, thereby selecting the best layout and combination method. In addition, the characteristic of chiplet packaging is that multiple chips may come from different sources, such as different foundries, processes, sizes, or even thicknesses. This really poses challenges to the subsequent flip chip and wafer thinning process for leveling the total package. It is necessary to confirm the evaluation of the impact of chips with different thicknesses and underfill coverage in the process, so as to ensure the consistency in processing and improve the yield of packages.

Fast and robust multilevel optoelectronic memory based on van der Waals heterostructure

Optoelectronic memory (OEM) has attracted tremendous attention for its great potential to boost the storage capacity of memory chips and break through the von Neumann bottleneck in the post-Moore era. Two-dimensional (2D) van der Waals (vdW) heterostructures, formed by artificially stacking different 2D layered materials, offer tremendous possibilities in OEMs due to their extraordinary capability to integrate and process optical/electrical signals. However, the realization of 2D vdW OEMs with high writing speed and robust memory performance has long been challenging. Here, we report a 2D vdW OEM consisting of tungsten diselenide (WSe2) and hexagonal boron nitride, which functions based on the fast charge transfer dynamics at a 2D interface. The OEM demonstrates high writing speed reaching up to 50 μs, approximately one order of magnitude faster than those of other 2D OEMs. Moreover, the outstanding robustness of such OEM is demonstrated by long retention time exceeding 14 days, together with a broad temperature endurance window from 100 to 420 K. Additionally, through continuously switching laser pulse on the OEM, we achieve 17 distinct current levels (over 4-bit storage) with random access. Our findings envision 2D vdW heterostructure-based OEM as a potential platform to overcome the “memory wall” in the conventional von Neumann configuration and to promote a promising paradigm for big data storage.

A Study of Advancing Ultralow-Power 3D Integrated Circuits with TEI-LP Technology and AI-Enhanced PID Autotuning

The 3D integrated circuit (3D-IC) is garnering significant attention from academia and industry as a key technology leading the post-Moore era, offering new levels of efficiency, power, performance, and form-factor advantages to the semiconductor industry. However, thermal management in 3D-ICs presents a critical challenge that must be overcome to ensure prosperity for this technology. Unlike traditional thermal management solutions that perceive heat generation in 3D-ICs negatively and aim to eliminate it, this paper proposes, for the first time, a thermal management method that positively utilizes heat to achieve low-power operation in 3D-ICs. This approach is based on a novel discovery that circuits can reduce power consumption at higher temperatures by leveraging the temperature effect inversion (TEI) phenomenon in ultralow-voltage (ULV) operating circuits, a characteristic of low-power techniques (TEI-LP techniques). Along with a detailed explanation of this discovery, this paper introduces new thermal management technologies for practical application in 3D-ICs. Furthermore, to achieve optimal energy efficiency with the proposed technology, we develop a temperature controller essential for this purpose. The developed controller is a deep learning-based PID autotuner. This paper proves the theoretical validity of the AI control algorithm designed for this purpose and demonstrates the functional correctness and power-saving effectiveness of the developed controller through intensively conducted simulations.

Full-Custom 90 nm CNTFET Process Design Kit: Characterization, Modeling, and Implementation

As the semiconductor industry enters the post-Moore era, the carbon nanotube field-effect transistor (CNTFET) has become a powerful substitute for silicon-based transistors beyond 5 nm process nodes due to its high mobility, low power consumption, and ultra-thin-body electrical advantages. Carbon-based transistor technology has made significant progress in device manufacture and preparation, but carbon-based process design kits (PDKs) that meet the standards of commercial design tools are still an important bottleneck hindering the development of carbon-based integrated circuits. For the first time, a complete full-custom 90 nm CNTFET PDK is proposed in this paper, which includes Pcells for transistors, resistors, and capacitors; a compact model; DRC/LVS/PEX rules; and a standard cell and timing library. It can support the entire design flow of analog, digital, and mixed-signal carbon-based integrated circuits. To achieve an accurate compact model, the back-gate effect of CNTFETs and the influence of gate/drain voltage on transport probability are analyzed. Then the theoretical formulas for mobility and channel current are established. The comparison of the simulation and test results of CNTFET characteristics proves the accuracy of the compact model. Using this PDK, combined with standard IC design tools and design flow, the circuit and layout of an operational amplifier, SRAM, and 8-bit counter are completed. The simulation results verify the correctness and effectiveness of the PDK, laying a solid foundation for the large-scale industrialization of carbon-based integrated circuits.