Post-etch Treatment Research Articles

Facile Tailoring of Surface Terminations of MXenes by Doping Nb Element: Toward Extraordinary Pseudocapacitance Performance.

MXenes show promising potential in supercapacitors due to their unique two-dimensional (2D) structure and abundant surface functional groups. However, most studies about MXenes have focused on tailoring surface structures by alternating synthesis methods or post-etch treatments, and little is known about the inherent relationship between surface groups and M elements. Herein, we propose a simple and novel strategy to adjust the surface structure of few-layered MXene flakes by adding a small amount of Nb element. Because of the strong affinity between Nb and O elements, the as-received V1.8Nb0.2CTx and Ti2.7Nb0.3C2Tx MXenes have much fewer -F functional groups and a higher O content than V2CTx and Ti3C2Tx MXenes, respectively. Thus, both V1.8Nb0.2CTx and Ti2.7Nb0.3C2Tx MXenes show enhanced pseudocapacitance performance. Especially, V1.8Nb0.2CTx delivers an ultrahigh volumetric capacitance of 1698 F/cm3 at a scan rate of 2 mV/s. Moreover, benefiting from the high activity of MAX precursors obtained through a fast self-propagating high-temperature synthesis, the etching time to produce V-based MXenes is much shorter than that in previous reports. Therefore, the results presented here are applicable to the surface engineering and rational design of 2D MXene materials and develop them into promising, cost-effective electrode materials for supercapacitors or other energy-storage equipment.

Supercritical Carbon Dioxide Treatment of Porous Silicon Increases Biocompatibility with Cardiomyocytes.

Porous silicon is of current interest for cardiac tissue engineering applications. While porous silicon is considered to be a biocompatible material, it is important to assess whether post-etching surface treatments can further improve biocompatibility and perhaps modify cellular behavior in desirable ways. In this work, porous silicon was formed by electrochemically etching with hydrofluoric acid, and was then treated with oxygen plasma or supercritical carbon dioxide (scCO2). These processes yielded porous silicon with a thickness of around 4 μm. The different post-etch treatments gave surfaces that differed greatly in hydrophilicity: oxygen plasma-treated porous silicon had a highly hydrophilic surface, while scCO2 gave a more hydrophobic surface. The viabilities of H9c2 cardiomyocytes grown on etched surfaces with and without these two post-etch treatments was examined; viability was found to be highest on porous silicon treated with scCO2. Most significantly, the expression of some key genes in the angiogenesis pathway was strongly elevated in cells grown on the scCO2-treated porous silicon, compared to cells grown on the untreated or plasma-treated porous silicon. In addition, the expression of several apoptosis genes were suppressed, relative to the untreated or plasma-treated surfaces.

Formation Mechanism of Rounded SiGe-Etch Front in Isotropic SiGe Plasma Etching for Gate-All-Around FETs

We investigated the formation mechanism of a rounded silicon-germanium (SiGe)-etch front (rounding) in gate-all-around field-effect transistor (GAA-FET) manufacturing. This rounding is created by the isotropic etching of the SiGe layer after anisotropic etching of the SiGe/Si stack, which degrades device characteristics. The etch-time dependence of the rounding amount during isotropic SiGe etching with nitrogen trifluoride plasma indicates that rounding is mainly formed in an initial stage of SiGe etching, namely, etch time less than 15 s. Cross-sectional scanning transmission electron microscopy and energy dispersive x-ray spectroscopy (STEM EDX) measurement indicated that a Ge-containing layer formed on the sidewall of SiGe/Si patterns before isotropic SiGe etching. From these results, we propose a formation model of SiGe rounding below. The Ge composition in the Ge-containing layer has a gradient due to ion-assisted Ge diffusion during anisotropic etching of the SiGe/Si stack. This gradient induces rounding during isotropic SiGe etching because the etch rate of the SiGe layer decreases as the Ge composition decreases. To validate our model, the Ge-containing layer after anisotropic etching was removed by post-etch treatment and the Ge spectra on the sidewall was reduced to the detection limit of STEM EDX. As a result, the rounding amount after isotropic SiGe etching improved from 2.7 to 1.8 nm. This reduction indicates that the formation of the Ge-containing layer during anisotropic etching of the SiGe/Si stack is one of the main causes of rounding after isotropic SiGe etching.

Improvement of Electron Transport Property and on-Resistance in Normally-OFF Al₂O₃/AlGaN/GaN MOS-HEMTs Using Post-Etch Surface Treatment

Post-etch surface treatment technique was developed for normally-OFF recess-gate Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs). By removing the residues and smoothing surface morphology after plasma etch, the diffusion-controlled interface oxidation (DCIO) and wet etch in MOS-HEMTs lead to a decrease in interface traps from 1.04 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> to 6.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> with a filling voltage of 12 V. Field-effect mobility extracted in the linear region is 48 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s for MOS-HEMTs with an optimized post-etch surface treatment process, 33% larger than the case with the conventional chemical clean process. Due to the increased electron mobility and decreased sheet resistance beneath the gate by over 30%, normally-OFF MOS-HEMTs with DCIO and wet etch exhibit a remarkable increase in output current by about 29% and an increase in peak transconductance from 35 to 41 mS/mm. The optimized post-etch surface treatment method also enhances blocking voltage from 120 to 230 V by suppressing the leakage current resulting from gate soft breakdown. Dynamic characterization shows that the normalized ON-resistance is increased by double with drain stress up to 80 V, and various post-etch surface treatment processes have little effect on current collapse. Two types of threshold voltage shifts caused by interface trapping and border trapping are observed in the normally-OFF MOS-HEMTs, which keeps stable with an increase in temperature up to 125 °C.

Interface and border trapping effects in normally-off Al2O3/AlGaN/GaN MOS-HEMTs with different post-etch surface treatments**Project supported by the National Natural Science Foundation of China (Grant Nos. 61704124, 11690042, and 61634005).

Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interface oxidation treatment and wet etch process were adopted to improve the interface quality of MOS-HEMTs. With capacitance–voltage (C–V) measurement, the density of interface and border traps were calculated to be 1.13 × 1012 cm−2 and 6.35 × 1012 cm−2, effectively reduced by 27% and 14% compared to controlled devices, respectively. Furthermore, the state density distribution of border traps with large activation energy was analyzed using photo-assisted C–V measurement. It is found that irradiation of monochromatic light results in negative shift of C–V curves, which indicates the electron emission process from border traps. The experimental results reveals that the major border traps have an activation energy about 3.29 eV and the change of post-etch surface treatment process has little effect on this major activation energy.

High voltage GaN p‐n diodes formed by selective area regrowth

GaN p-n diodes were formed by selective area regrowth on freestanding GaN substrates using a dry etch, followed by post-etch surface treatment to reduce etch-induced defects, and subsequent regrowth into wells. Etched-and-regrown diodes with a 150 μm diameter achieved 840 V operation at 0.5 A/cm 2 reverse current leakage and a specific on-resistance of 1.2 mΩ·cm 2 . Etched-and-regrown diodes were compared with planar, regrown diodes without etching on the same wafer. Both types of diodes exhibited similar forward and reverse electrical characteristics, which indicate that etch-induced defectivity of the junction was sufficiently mitigated so as not to be the primary cause for leakage. An area dependence for forward and reverse leakage current density was observed, suggesting that the mesa sidewall provided a leakage path.

Investigation of dry-etch-induced defects in &amp;gt;600 V regrown, vertical, GaN, p-n diodes using deep-level optical spectroscopy

The impact of dry-etch-induced defects on the electrical performance of regrown, c-plane, GaN p-n diodes where the p-GaN layer is formed by epitaxial regrowth using metal-organic, chemical-vapor deposition was investigated. Diode leakage increased significantly for etched-and-regrown diodes compared to continuously grown diodes, suggesting a defect-mediated leakage mechanism. Deep level optical spectroscopy (DLOS) techniques were used to identify energy levels and densities of defect states to understand etch-induced damage in regrown devices. DLOS results showed the creation of an emergent, mid-gap defect state at 1.90 eV below the conduction band edge for etched-and-regrown diodes. Reduction in both the reverse leakage and the concentration of the 1.90 eV mid-gap state was achieved using a wet chemical treatment on the etched surface before regrowth, suggesting that the 1.90 eV deep level contributes to increased leakage and premature breakdown but can be mitigated with proper post-etch treatments to achieve &amp;gt;600 V reverse breakdown operation.

The Line Roughness Improvement in Self-aligned Multiple Patterning

Multi-patterning has been widely used in the semiconductor industry to enable the continued scaling requirement such as Fin, Gate, and critical Metal lines. Either Self-aligned Multiple Patterning (SaMP) or Litho-Etch/Litho-Etch (LELE) shows plasma etch become more dominant for the line edge and width roughness (LER/LWR) than single patterning technology [1]. To mitigate the strict line roughness requirements for advanced technology nodes (14nm and below), we proposed and demonstrated a novel nitrogen-based Inductively Coupled Plasma (ICP) treatment and an argon-based Capacitively Coupled Plasma (CCP) treatment on LER/LWR improvement, separately. Both recipes are optimized with an optimal design experiment (ODE) statistical method. The optimal organic mandrel etch recipe can improve the LER of the final pattern to 1.2nm. Furthermore, two effective Si mandrel post etch treatment (PET) methods are investigated: special surface plasma treatment and H2 anneal. The H2 anneal effect was found related to the capping layer, different from former published paper. We also found out the different chemistry in Spacer etch can impact line roughness but trade-off with defect performance. Finally, we achieved a 20% LWR improvement of final pattern in a self-aligned quadruple patterning (SAQP) without any side effect.

Influence of surface treatments in flexural strength and superficial topography of a lithium disilicate ceramic

The aim of the study was to evaluate the influence of different surface post-etching treatments in flexural strength, contact angle and surface roughness of a lithium disilicate ceramic. 60 bars (16x2x4mm) were divided in six groups (n=10): C, no treatment; HF, hydrofluoric acid for 20s (HF) + washing (60s), drying (30s); HFL, HF + washing (60s), drying (30s) and luting; HFNL, HF + washing (60s) + neutralization with sodium bicarbonate (SB) for 40s + washing (5s), drying (30s) and luting; HFUL, HF + washing (60s) + ultrasonic bath (UB) for 4 min, drying (30s) and luting; HFNUL, HF + washing (60s) + SB (40s) + UB (4 min) and luting. The bars were submitted to three-points flexural strength test. To analyze roughness and contact angle 25 ceramic blocks (12x7x7 mm) were divided into five groups (n=5): C - no treatment; HF - HF ; HFU - HF and UB for 5 min ; HFN - HF and SB; HFNU - HF, UB and SB. A scanning electron microscope (SEM) analysed the surface of the samples. ANOVA one-way statistical analysis was done for comparison of results. There was no statistical difference for flexural strength (p-value=0.15) and for surface roughness (p-valor=0.15). However, it was obtained statistically significant difference for contact angle (p-valor=0.00). SEM images showed precipitates after the acid etching, which were removed by post-etching treatments. It can be concluded that the different post-etching surface treatments did not increase the flexural strength, surface roughness and ceramic wetting, but it influenced the SEM images.

An effective process to remove etch damage prior to selective epitaxial growth in 3D NAND flash memory

An effective post etch treatment (PET) process was proposed to eliminate etch damage in the channel hole, of which the depth and the aspect ratio is beyond 3 μm and 30:1 respectively, prior to selective epitaxial growth (SEG) in three dimensions (3D) NAND flash memory. In this work, it is demonstrated that the damaged layer both at the channel hole bottom and sidewall induced by capacitively coupled plasma (CCP) was effectively eliminated using low energy plasma of CL2 + NF3/CH2F2 in PET, and then obtaining an excellent surface condition in channel hole and fabricating a void-free SEG epitaxial layer.

The Line Roughness Improvement in Self-Aligned Multiple Patterning

Multi-patterning has been widely adopted in the semiconductor manufacturing industry to enable the continued scaling requirement such as fin, gate, and critical metal lines. Either Self-aligned Multiple Patterning (SaMP) or Litho-Etch-Litho-Etch (LELE) shows plasma etch becomes more dominant for the line roughness than single patterning technology (1). To mitigate the strict line roughness requirements for advanced technology nodes, we demonstrated a novel nitrogen-based inductively coupled plasma (ICP) treatment. The recipe was optimized with an optimal design experiment (ODE). The optimal mandrel etch recipe coupled with HBr plasma curing can improve 60% line edge roughness (LER) of the final pattern. Furthermore, two post etch treatment (PET) methods were investigated on Si mandrel: special argon-based plasma treatment and hydrogen annealing. The hydrogen annealing effect was found related to the capping layer, different from previously published paper. Finally, we achieved a 20% line width roughness (LWR) improvement of final pattern in a self-aligned quadruple patterning (SaQP) without any side effect.

Formation and Wet Removal of Organic and Titanium-Containing Residues on Patterned TiN/Porous Low-k Structure

The formation of the residues after patterning of a patterned metal hard mask/dielectric stack was characterized using surface-sensitive methods (attenuated total reflection-Fourier transform infrared spectroscopy and angle-resolved X-ray photoelectron spectroscopy) and scanning electron microscopy. The effect of a reducing plasma post-etch treatment (PET), aging, and moisture on the evolution of the residues was investigated. Both polymer-based (CFx) and metal-containing (TiFx) residues were identified on the exposed surface of the stack. Without the PET, the XPS data collected at different take-off angles suggested that the metal-containing residues were covered by a thin layer of polymer-based residues. The metal-containing residues were found to continue to evolve as a function of aging time if the layer of polymer-based residues was removed by the PET, making the metal hard mask in direct contact with cleanroom air. Exposing the MHM/dielectric stack to a 100% humidity environment did not induce further growing of the TiFx residues. Despite the PET only had limited removal of the TiFx-based residues, it was efficient in removing the polymer-based CFx residues, which in turn led to a better cleaning efficiency after the subsequent wet clean. The results in this study also confirmed that diluted HF dissolved TiFx-type residues and had no CFx removal capability. Although only two chemicals are shown as examples for post-etch residue removal, the type of test structure and methodology shown in this study can be applied for investigation and optimization of any other chemical mixture candidates for cleaning purpose.

Influence of post-etch cleaning and silane heat treatment on resin bond strength to silica-based leucite: an in vitro study

Adhesive cementation of bonded all-ceramic restorations is critical for their long-term clinical performance. The objective of this study was to evaluate the role of post-etch cleaning (PEC) and silane heat treatment on the micro-tensile bond strength of silica-based leucite (SBLE) ceramic when bonded to composite resin. Twenty-four blocks of SBLE ceramic (HeraCeram Press®, Heraeus Kulzer GmbH Grüner Weg 11 63450 Hanau) were fabricated and bonding surfaces were etched using 9.5% hydrofluoric acid. Six experimental groups were made from the various surface treatment combinations including: PEC (37.5% phosphoric acid for 1 min, rinsed with water for 20 s and ultrasonic bath immersion), silane application and silane heat treatment (100 °C for 5 min). An adhesive resin and a light-cured restorative composite were used to bond the ceramic and composite resin blocks under standard conditions. Three hundred and sixty specimen sticks (8 × 1 mm²) were subjected to micro-tensile testing. The means of the micro-tensile bond strength (μ-TBS) were analysed with ANOVA and Tukey–Kramer multiple comparison test. The specimens tested were assessed for mode of failure using scanning electron microscopy. The highest μ-TBS value (38.25 ± 3.40 MPa) of the specimen was achieved by PEC and heated silane. PEC and silane application showed statistically significant improvements in the μ-TBS (p < 0.01). The mean maximum difference was due to PEC (18.91 ± 3.70 MPa). In the surface treatment of SBLE ceramics, PEC had the most significant factor which affected the μ-TBS of resin composite.

Dummy Poly Gate Removal Process Optimization with Pulsing Plasma Application

The technology of High-K/metal gate has led to the continuity of device scaling and enabled the extension of Moore’s Law towards 28 nm node and beyond. The gate last approach has been widely adopted since it can better control n/p-MOS transistor threshold voltage (Vt), hence yielding better electrical performance [1]. However, it poses the formidable challenges to every process of metal gate formation, especially for the 2nd DPGR (dummy gate removal) process. In order to get the robust device performance, the 2nd-DPGR [2] process needs to fully consider all kinds of tangled aspects such as trench profile, n/p-MOS boundary interface, ILD (Interlayer dielectric) loss, Al damage, trench poly residue, trench corner residue, PID (plasmas induce damage), HK capping layer loss and surface residue. In this work, we will first introduce the various dilemma of the 2nd DPGR with conventional CW (continuous wave) plasma approach, and demonstrate the hybrid pulsing scheme could completely solve the aforementioned issues. Synchronous and source-only pulsing plasma have been introduced in the different etch steps of the 2nd DPGR. Synchronous pulsing scheme is proven to achieve vertical trench profile, clean n/p-MOS boundary, precisely-controlled oxide loss/Al damage. While, source-only pulsing PET (post etch treatment) is effective in terms of HK capping layer loss control without sacrificing the ability of interface treatment. 1.Trench Bottom Profile and n/p-MOS Boundary Perfect trench profile could alleviate the gap-fill difficulty and deliver the more reliable device performance. In the 2nd DPGR process, too much profile pull-back at trench bottom is not acceptable. This necessitates the demand for extremely anisotropic dry etching. Besides, n/p-MOS boundary connects the pull -up area and the pull-down area, highly related to ring oscillation performance. As is well known, the produced etching polymer/by-product inevitably adheres to n/p-MOS boundary during DPGR for the high selectivity of poly-si over oxide is required to avoid the excessive oxide loss. However, such polymer/by-product needs to be fully removed before metal gap-fill. Seemingly, even if CW plasma could leverage the extra either in-situ step or ex-situ step to thin down such polymer/by product layer. However, we found there is a trade-off relationship between trench bottom profile and n/p-MOS boundary. On another side, pulsing plasma paves the way to seek the common process window for the above two targets. In synchronous pulsing plasma, the polymer/by-products could be pumped out easily during the plasma-off time and more positive charges could be neutralized at trench bottom. With the proper frequency and duty cycle, we achieved the vertical trench profile with clean n/p-MOS boundary as shown in Fig 1a and b. 2.ILD Loss, Al Damage and Poly Residue In the 2nd DPGR process, the sufficient hard-mask OE (over-etch) process must be kept to avoid poly-Si residue at trench bottom. However, the excessive OE will induce serious Al damage and more ILD loss. The former could result in Al corrosion; the latter could tend to suffer n/p-MOS bridge risk because of metal residue after CMP (chemical mechanical polishing). Finally, we leveraged the synchronous pulsing scheme to tackle both issues from the point of view of less bombardment. 3.Bottom Corner Residue and PID HBr/O2, the typical silicon etch process, tends to suffer trench bottom corner residue. This could reduce the effective channel length, introduce process variation and worsen Vt mismatch. To solve this issue, we resorted to NF3/H2 gas combination to fully remove trench corner residue. However, the device test randomly shows PID issue. This might be the fact that H atom could easily damage HK oxide and/or its capping layer at higher electron temperature under CW plasma mode. Again, synchronous pulsing plasma can balance both corner residue and PID issue as it can reduce the averaged electron temperature to a very low level and the electron shading effect by neutralizing the electron accumulated at trench bottom. 4.Capping Layer Loss and Its Interface HK capping layer is used to protect HK oxide from direct plasma bombardment. The thickness and surface roughness of capping layer are very critical to the adjustment of gate work function, leakage and reliability control. In this work, we came up with the source-only pulsing PET and have proven that it is capable of rigorously controlling capping layer loss without sacrificing the ability of interface treatment. Acknowledgement This work is partially sponsored by Shanghai Rising-Star Program (B type). [1] P. Lim et al, USP, 7871915 B2 “Method for forming metal gates in a gate last process”, 2011 [2] Jack Huang, et al, SPIE, “Synchronous Pulsing Plasma Utilization in Dummy Poly Gate Removal Process”, 2015 Figure 1

A photoluminescence study of plasma reactive ion etching-induced damage in GaN

GaN films with reactive ion etching (RIE) induced damage were analyzed using photoluminescence (PL). We observed band-edge as well as donor-acceptor peaks with associated phonon replicas, all in agreement with previous studies. While both the control and damaged samples have their band-edge peak location change with temperature following the Varshni formula, its intensity however decreases with damage while the D—A peak increases considerably. Nitrogen post-etch plasma was shown to improve the band edge peak and decrease the D—A peak. This suggests that the N2 plasma has helped reduce the number of trapped carriers that were participating in the D—A transition and made the D°X transition more active, which reaffirms the N2 post-etch plasma treatment as a good technique to heal the GaN surface, most likely by filling the nitrogen vacancies previously created by etch damage.

Cryoetching of Silicon and Advanced Materials for 3D Interconnects

Deep silicon etching is currently used for fabrication of many microelectronic components, especially in power microelectronics and in MEMS technology. This etching technology is also needed for Through Silicon Vias (TSV) in 3D integration of microelectronic components in order to enhance the device performance by ‘More than Moore’.Several different processes are commonly exploited for deep silicon etching. One of the techniques is the so-called cryogenic process, which requires the substrate to be cooled down to a temperature of the order of -100°C. Since its introduction by a Japanese team in the end of the eighties, the cryoetching process has been studied by different groups and has been used to etch silicon in a wide range of dimensions from several dozens of nanometer to hundreds of micron-wide structures. The typical cryoetching process relies on plasma which is composed of SF6 and O2. In the plasma, an SiOxFy passivation layer is generated on the vertical sidewalls of the etched features. One of the great advantages in cryoetching process is that any specific post etch treatments are not required because a passivation layer evaporates at ambient temperature. Hence, the surface of micro- or nanostructures fabricated by cryoetching are clean. The most critical point of cryogenic etching is the control of the passivation layer which determines the etching profile. However, it is very difficult to characterize this passivation because of its unique nature, as mentioned above. Consequently, the passivation layer characterization has to be carried out in-situ at a cryogenic temperature.In this paper, we will detail in-situ experiments including mass spectrometry, ellipsometry, double cavity tests and XPS, which were performed in order to investigate physical and chemical mechanisms involved in the silicon cryoetching process. We will also show that etch by-products (SiF4) can participate in the passivation layer formation and reinforce it. Cyclic processes are desired in order to enhance the robustness of the cryoetching process. Among them, the so-called STiGer process consists in alternating SiF4/O2 deposition regime and SF6 etching regime. This particular process greatly enhances process reproducibility. In addition to deep silicon, cryoetching was applied to interconnects in back-end-of-the-line part of advanced CMOS technology, focusing on the etch of organosilicate (OSG) low-k materials with different porosities. The objective is to minimize the plasma induced carbon depletion. We defined an equivalent damaged layer (EDL) by ellipsometry and FTIR experiments, and measured the change of dielectric constant. Etching experiments were performed on patterned and blanket wafers. In porous low-k materials, pores can be filled with the introduced chemicals and/or etch by-products so that plasma-induced damage is significantly reduced. Although the passivation layer evaporates at ambient temperature, condensate by-products (carboxylic acids) remain stable up to room temperature. However, this condensate can be removed easily by high-temperature annealing without additional damage to the low-k materials.

Effective Defect Control in TiN Metal Hard Mask Cu/Low-k Dual Damascene Process

Metallic hard masks (MHM) are routinely employed in Cu/low k dual damascene (DD) etching, but can create defectivity problem. N2 plasma post-etch treatment (N2PET) based on high substrate temperature has been developed to provide effective TiFx residue reduction and MHM defect prevention without low k damage and productivity concerns. Strong gains in surface de-fluorination with substrate temperature and N2PET time was determined. SLIC, XPS, SEM data show 90% reduction of F residue on TiN and no defects on pattern at optimized N2PET. AES and EELS data show that “TiFx” defects are actually TiOx crystals covered by TiFx residue catalyzing the crystal growth. N2PET de-fluorination and defect growth are in focus of this study. An alternative approach in preventing defect growth by surface passivation in CF4/C4F8 etch chemistry was also studied. Both methods, N2PET cleaning and surface passivation, provide effective defect control in TiN MHM Cu/low-k DD etch process.

Recovery of clean ordered (1 1 1) surface of etched silicon

It is generally known that dry etching induces surface damage, but the structure of etched surfaces has not been studied in detail. Nor has it been established how or whether a clean, ordered surface can be recovered after etching damage. Generally, etching damages the surface by introducing structural disorder and impurities to the surface region. Such damage may be so severe that a clean, ordered surface is not recoverable even after heating up to ∼1400K in UHV. We subjected Si (111) surfaces to different reactive ion etching conditions and/or post-etch treatments and examined their effect on the surface. Low temperature STM revealed that a clean, ordered surface as evidenced by the appearance of large area 7×7 reconstructions can be obtained only under certain etching/post-etch recipes. On the other hand, LEED showing 7×7 diffraction spots but with high intensity background and Auger electron spectroscopy (AES) showing no impurity signal cannot be used as evidence that an ordered surface has been obtained.

Review of Plasma-Based Etch Treatment in Dielectric Etch Processes

This work mainly focuses on the post-etch treatment (PET) in dielectric etch processes from contact etch, trench etch to all-in-one etch. PET step is optimized not only to efficiently remove the byproducts formed on the sidewall/bottom of contact/via hole during etch proceses but also to eliminate the surface corrosion of the etched metal comprising feature. Besides, we also leveraged PET to repair low-k damage and prevent the formation of mositure on film surface by modifing film from hydrophilic to hydrophobic, especially for low-k/ultra low-k dielectric processes. Results show the actual effect of PET in terms of reliability performance highly relies on the specific etch recipe, wet clean condition and substrate material in back end of line (BEOL). We also addressed the pre-etch treatment to effectively reduce the impact of photo-resist scumming in contact etch. In brief, plasma-based etch treatment is imperative to extend the tightened process window margin.

Ultra Low-k Damage Control and k Recovery for 28nm RC Improvement

To improve resistance-capacitance delay, porous ultra low-k dielectric materials are used in advanced copper damascene integration. However, the BEOL processes often lead to low-k film damage by removing the hydrophobic groups Si-CH3, and convert partially low-k materials surface from hydrophobic to hydrophilic one. During the wet related processes, the hydrophilic porous low-k film surface is easy to absorb moisture and potentially increase k-value. In this work, we developed the processes that can maintain ultra low-k film k-value either by repairing low-k damage or by removing moistrue. Dry etch plasma process is one of the main steps to result in low-k film damage. Post etch treatment (PET) was optimized to repair porous low-k film surface due to the etch damage. This improved process with less low-k damage can significantly reduced the moisture absorption in the following wet process and improve the capacitance by about 10%. Various thermal treatments post wet and post CMP processes were studied, including temperature, gases and pressures. From our results, post wet clean heat treatment can improve capacitance by about 5% and post CMP heat treatment can improve capacitance by about 10%. To decrease moisture absorption from atmosphere after the wafers were processed thru CMP, queue time from CMP to NDC deposition also was studied and the safe specification was also defined.