Post-deposition Annealing Temperature Research Articles

Insight into gate dielectric reliability and stability of SiO2/GaN MOS devices

Gate dielectric reliability and stability of SiO2/GaN metal–oxide–semiconductor (MOS) capacitors were systematically investigated by means of area-dependent and time-dependent dielectric breakdown (TDDB) characteristics. It was found that, although high-temperature post-deposition annealing (PDA) that causes Ga diffusion in SiO2 gate dielectrics has only a minor impact on electrical properties of the SiO2/GaN interfaces, PDA at temperatures above 800 °C severely degrades dielectric reliability and stability of GaN MOS devices. Area dependences of time-zero and TDDB characteristics revealed the formation of local weak spots and generation of uniform charge trapping sites throughout the gate oxides depending on the PDA temperatures. Determinant factors for dielectric reliability of SiO2/GaN gate stacks and reasonable measures for improving their reliability and stability are discussed on the basis of the experimental findings.

VCC-α nullification and leakage reduction in Pt/Ba0.5Sr0.5TiO3/Pt thin-film capacitor by MgO barrier and PDA for energy storage application

A critical performance parameter of thin-film metal–insulator–metal capacitors when used for energy storage application is leakage current. Introduction of another insulator barrier layer at metal–insulator interface having low electron affinity enhances leakage current performance. The probability of deterioration in capacitance is higher while enhancing leakage performance by barrier layer establishment. The effects of Pt-Ba0.5Sr0.5TiO3 (BST) interface barrier layer and post deposition annealing (PDA) on voltage coefficient of capacitance and leakage current density in Pt/Ba0.5Sr0.5TiO3/Pt thin-film capacitor are reported in this paper. The capacitance measurement is done at low frequency as it meant for energy storage. It is observed that PDA of Pt/MgO/Ba0.5Sr0.5TiO3/MgO/Pt thin-film capacitor at 700 0C in O2 gas environment for 30 min nullifies quadratic voltage coefficient of capacitance (VCC-α). The VCC-α obtained for as-deposited capacitor is −34408 ppm V−2 while that of capacitor annealed at 700 0C is 4.88 ppm V−2 which is the least VCC-α ever reported. A gradual leakage current performance enhancement is observed while increasing annealing temperature and a very low leakage current density of 48 nA cm−2 is observed when annealed at 700 0C. The diffraction peaks in XRD pattern of capacitor annealed at 700 0C indicate good crystallinity achieved in Pt, Ba0.5Sr0.5TiO3 and MgO layers due to high-temperature PDA process. This substantiates the best leakage current characteristics in Pt/MgO/Ba0.5Sr0.5TiO3/MgO/Pt thin-film capacitor annealed at 700 0C than as-deposited capacitor and capacitor annealed at lower temperatures. Further we observed an energy band gap enhancement of 0.055 eV in every 100 0C rise in temperature from the UV–Vis NIR spectroscopy. This continuous energy band gap enhancement while increasing annealing temperature also justifies the reduction in leakage current density at high PDA temperature.

Impact and origin of the oxide-interface traps in Al/Yb2O3/n-Si/Al on the electrical characteristics

This study presents comprehensive results on the changes of the crystal properties, surface morphology, chemical composition and bonding structures based on X-ray photoelectron spectroscopy (XPS) at different depths of the Yb2O3/Si as depending on post-deposition annealing (PDA) temperature. It also includes a detailed examination of the structural properties and the electrical characteristics of the Yb2O3 MOS capacitors. 125 nm-thick Yb2O3 thin films were deposited on n-Si by RF magnetron sputtering system and the Yb2O3/Si structures were annealed at 200 °C, 400 °C, 600 °C, 800 °C under nitrogen ambient. The largest grain size was obtained to be 17.3 nm from the sample annealed at 400 °C. The lowest roughness root-mean-square (Rq) value was measured as 0.464 nm in the Yb2O3 film annealed at 200 °C. Yb 4 d and O 1s spectra shifted to higher binding energies at Yb2O3/Si interface due to the approaching Si with high electronegativity. The peaks assigned to 2+ oxidation states were observed intensely at 400 °C and above due to the conversion of Yb3+→Yb2+. The intensity of the bonded oxygen species in O 1s spectra measured at surface decreased with increasing annealing temperature, which may cause decreasing in the dielectric constant value. The Yb–O bond was mostly observed within the film, while Si-rich (positively charged interface traps) or Yb-rich (negatively charged interface traps) silicate layers (Yb-Si-O) were formed at the interface depending on the PDA temperature. It has been determined that the thickness of the silicate-like layer increases with PDA temperature, resulting in decreasing dielectric constant. The interface state density (Nit) decreased with decreasing concentrations of Yb–Yb, Yb–Si and Si–Si at the interface. It was found that the presence of the Yb3+/Yb2+ ions within the film cause of negative oxide charge trapping and they were more active in the electric characteristics that the interface states. Whether the donor-like and acceptor-line interface states are active depending on the frequency makes it difficult to establish a link between the structural analyses and the electrical characteristics in some cases. The barrier height (φb), dopant concentration (Nd), Fermi energy level (EF) were determined depending on frequency.

Investigation of the Influences of Post-Thermal Annealing on Physical Properties of TiO2 Thin Films Deposited by RF Sputtering

For this study, titanium dioxide (TiO2) thin films were deposited on glass substrates at room temperature by the RF magnetron sputtering technique. The preparation parameters that offer better control and reproducibility of film fabrication were first optimized. Then, the effects of post-deposition annealing temperature at 350, 450, and 550°C on the microstructure, surface morphology, and optical properties of the prepared films were investigated using X-ray diffraction (XRD), Raman spectroscopy (RS), scanning electron microscopy (SEM), atomic force microscopy (AFM), and UV–Visible (UV–Vis) spectrophotometry. Interestingly, XRD analysis shows that as-deposited and annealed TiO2 film possess anatase crystal structure only with a preferential orientation along the (101) plane. The intensity of the (101) diffraction peak and crystallite size are found to increase with increasing annealing temperature, which indicates an improvement in the crystallinity of the films. Raman spectra confirm that all samples possess anatase phase and the crystallinity is enhanced with increasing thermal annealing. From the analysis of SEM and AFM images, it is revealed that the heat treatment significantly affects the morphology, grain size, and surface roughness of the TiO2 films. The UV–Vis spectroscopy analysis shows that as-deposited TiO2 thin film is highly transparent in the visible region with an average transmittance about 84%, whereas the transmission decreases slightly with an increase in annealing temperature. Moreover, the optical band gap energy shows a red shift with increasing the annealing temperature.

Effects of damages induced by indium-tin-oxide reactive plasma deposition on minority carrier lifetime in silicon crystal

A reactive-plasma deposition (RPD) process damage is evaluated for an indium-tin-oxide (ITO)/SiO2/Si structure in terms of the recombination properties at the interface. To calculate the surface recombination velocity (SRV), the defect density at the SiO2/Si interface (Dit), the effective total charge (Qtot) which is the sum of the charges in the SiO2 and the trapped charge at the SiO2/Si interface, and the workfunction of ITO at the ITO/SiO2 interface (ϕITO), are extracted by capacitance-voltage (C-V) analysis as a function of a postdeposition annealing (PDA) temperature. The Dit and Qtot significantly increase by the RPD process to 1.4×1012 cm-2eV-1 and 1.5×1012/q cm-2, respectively, and decrease by the PDA at 200 °C in N2 ambient to 1.4×1011 cm-2eV-1 and 1.1×1011/q cm-2, respectively. The ϕITO also varies from 4.80 eV to 4.35 eV by the PDA. The correlation is examined between the SRV values calculated based on the extended SRH model using the extracted Dit, Qtot, and ϕITO values [SRV(CV)], and the SRV ones obtained from the minority carrier lifetime measurements [SRV(LT)]. It is found that multiple sets of capture cross-sections were required for SRV(CV) values to coincide with SRV(LT) ones. The effect of variation in the Qtot and ϕITO on the band bending is almost canceled out in the present PDA condition. It is thus considered that the increase in Dit is the main cause to decrease the minority carrier lifetime.

Study on the Effects of Post-Deposition Annealing on SiO2/β-Ga2O3 MOS Characteristics

MOSFETs on β-Ga2O3 is a new candidate of high-efficient and cost-effective alternative option for high-voltage power devices. In various studies, ALD-deposited Al2O3 films have been often employed as the gate dielectrics, however, it would be reasonable to replace with SiO2 if one considers the conduction-band offset against β-Ga2O3, which is limited to 1.5−1.6 eV [1] for Al2O3 but can be beyond 2 eV for the case of SiO2. In this study we investigated the effects of post-deposition-annealing (PDA) on the characteristics of SiO2/β-Ga2O3 MOS interface, especially focusing of the impact of the annealing temperature and ambient. β-Ga2O3 (001) wafers with ~2×1016 cm-3 n-type doped epitaxial layers were cleaned in diluted HF solution. Then SiO2 films were deposited by electron-beam evaporation of Si in O2 ambient of ~1×10-2 Pa, followed by PDA in 1 atm-O2 at various temperatures from 600 to 1000℃. Au was evaporated as gate electrode to form MOS capacitors. For some samples an additional annealing at 400℃ was conducted in various ambient (O2, N2, and diluted H2). Nearly-ideal C-V characteristics with negligible hysteresis were obtained for the MOS capacitor fabricated with O2-PDA at 1000℃. The suppressed frequency dispersion indicates a successful formation of MOS interface with low interface defect densty. The energy profiles of interface state density (Dit) were determined by conductance method for the samples with different PDA conditions. Lower Dit was achieved for higher PDA temperatures, down to ~1010 cm-3 at the energy level of EC−0.2 eV. These values are significantly lower than typically reported ones so far on β-Ga2O3 [2, 3]. When we see the hysteresis width (ΔVhys) of C-V curves, defined by the difference between the voltages to observe the flatband-capacitance, the smaller ΔVhys was observed for the samples annealed at higher temperatures. The additional annealing at low temperature at 400℃ works for further reduction of ΔVhys to less than 1 mV/nm, irrespective of the annealing ambient, O2, N2, or diluted H2. After such low-temperature annealing at 400℃, I-V characteristics clarifed that these stacks resulted in the dielectric breakdown fields around 7−8 MV/cm, even though the process has not been optimized for the suppression of the leakage current. Next the flatband voltage (VFB) shift was compared for the samples annealed in different conditions. As we expected, O2-PDA resulted in VFB close to the ideal value estimated from the physical properties of Au and Ga2O3, probably because the fixed charge density at the interface would be minimized. However, PDA in N2 at 1000℃ resulted in a negative shift of VFB, which shows the introduction of positive fixed charges in the stack. The additional annealing in diluted H2 at 400℃ was also induced a negative VFB shift, whereas such additional annealing at the same temperature in O2 or N2 does not cause a significant shift. From these results it was suggested that oxygen deficiency introduction near the interface will induce positive fixed charges. Acknowledgement: This work was partly done in collaboration with JST, Center for Low Carbon Society Strategy.

Electron-spin-resonance studies of AlGaN/GaN MIS-HEMT structures with Al2O3 fabricated by atomic layer deposition

We performed electron-spin-resonance (ESR) investigations of defects related to dangling bonds (DBs) around the insulator/semiconductor interface in Al2O3/AlGaN/GaN MIS-HEMT structures on Si. The Al2O3 layer was fabricated by atomic layer deposition, and we studied the effects of the Al2O3 layer thickness and the post-deposition annealing (PDA) temperature on the number of DBs (Ndb). The Ndb of the AlGaN/GaN HEMT structure was reduced by deposition of the 10-nm-thick Al2O3 layer. The Ndb value at the 5-nm-thick Al2O3/AlGaN interface decreased to a minimum value with PDA at 500 °C. We show that defects related to DBs around ALD-Al2O3/AlGaN interfaces can be reduced by optimizing the ALD-Al2O3 thickness and PDA temperature.

Comparative study of photoluminescence properties obtained from SiO2/GaN and Al2O3/GaN structures

Photoluminescence properties of SiO2/GaN and Al2O3/GaN structures formed with plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) methods were systematically investigated. Intensities related to the band edge (BE) transition for the ALD-SiO2/GaN and ALD-Al2O3/GaN structures significantly decrease compared with the intensity for the GaN surface after a wet-chemical cleaning. The BE intensities have dependences on the temperature of post-deposition annealing (PDA), while they do not achieve the intensity for the wet-cleaned sample even after high-temperature PDA. On the other hand, we found that the BE intensity for the PECVD-SiO2/GaN structure showed almost no reduction compared with the wet-cleaned sample. These results suggest that the interface between PECVD-SiO2 and GaN is well passivated, and that the PECVD-SiO2/GaN structure is suitable for future electrical and optical GaN devices.

Effects of Post-Deposition Annealing Temperatures on the Composition of Interfacial Layer at Germanium (Ge)/Aluminium Oxide (Al2O3)

The understanding of chemical bonding structure of high k dielectrics/Germanium (Ge) interface is upmost importance in order to form a good quality dielectric/Ge interface in fabricating Ge metal oxide semiconductor field effect transistor (MOSFETs). In addition, there is still no detail explanation on the interfacial growth of dielectrics/Ge under the influenced of different temperature of post deposition anneal. In current work, the effects of post deposition anneal (PDA) temperature between 400°C and 600°C on the chemical composition of interfacial layer between Ge and Al2O3 were examined by X-ray photoelectron spectroscopy (XPS). Investigation on thermal stability and structural characteristics for gate structure of Al2O3 dielectric grown on Ge by RF sputtering was done by analyzing X-ray photoelectron spectroscopy (XPS) spectra. It is observed that the oxygen deficient region in interfacial layer (IL) is enhanced rather than fully oxidized Al2O3 with increased PDA temperatures. These undesired phenomena caused shrinkage of IL at Ge/Al2O3 interface at higher temperature of 600°C.

Photoluminescence of silicon carbonitride thin films: The interdependence of post-deposition annealing and growth temperature

Silicon carbonitride (SiCN) thin films have recently emerged as the promising class of multifunctional materials because of their unique properties inherited from binary submatrices of silicon carbide, silicon nitride, and carbonitride. The luminescence mechanism of such ternary materials is complex and is influenced by slight changes in the film composition, deposition temperature, and post-deposition annealing temperature. This paper reports the temperature dependence of luminescent centres in SiCN thin films grown using the electron cyclotron plasma enhanced chemical vapour deposition (ECR PECVD) at different deposition temperatures, which are subsequently subjected to a wide range of annealing temperatures. With the increase of the deposition temperature, the photoluminescence (PL) sub-band positioned at around 1.8 eV (650 nm) intensifies. Following the annealing, the changes of the PL spectra at higher annealing temperatures are dominated by the emission related to this PL sub-band. The white luminescence of SiCN thin films observed under excitation by a 325 nm laser is explained in terms of the radiative defects at localized carbide- and nitride-related states. We assign the changes of the intensity and shape of the PL-sub bands mainly to the evolution of carbon-related defects. The observed variation of the PL emission of different samples was linked with the film restructuring and original growth temperature. We discuss how the post-deposition thermal annealing influences the emissions associated with the carbon and nitride states differently in the samples grown at different deposition temperatures, which have different compositions.

Influence of post-deposition annealing on characteristics of Pt/Al2O3/β-Ga2O3 MOS capacitors

We investigated the influence of post-deposition annealing (PDA) temperature on the characteristics of Pt/Al2O3/n-β-Ga2O3 MOS capacitors. Electrical properties such as the flatband voltage (Vfb) shift, Vfb hysteresis, fixed charge (QIL), interface state density (Dit) and leakage current could be divided into two groups such as a low PDA temperature range below 600 °C and a high temperature range above 700 °C. The capacitors with a low PDA temperature exhibited superior electrical properties compared to the capacitors with a high PDA temperature, excluding leakage current property. We found that 700 °C is a critical PDA temperature because Al2O3 film starts to crystallize and solid-solution reaction of Al2O3 gate insulator and β-Ga2O3 substrate also occurs, resulting in Ga diffusion into the Al2O3 film and large roughness at Al2O3/β-Ga2O3 interface. These lead to a large Dit and positive Vfb shift at 700 °C. Even in a low PDA temperature range, it is clear that capacitor at 300 °C exhibited superior electrical properties of Vfb shift of −0.23 V, QIL of 4.1 × 1011 cm−2, and Dit (1.6 × 1012 eV−1 cm−2 at Ec-E = 0.4 eV). Based on these experimental data, lower PDA temperature of 300 °C is suitable.

Inkjet‐Printed and Deep‐UV‐Annealed YAlOx Dielectrics for High‐Performance IGZO Thin‐Film Transistors on Flexible Substrates

AbstractRecent developments in inkjet printing have proven it a viable method for low‐cost and large‐area coating of oxide materials. The main drawback of this method is the common requirement of a post‐deposition annealing (PDA) of the printed layers at relatively high temperatures (T > 200 °C). This sets a requirement for the substrate to have high glass transition temperature (Tg). To reduce the PDA temperature, deep‐ultraviolet (DUV) annealing is proposed as an effective method. In this study, yttrium aluminum oxide (YAlOx) dielectrics are realized for application in flexible electronic devices via inkjet printing and DUV annealing at a temperature of 150 °C. The effect of the Y concentration on the electrical properties of the dielectrics is investigated. An increase in the Y incorporation is found to increase the dielectric constant and decrease the leakage current of the dielectrics. Flexible indium gallium zinc oxide (IGZO) thin‐film transistors with 50 µm channel widths and 7 µm channel lengths employing printed YAlOx dielectrics are fabricated on polyimide substrates with a maximum processing temperature of 150 °C, yielding a maximum gate leakage current of 10−13A, a high ION/IOFF ratio of 108, and a field effect mobility of 4.3 cm2 V−1 s−1.

P-type SnO thin films prepared by reactive sputtering at high deposition rates

SnO is an ideally suitable p-type conductive material, with large hole mobility, and has attracted great interest in connection with next-generation electronic applications. In the present work, tin oxide (SnOx) thin films were deposited on unheated soda lime glass substrates by reactive DC sputtering from a pure Sn target. The structural, optical and electrical properties of the films were analysed as a function of the oxygen partial pressure in the sputtering atmosphere and of the post-deposition annealing temperature in air. A structural analysis was carried out using Raman spectroscopy and X-ray diffraction. Optical and electrical characterizations were performed using photo-spectrometry and Hall effect measurements, respectively. The films grown at room temperature and low oxygen pressures reached high deposition rates of above 45 nm/min, showing poorly crystalline SnO and low transparency. Subsequent heating to 350 °C allowed to achieve a more crystalline tetragonal SnO with an average visible transmittance of 65%, a p-type conductivity of 0.8 S/cm, and a hole mobility of 3.5 cm2/(V s).

High Temperature Annealing of ZnO:Al on Passivating POLO Junctions: Impact on Transparency, Conductivity, Junction Passivation, and Interface Stability

We investigate the enhancement in transparency and conductivity of aluminum doped zinc oxide (ZnO:Al) layers upon high-temperature annealing and its impact on contact resistance, as well as, on passivation properties of carrier selective junctions based on doped polycrystalline Si on a passivating silicon oxide (POLO). The temperature stability of these junctions allows annealing of the ZnO:Al/POLO combination up to 600 °C. We prepare ZnO:Al films by dc magnetron sputtering at room temperature. We determine the complex refractive index of ZnO:Al in dependence of post-deposition annealing (PDA) temperature by spectroscopic ellipsometry. High-temperature annealing improves the conductivity and reduces the absorption within ZnO:Al. The optical losses in a ZnO:Al/POLO stack are rather limited by the poly-Si layer than by the ZnO:Al. The sheet resistance improves from roughly 20 000 Ω/sq for 80 nm thick as-deposited ZnO:Al films to 72 Ω/sq after fast firing at 600 °C. At the same time, PDA cures the damage induced in the POLO junctions during ZnO:Al deposition. After PDA with AlxOy capping layers, the passivation quality even surpasses the initial level. A transmission electron microscopy analysis of the interface between the ZnO:Al and the underlying poly-Si reveals the formation of a silicon oxide like interfacial layer after PDA at 400 °C. This interfacial layer causes a high contact resistivity of the metal/ZnO:Al/POLO-junction and could limit the thermal budget for cell processing. Our results indicate that after successful process adjustment, ZnO:Al could substitute In-based transparent conductive oxides on POLO cells for cost reasons, as well as, enable a high efficiency potential.

Growth of epitaxial CdTe thin films on amorphous substrates using single crystal graphene buffer

Traditionally, a high-quality CdTe film can only be grown on a single crystal substrate with a small lattice mismatch. Herein, we report the epitaxy of CdTe films on monolayer single crystal graphene buffered amorphous SiO2/Si(100) substrates, despite a 86% lattice mismatch between CdTe(111) and graphene. X-ray pole figure, electron backscatter diffraction mapping and transmission electron microscopy all confirm that the epitaxial CdTe films are composed of two domains: the primary and the Σ3 twin. The crystal quality of films is shown to improve as the post-deposition annealing temperature increases. However, the rotational misalignment in CdTe remains large even after annealing. Through density functional theory calculations on the charge transfer distribution at the interface of CdTe and graphene, it is found that the interface is dominated by the weak van der Waals interaction, which explains the large spread of in-plane orientation in CdTe films. Furthermore, the rotational misalignment in graphene itself is also confirmed to produce the large in-plane orientation spread in CdTe films. Although imperfect in epitaxy quality, this work demonstrates that monolayer single crystal graphene can buffer amorphous substrates for growing epitaxial films, and hence hints an opportunity for developing advanced thin film devices using graphene as a template.

Effect of deposition rate and heat treatment on microstructural, morphological, optical properties and ultra-fast laser-induced damage threshold of Al2O3-ZrO2 pure and mixed thin films prepared by electron beam evaporation

Electron beam evaporation method was used to synthesize alumina, zirconia, and alumina-zirconia mixed thin films on the fused silica substrate. Rutherford backscattering spectroscopy was carried on to determine the stoichiometry and composition ratio of the prepared mixed thin films. Ultraviolet-visible-near infrared spectrophotometry was performed to measure the transmittance spectra of the deposited thin films. Yoldas expression was developed to calculate the porosity of mixed thin films. The approach for the modification of refractive index, extinction coefficient, porosity, and band-gap energy of fabricated thin films by the adjustment of the deposition rate and post-deposition annealing temperature was indicated. The growth of voids, pinholes, and separation between neighboring columns at higher annealing temperature is evident in the images of scanning electron microscopy. The results of X-ray diffractometry reveal the short-range order and amorphous nature of prepared alumina-zirconia mixed thin films. The optimized deposition conditions, for the improvement of the femtosecond laser-induced damage threshold of synthesized thin films were introduced.

Electrical properties of Pb[Zr0.35Ti0.65]O3 on PEALD Al2O3 for NVM applications

PurposeDevelopment of (1T-type) ferroelectric random access memory (FeRAM) has most actively progressed since 1995 and motivated by the physical limits and technological drawbacks of the flash memory. 1T-type FeRAM implements ferroelectric layer at the field effect transistor (FET) gate. During the course of the investigation, it was very difficult to form a thermodynamically stable ferroelectric-semiconductor interface at the FET gate, leading to the introduction of one insulating buffer layer between the ferroelectric and the silicon substrate to overcome this problem. In this study, Al2O3 a high-k buffer layer deposited by plasma enhanced atomic layer deposition (PEALD) is sandwiched between the ferroelectric layer and silicon substrate.Design/methodology/approachFerroelectric/high-k gate stack were fabricated on the silicon substrate and pt electrode. Structural characteristics of the ferroelectric (PZT) and high-k (Al2O3) thin film deposited by RF sputtering and PEALD, respectively, were optimized and investigated for different process parameters. Metal/PZT/Metal, Metal/PZT/Silicon, Metal/PZT/Al2O3/Silicon structures were fabricated and electrically characterized to obtain the memory window, leakage current, hysteresis, PUND, endurance and breakdown characteristics.FindingsXRD pattern shows the ferroelectric perovskite thin Pb[Zr0.35Ti0.65]O3 film with (101) tetragonal orientation deposited by sputtering and PEALD Al2O3 with (312) orientation showing amorphous nature. Multiple angle analysis shows that the refractive index of PZT varies from 2.248 to 2.569, and PEALD Al2O3 varies from 1.6560 to 1.6957 with post-deposition annealing temperature. Increase in memory window from 2.3 to 8.4 V for the Metal-Ferroelectric-Silicon (MFS) and Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure has been observed at the annealing temperature of 500°C. MFIS structure with 10 nm buffer layer shows excellent endurance of 3 × 109 read-write cycles and the breakdown voltage of 33 V.Originality/valueThis paper shows the feature, principle and improvement in the electrical properties of the fabricated gate stack for 1T-type nonvolatile FeFET. The insulating buffer layer sandwiched between ferroelectric and silicon substrate acts as a barrier to ferroelectric–silicon interdiffusion improves the leakage current, memory window, endurance and breakdown voltage. This is perhaps the first time that the combination of sputtered PZT on the PEALD Al2O3 layer is being reported.

Impact of post-deposition annealing in Cu2SnS3 thin film solar cells prepared by doctor blade method

In this work, post-deposition annealing is done at three different temperatures on Cu2SnS3 (CTS) thin film solar cells prepared by doctor blade technique. Structural and electrical characteristics are determined from scanning electron microscopy (SEM), energy-dispersive X-ray fluorescence spectroscopy (ED-XRF), X-ray diffraction (XRD), Hall Effect and I-V characteristics studies to enlighten the mechanisms by which solar cells performance varies. The highest efficiency gain is obtained 1.14%. It is concluded that the optimum post-deposition annealing temperature for CTS is 400 °C for 30 min in the sulfur atmosphere.

Sol-gel deposition and characterization of vanadium pentoxide thin films with high TCR

Vanadium pentoxide thin films have been deposited on quartz substrates via sol-gel synthesis and dip coating. The process was developed to establish a reliable and inexpensive method to produce thin films with a high temperature coefficient of resistance (TCR) for sensing applications. Sol-gel precursor concentration and post-deposition annealing conditions were varied to address their effects on film composition, morphology, structure, resistivity, and TCR response. The resulting thin films were structurally characterized by thin film profilometry, x-ray diffraction, scanning electron microscopy, and Raman spectroscopy. Resistivity and TCR measurements were carried out to determine their efficacy as sensor materials. Both low and high concentration alkoxide sol-gel precursors led to films of pure α-V2O5 composition but with characteristically different structural and electrical properties. Low concentration films showed a modest decrease in resistivity and TCR with increasing annealing temperature, consistent with the formation of increasing grain size and the coalescence of largely planar grains with common crystalline orientation. In contrast, films fabricated from higher alkoxide precursor concentration are characterized by a higher density of grains with a larger dispersion in orientation and better-developed grain boundaries, leading to a general increase in resistivity and TCR with annealing temperature. The TCR of the films lied in the range of -3%°C−1 to -4%°C−1, comparing favorably with films produced through conventional techniques such as DC magnetron sputtering, chemical vapor deposition, or pulsed laser deposition. Further, their TCR and resistivity characteristics can be controlled through sol-gel precursor concentration and post-deposition annealing temperature, indicating that sol-gel deposited vanadium pentoxide films are promising candidates for infrared sensor applications.

Room temperature pulsed-DC sputtering deposition process for CIGS absorber layer: Material and device characterizations

A pulsed-DC sputtering process at room temperature has been developed for the deposition of the CIGS absorber layer. It uses a single quaternary target and is followed by a high temperature post-deposition annealing process. It has to be particularly noticed that no additional selenium supply was used. The annealed layers have shown a high microstructural quality: micrometric grain size, highly oriented (112) chalcopyrite phase, no phase decomposition and no Cu2-xSe secondary phase at the surface. The use of such an absorber layer for the fabrication of 0.5 cm2 solar cells has allowed reaching a conversion efficiency of 11.8% with an open circuit voltage of 558 mV, a short circuit current density of 32.1 mA·cm−2 and a fill factor of 65.8%.