Post-deposition Annealing Temperature Research Articles

Fabrication and Characteristics of Nano-Floating Gate Memories with ZnO Nano-Crystals as Charge-Storage Layer**Supported by the National Natural Science Foundation of China under Grant No 61404055.

Nano-floating gate memory devices with ZnO nano-crystals as charge storage layers are fabricated, and the influence of post-deposition annealing temperature and thickness of the ZnO layer are investigated. Atomic force microscopy and scanning electron microscopy reveal the morphology of discrete ZnO nano-crystals. For capacitance-voltage measurements, it is found that the memory device with 1.5 nm ZnO and annealed at 700°C shows a larger memory window of 4.3 V (at ±6 V) and better retention characteristics than memory devices with 2.5 nm ZnO or annealed at other temperatures. These results indicate that the nano-floating gate memory with ZnO nano-crystals can obtain good trade-off memory properties.

Energy band structure and electrical properties of Ga-oxide/GaN interface formed by remote oxygen plasma

The energy band structure of a Ga-oxide/GaN structure formed by remote oxygen plasma exposure and the electrical interface properties of the GaN metal–oxide–semiconductor (MOS) capacitors with the SiO2/Ga-oxide/GaN structures with postdeposition annealing (PDA) at various temperatures have been investigated. Reflection high-energy electron diffraction and X-ray photoelectron spectroscopy clarified that the formed Ga-oxide layer is neither a single nor polycrystalline phase with high crystallinity. We found that the energy band offsets at the conduction band minimum and at the valence band maximum between the Ga-oxide layer and the GaN surface were 0.4 and 1.2 ± 0.2 eV, respectively. Furthermore, capacitance–voltage (C–V) characteristics revealed that the interface trap density (Dit) is lower than the evaluation limit of Terman method without depending on the PDA temperatures, and that the SiO2/Ga-oxide stack can work as a protection layer to maintain the low Dit, avoiding the significant decomposition of GaN at the high PDA temperature of 800 °C.

Annealing behavior of open spaces in AlON films studied by monoenergetic positron beams

The impact of nitridation on open spaces in thin AlONx films deposited by a reactive sputtering technique was studied by using monoenergetic positron beams. For AlONx films with x = 0%–15%, positrons were found to annihilate from trapped states in open spaces, which coexist intrinsically in an amorphous structure with three different sizes. Nitrogen incorporation into the Al2O3 film increased the size of the open spaces, and their density increased as the post-deposition annealing temperature increased. The effect of nitrogen incorporation, however, diminished at x = 25%. The observed change in the network structure was associated with the formation of a stable amorphous structure, which we could relate to the electrical properties of AlONx/SiO2/Si gate stacks.

Densification of silicon dioxide formed by plasma-enhanced atomic layer deposition on 4H-silicon carbide using argon post-deposition annealing

Post-deposition annealing (PDA) was used to improve gate oxide physical and electrical properties. Deposition was accomplished by plasma-enhanced atomic layer deposition (PEALD). We investigated the densification silicon dioxide (SiO2) formed by PEALD on 4H-silicon carbide (SiC) using PDA without oxidation and nitridation. PDA was conducted at 400–1200 °C in argon (Ar) ambient. The thickness of the SiO2 was reduced by up to 13.5% after Ar PDA at 1000 °C. As the temperature of the Ar PDA increased, the etching rate of SiO2 decreased. At temperatures greater than 1000 °C, the SiO2 etching rate was low compared with that of thermal SiO2. After PDA, the SiO2/4H-SiC interface was smoother than that of thermal SiO2/4H-SiC. The current density versus oxide field and capacitance versus voltage of the SiO2/4H-SiC metal oxide semiconductor (MOS) capacitors were measured. Sufficient densification of SiO2 formed by PEALD on 4H-SiC was obtained using Ar PDA at 1200 °C.

Impact of sublayer thickness and annealing on silicon nanostructures formation in a-Si:H/a-SiNx:H superlattices for photovoltaics

In this work, we synthesized amorphous multilayered a-Si:H/a-SiNx:H superlattices with different thickness of sublayers grown on silicon and quartz substrates by PECVD method at low power density (60 mW/cm2) and substrate temperature (250 °C) using nitrogen and silane gases as reactive precursors. Subsequently, the post-deposition annealing of these structures, composed of alternating layers of a-Si:H and a-SiNx:H, was carried out up to 1100° in vacuum to form silicon nanostructures. The dependence of the structural and chemical bonding characteristics of prepared superlattices on the silicon sublayer thickness and post-deposition annealing temperature was investigated. The formation of silicon nanostructures was confirmed by transmission electron microscopy, X-ray diffraction measurement and Raman scattering spectroscopy. Changes in bonding configuration during the annealing were carried out by Fourier transform infrared spectroscopy. Optical properties were studied by UV–Vis spectroscopy. XRD, Raman and TEM measurements show that the crystallization process of a-Si:H sublayers strongly depends on the thickness of initial a-Si:H sublayers and the post-deposition treatment process. It was found that a higher crystallization temperature for the thinner a-Si:H sublayers is needed. Results clearly show that structural and optical characteristics of these systems can be controlled by deposition parameters and post-deposition annealing conditions.

Atomic layer deposited HfO2 ultra-thin films on different crystallographic orientation Ge for CMOS applications

The properties of the HfO2 ultra-thin films high-k gate stack deposited on surface passivated (GeON) germanium with three different orientations viz. Ge (100), Ge (110) and Ge (111) for CMOS applications have been studied. The effect of post deposition annealing (PDA) at temperatures 350 °C and 400 °C has been investigated. The high-resolution transmission electron microscopy, X-ray photoelectron spectroscopy and atomic force microscopy were used to study the interfacial, chemical and surface properties of atomic layer deposited-HfO2 ultrathin films, respectively. The high frequency conductance method was applied to evaluate the value of interface trap density (Dit) and the lowest Dit of 6.24 × 1012 cm−2ev−1 was evaluated for (111) orientation annealed at 400 °C than (100) and (110) orientation. The effective barrier height extracted from the Fowler-Nordheim conduction transport is in the range of 0.29–0.70 eV for all samples and shows the significant dependence of the substrate orientations and PDA temperature.

Optimization of MgF2-deposition temperature for far UV Al mirrors.

Progress towards far UV (FUV) coatings with enhanced reflectance is invaluable for future space missions, such as LUVOIR. This research starts with the procedure developed to enhance MgF2-protected Al reflectance through depositing MgF2 on a heated aluminized substrate [Quijada et al., Proc. SPIE 8450, 84502H (2012)] and it establishes the optimum deposition temperature of the MgF2 protective film for Al mirrors with a reflectance as high as ~90% at 121.6 nm. Al films were deposited at room temperature and protected with a MgF2 film deposited at various temperatures ranging from room temperature to 350°C. It has been found that mirror reflectance in the short FUV range continuously increases with MgF2 deposition temperature up to 250°C, whereas reflectance decreases at temperatures of 300°C and up. The short-FUV reflectance of mirrors deposited at 250°C only slightly decreased over time by less than 1%, compared to a larger decay for standard coatings prepared at room temperature. Al mirrors protected with MgF2 deposited at room temperature that were later annealed displayed a similar reflectance enhancement that mirrors protected at high temperatures. MgF2 and Al roughness as well as MgF2 density were analyzed by x-ray grazing incidence reflectometry. A noticeable reduction in both Al and MgF2 roughness, as well as an increase of MgF2 density, were measured for films deposited at high temperatures. On the other hand, it was found a strong correlation between the protective-layer deposition temperature (or post-deposition annealing temperature) and the pinhole open area in Al films, which could be prevented with a somewhat thicker Al film.

Effect of annealing on doping of graphene with molybdenum oxide

We investigated the effect of post-annealing on the doping of graphene with MoO3 in this study. The as-deposited molybdenum oxide thin film prepared using our method was not completely oxidized; in addition, it was in an amorphous state, due to which its doping effect was not significant. As the post-deposition annealing temperature was increased, the oxidation and crystallization of the molybdenum oxide progressed and the doping effect increased accordingly. After annealing at 350 °C, the holes were the most doped and the sheet resistance was the lowest. The doped graphene film obtained in this study shows higher doping effect and stability compared to other dopants.

Investigation of Gate-Stacked In-Ga-Zn-O TFTs with Ga-Zn-O Source/Drain Electrodes by Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition.

Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) was employed for the fabrication of indium gallium zinc oxide thin-film transistors (IGZO TFTs) with high transparent gallium zinc oxide (GZO) source/drain electrodes. The influence of post-deposition annealing (PDA) temperature on GZO source/drain and device performance was studied. Device with a 300 °C annealing demonstrated excellent electrical characteristics with on/off current ratio of 2.13 × 108, saturation mobility of 10 cm2/V-s, and low subthreshold swing of 0.2 V/dec. The gate stacked LaAlO3/ZrO2 of AP-IGZO TFTs with highly transparent and conductive AP-GZO source/drain electrode show excellent gate control ability at a low operating voltage.

Understanding of post deposition annealing and substrate temperature effects on structural and electrical properties of Gd2O3 MOS capacitor

The purpose of this study is to understand the effects of substrate temperature (ST) and post deposition annealing (PDA) on the structural-electrical properties of Gd2O3 film and to evaluate the electrical performances of the MOS based devices formed with this dielectric. The Gd2O3/Si structures were annealed at 500, 600, 700, and 800 °C under N2 ambient after the films were grown on heated p-Si substrate at various temperatures ranged from 20 to 300 °C by RF magnetron sputtering. For any given ST, the crystallization/grain size increased with increasing PDA temperature. The bump in the accumulation region or continuous decrease in the capacitance values of the inversion region of the C–V curves for 800 °C PDA was not observed. The lowest effective oxide charge density (Qeff) value was obtained to be − 1.13 × 1011 cm−2 from the MOS capacitor with Gd2O3, which is grown on heated Si at 300 °C and annealed at 800 °C. The density of the interface states (Dit) was found to be in the range of 0.84 × 1011 to 1.50 × 1011 eV−1 cm−2. The highest dielectric constant (e) and barrier height $$({\Phi _B})$$ values were found to be 14.46 and 3.68, which are obtained for 20 °C ST and 800 °C PDA. The results show that the negative charge trapping in the oxide layer is generally more than that of the positive, but, it is reverse of this situation at the interface. The leakage current density decreased after 20 °C ST, but no significant change was observed for other ST values.

The Effect of Thermal Treatment Induced Performance Improvement for Charge Trapping Memory with Al2O3/(HfO2)0.9(Al2O3)0.1/Al2O3 Multilayer Structure

Charge trapping flash memory devices with the structure of [TiN/W]/Al2O3/(HfO2)0.9(Al2O3)0.1/Al2O3/Si were fabricated, and their memory properties were characterized. High-κ (HfO2)0.9(Al2O3)0.1 composite (named as HfAlO in short) was prepared as the charge trapping layer, and the effect of post deposition annealing (PDA) conditions on its charge trapping characteristics was also investigated. The sample treated by high PDA temperature (1000°C) exhibits larger memory window, faster program/erase (P/E) speed, lower P/E voltage, better data retention and endurance performance, which should be ascribed to the intensive mixing of HfO2 and Al2O3 in the charge trapping layer. Therefore, the proposed memory devices show great potential in future nanoscale memory applications.

Normally-off Al2O3/GaN MOSFET: Role of border traps on the device transport characteristics

Based on the self-terminating gate recess technique, two different processes featuring gate-recess-first (GF) and ohmic-contact-first (OF) were proposed for E-mode Al2O3/GaN MOSFETs. Increased maximum drain current (Idmax) ∼30% (420 vs 325 mA/mm), field-effect mobility (μFEmax) ∼67% (150 vs 90 cm2/Vs) and reduced on-state resistance (Ron) ∼42% (9.7 vs 16.8 Ω·mm) were observed in the devices fabricated by GF process. Such significant performance difference of GF- and OF-devices resulted from the presence of border traps at Al2O3/GaN interface with a time constant ∼7 × 10−6 s. Experimental results indicated that: (1) the near interface border traps in Al2O3 dielectric significantly affect device channel mobility; (2) a high temperature post-deposition annealing process could effective suppress generation of border traps.

Electrical characteristics and interface properties of ALD-HfO2/AlGaN/GaN MIS-HEMTs fabricated with post-deposition annealing

HfO2/AlGaN/GaN metal–insulator–semiconductor (MIS)-type high electron mobility transistors (HEMTs) on Si substrates were fabricated by atomic layer deposition of HfO2 layers and post-deposition annealing (PDA). The current–voltage characteristics of the MIS-HEMTs with as-deposited HfO2 layers showed a low gate leakage current (Ig) despite the relatively low band gap of HfO2, and a dynamic threshold voltage shift (ΔVth) was observed. After PDA above 500 °C, ΔVth was reduced from 2.9 to 0.7 V with an increase in Ig from 2.2 × 10−7 to 4.8 × 10−2 mA mm−1. Effects of the PDA on the HfO2 layer and the HfO2/AlGaN interface were investigated by x-ray photoelectron spectroscopy (XPS) using synchrotron radiation. XPS data showed that oxygen vacancies exist in the as-deposited HfO2 layers and they disappeared with an increase in the PDA temperature. These results indicate that the deep electron traps that cause ΔVth are related to the oxygen vacancies in the HfO2 layers.

Interface chemistry study of InSb/Al2O3 stacks upon in situ post deposition annealing by synchrotron radiation photoemission spectroscopy

The thermal stability of InSb/Al2O3 stacks has been systematically studied upon in situ post deposition annealing (PDA) at 300°C and 400°C. Atomic layer deposition (ALD) of Al2O3 (∼3nm) has been grown on the native oxide and the HCl aqueous solution treated InSb (100) at 200°C. The interface chemistry, elemental diffusion as well as elemental desorption are characterized by synchrotron radiation photoemission spectroscopy (SRPES) with the incident photon energy of 750, 600 and 500eV. A Math model has been proposed to calculate the depth profile for In and Sb oxides based on the analysis from different incident energies. Indium atoms have re-oxidized during ALD process, and indium oxide has been observed to diffuse into the Al2O3 film upon PDA at 300°C for the HCl pretreated sample. Indium oxide has desorbed and diffused upon PDA process for the native oxide sample. Sb oxide has been observed to desorb continuously as PDA temperature increases, for all samples. The surface has been torn up upon PDA at 400°C from the morphology characterization.

Post-deposition annealing effects on the insulator/semiconductor interfaces of Al2O3/AlGaN/GaN structures on Si substrates

The effects of post-deposition annealing (PDA) on Al2O3/AlGaN interfaces fabricated by atomic layer deposition (ALD) are studied by x-ray photoelectron spectroscopy (XPS) using synchrotron radiation. Current–voltage (I–V) measurements of annealed Al2O3/AlGaN/GaN metal–insulator–semiconductor (MIS)-type high electron mobility transistors (HEMTs) on Si substrates are also performed to investigate the effects of PDA. XPS results show that the amount of Al-O bonding in the Al2O3 layer and Ga-O bonding in the AlGaN layer changes considerably at a PDA temperature of 600 °C. The results of the I–V measurements show that the electrical characteristics of the MIS-HEMTs change substantially at a PDA temperature of 700 °C. After PDA at 700 °C, the dynamic threshold voltage shift (ΔVth) was reduced from 5 to 0.5 V with an increase of the gate leakage current (Ig) from 1 × 10−7 to 7 × 10−5 mA mm−1. These results indicate that the deep electron traps, such as oxide traps near the Al2O3/AlGaN interfaces, almost disappear at approximately 700 °C with the crystallization of the Al2O3 layers.

Characterization of Sputter-Deposited LiCoO2 Thin Film Grown on NASICON-type Electrolyte for Application in All-Solid-State Rechargeable Lithium Battery.

All-solid-state Li-rechargeable batteries using a 500 nm-thick LiCoO2 (LCO) film deposited on two NASICON-type solid electrolyte substrates, LICGC (OHARA Inc.) and Li1.3Al0.3Ti1.7(PO4)3 (LATP), are constructed. The postdeposition annealing temperature prior to the cell assembly is critical to produce a stable sharp LCO/electrolyte interface and to develop a strong crystallographic texture in the LCO film, conducive to migration of Li ions. Although the cells deliver a limited discharge capacity, the cells cycled stably for 50 cycles. The analysis of the LCO/electrolyte interfaces after cycling demonstrates that the sharp interface, once formed by proper thermal annealing, will remain stable without any evidence for contamination and with minimal intermixing of the constituent elements during cycling. Hence, although ionic conductivity of the NASICON-type solid electrolyte is lower than that of the sulfide electrolytes, the NACSICON-type electrolytes will maintain a stable interface in contact with a LCO cathode, which should be beneficial to improving the capacity retention as well as the rate capability of the all-solid state cell.

Post-deposition-annealing effect on current conduction in Al2O3 films formed by atomic layer deposition with H2O oxidant

Atomic-layer-deposition (ALD) Al2O3 films are promising as gate insulators of non-Si semiconductor devices. Although they allow relatively small leakage currents just after deposition, ALD Al2O3 films formed at low temperatures are subject to high temperature during fabrication or operation of devices. Therefore, the effect of post-deposition annealing (PDA) on the properties of Al2O3 films is investigated in this study. ALD Al2O3 films formed using H2O oxidant at low temperatures are compacted by PDA, but their mass density and dielectric constant remain approximately unchanged or slightly decrease owing to the desorption of methyl groups contained in the films as impurities. In accordance with these results, the wet etching rate of Al2O3 films is not much reduced by PDA. The conduction current in ALD Al2O3 films formed on Si is reduced by PDA and becomes smaller than that in films formed at the same ALD temperatures as those of PDA. The conduction current for PDA temperatures above 250 °C, however, increases and, accordingly, spoils the merit of low-temperature ALD. Therefore, given that the dielectric constant of annealed films remains low, high-temperature ALD is practically more significant than applying PDA to low-temperature ALD Al2O3 films from the viewpoint of leakage current under the same thermal budget. Space-charge-controlled field emission analysis revealed that, at the aforementioned threshold temperature, PDA abruptly increases the Al2O3/SiO2 interfacial dipoles and simultaneously reduces the amount of the positive charge near the interface. The so-called negative-charge buildup by PDA might be caused by this decrease in the positive charge.

Origin of visible photoluminescence from Si-rich and N-rich silicon nitride films

Si-rich (SiN1.1) and N-rich (SiN1.5) silicon nitride films were grown on the Si wafers by plasma-enhanced chemical vapor deposition. Their composition and structure were investigated by Rutherford backscattering spectroscopy and transmission electron microscopy. The effect of composition and post-deposition annealing temperature on the SiNx light-emitting properties was investigated by the examination of photoluminescence. The intensive bands for the Si-rich and N-rich nitride films were detected in the red and blue spectral ranges, respectively. Photoluminescence bands transformations for the annealed nitride films can be ascribed to the increasing K- and N-centre concentration via the SiH and NH bonds rupture and the competitive processes of defect annihilation. On the basis of photoluminescence band FWHM broadening with “x” increasing, the FWHM dependence on the measurement temperature and SiNx films inhomogeneous structure, the emission from the SiN1.1 and SiN1.5 films is attributed to the transitions between the bands of defect and tail states associated with chemical disordering.

Substrate-insensitive atomic layer deposition of plasmonic titanium nitride films

The plasmonic properties of titanium nitride (TiN) films depend on the type of substrate when using typical deposition methods such as sputtering. Here we show atomic layer deposition (ALD) of TiN films with very weak dependence of plasmonic properties on the substrate, which also suggests the prediction and evaluation of plasmonic performance of TiN nanostructures on arbitrary substrates under a given deposition condition. Our results also observe that substrates with more nitrogen-terminated (N-terminated) surfaces will have significant impact on the deposition rate as well as the film plasmonic properties. We further illustrate that the plasmonic properties of ALD TiN films can be tailored by simply adjusting the deposition and/or post-deposition annealing temperatures. Such characteristics and the capability of conformal coating make ALD TiN films on templates ideal for applications that require the fabrication of complex 3D plasmonic nanostructures.

Zinc tin oxide thin film transistors produced by a high rate reactive sputtering: Effect of tin composition and annealing temperatures

Amorphous zinc tin oxides (a-ZTO), which are stoichiometrically close to the Zn2SnO4 and ZnSnO3 phases, have been deposited using remote-plasma reactive sputtering, and incorporated as the channel layers in thin film transistors (TFTs). The influence of tin composition and annealing temperatures on the structural and phase evolutions of the thin films, and the electrical performances of the TFTs are investigated. Zn2SnO4 exhibited randomly oriented polycrystalline peaks at annealing temperatures ≥700 °C, while ZnSnO3 decomposed into Zn2SnO4 and SnO2 at 950 °C. TFTs employing a Zn2SnO4 channel, after a post-deposition annealing at 500 °C, exhibited a field effect mobility ∼14 cm2 V−1 s−1 and a sub-threshold slope ∼0.6 V dec−1. When the tin content was increased in the channel, as in ZnSnO3, TFTs exhibited an increase in field effect mobility ∼20 cm2 V−1 s−1, but with a slight deterioration of sub-threshold slope to ∼0.8 V dec−1. When the post-deposition annealing temperature was reduced to 300 °C, a mobility as high as ∼10 cm2 V−1 s−1 was still achieved, however, a significant shoulder in the IDS–VGS curve, together with a higher off-state current was observed. TFT characteristics are explained by the sub-bandgap defect states measured by photothermal deflection spectroscopy and the extracted Urbach energies.