post-CMOS Technologies Research Articles

A Extensive Review of Recent Technologies and Trends in Low-Power VLSI Design

The demand for energy-efficient electronic devices has driven significant advancements in low-power Very-Large-Scale Integration (VLSI) design. This paper presents a Extensive review of the recent technologies and trends that have emerged to address the challenges associated with power utilization in VLSI circuits. The review covers a broad spectrum of innovations, including advanced transistor technologies such as FinFETs, Gate-All-Around (GAA) FETs, and Silicon-on-Insulator (SOI), which offer improved power efficiency. It also explores cutting-edge power enhance techniques like Dynamic Voltage and Frequency Scaling (DVFS), power gating, and Multi-Threshold CMOS (MTCMOS), highlighting their impact on reducing both dynamic and leakage power. Further, the paper examines energy-efficient architectures, including Near-Threshold Computing (NTC), approximate computing, and asynchronous circuits, which promise substantial power savings. The fusing of machine learning and AI in power optimization and the development of advanced Electronic Design Automation tools are also discussed as emerging trends. Finally, the paper considers future directions, including the potential of 3D Integrated Circuits (3D ICs), quantum and neuromorphic computing, and post-CMOS technologies, to revolutionize low-power VLSI design. This review provides a critical exploration of the actual state of the art and offers comprehensions into the future trajectory of low-power VLSI, making it a valuable resource for researchers and practitioners in the field.

The Quest of the Ideal Error Detecting Architecture: The GRAAL Architecture

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen steadily making further nanometric scaling increasingly difficult. These problems would become showstoppers in ultimate-CMOS and post-CMOS technologies, unless efficient fault-mitigation and low-power approaches are developed to maintain acceptable levels of yield, reliability, and power densities. This paper describes the GRAAL architecture, which improves significantly the fault detection efficiency, cost, and timing constraints of the double-sampling approach, providing this way an efficient scheme for solving the issues induced by aggressive technology scaling in the era of ultimate-CMOS and post-CMOS technologies.

Antiferromagnetic half-skyrmions and bimerons at room temperature.

In the quest for post-CMOS (complementary metal-oxide-semiconductor) technologies, driven by the need for improved efficiency and performance, topologically protected ferromagnetic 'whirls' such as skyrmions1-8 and their anti-particles have shown great promise as solitonic information carriers in racetrack memory-in-logic or neuromorphic devices1,9-11. However, the presence of dipolar fields in ferromagnets, which restricts the formation of ultrasmall topological textures3,6,8,9,12, and the deleterious skyrmion Hall effect, when skyrmions are driven by spin torques9,10,12, have thus far inhibited their practical implementation. Antiferromagnetic analogues, which are predicted to demonstrate relativistic dynamics, fast deflection-free motion and size scaling, have recently become the subject of intense focus9,13-19, but they have yet to be experimentally demonstrated in natural antiferromagnetic systems. Here we realize a family of topological antiferromagnetic spin textures in α-Fe2O3-an Earth-abundant oxide insulator-capped with a platinum overlayer. By exploiting a first-order analogue of the Kibble-Zurek mechanism20,21, we stabilize exotic merons and antimerons (half-skyrmions)8 and their pairs (bimerons)16,22, which can be erased by magnetic fields and regenerated by temperature cycling. These structures have characteristic sizes of the order of 100nanometres and can be chemically controlled via precise tuning of the exchange and anisotropy, with pathways through which further scaling may be achieved. Driven by current-based spin torques from the heavy-metal overlayer, some of these antiferromagnetic textures could emerge as prime candidates for low-energy antiferromagnetic spintronics at room temperature1,9-11,23.

Hardware Security Exploiting Post-CMOS Devices: Fundamental Device Characteristics, State-of-the-Art Countermeasures, Challenges and Roadmap

Emerging nanoelectronic semiconductor devices have been quite promising in enhancing hardware-oriented security and trust. However, implementing hardware security primitives and methodologies requires large area overhead and power consumption. Furthermore, emerging new attack models and vulnerabilities are regularly evolving and cannot be adequately addressed by current CMOS technology. This paper for the first time presents a comprehensive review of numerous post-CMOS technologies based hardware security primitives and methodologies, particularly true random number generators, physically unclonable functions, sidechannel analysis countermeasures, and hardware obfuscation techniques. Various beyond-CMOS device technologies including tunneling FET (TFET), hybrid phase transition FET (HyperFET), carbon nanotube FET (CNTFET), silicon nanowire FET (SiNWFET), symmetrical tunneling FET (SymFET), phase-change memory (PCM), spin-transfer torque magnetic tunnel junction (STT-MTJ), resistive random access memory (RRAM) have been considered in this study. First, the basic principle of operation and unusual characteristics of nanoelectronic devices used for hardware security applications have been extensively discussed. Later, CMOS technology challenges and benefits of emerging nanotechnologies for the design of hardware security primitives and methodologies have been reported. Finally, different analyses have been presented to demonstrate the promising performance of post-CMOS devices over the current CMOS technology in different countermeasures. Additionally, challenges, future directions, and plans have been presented to achieve more research outcomes in this field.

All-Spin Bayesian Neural Networks

Probabilistic machine learning enabled by the Bayesian formulation has recently gained significant attention in the domain of automated reasoning and decision-making. While impressive strides have been made recently to scale up the performance of deep Bayesian neural networks, they have been primarily standalone software efforts without any regard to the underlying hardware implementation. In this paper, we propose an "All-Spin" Bayesian Neural Network where the underlying spintronic hardware provides a better match to the Bayesian computing models. To the best of our knowledge, this is the first exploration of a Bayesian neural hardware accelerator enabled by emerging post-CMOS technologies. We develop an experimentally calibrated device-circuit-algorithm co-simulation framework and demonstrate $24\times$ reduction in energy consumption against an iso-network CMOS baseline implementation.

Iterative Diagnosis Approach for ECC-Based Memory Repair

In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield, as well as during lifetime to increase lifespan. In technologies affected by high defect densities, conventional repair induces very high cost. To reduce it, in previous work we proposed the ECC-based repair scheme, consisting in using the ECC for fixing words comprising a single faulty cell, and self-repair to fix all other faulty words. This approach is of high interest for ultimate CMOS and post-CMOS technologies, where the defect densities are expected to increase significantly, and/or in very-low power designs as very-low voltage sharply increases defect densities. However, we showed recently that, for high defect densities the diagnosis circuitry required for ECC-based repair may induce large cost. In previous work we addressed this issue by means of a new family of memory test algorithms that exhibit the so-called single-read double-fault detection (SRDF) property. The SRDF algorithms resolve the diagnosis issue at no area cost. However, as they are complex and increase test length, in this paper we explore a new diagnosis approach using iterative test execution, which, together with the SRDF test algorithms, provide a set of options enabling efficient tradeoffs in terms of hardware and power costs, and test length.

A scalable and reconfigurable in-memory architecture for ternary deep spiking neural network with ReRAM based neurons

Neuromorphic computing using post-CMOS technologies is gaining increasing popularity due to its promising potential to resolve the power constraints in Von-Neumann machine and its similarity to the operation of the real human brain. In this work, we propose a scalable and reconfigurable architecture that exploits the ReRAM-based neurons for deep Spiking Neural Networks (SNNs). In prior publications, neurons were implemented using dedicated analog or digital circuits that are not area and energy efficient. In our work, for the first time, we address the scaling and power bottlenecks of neuromorphic architecture by utilizing a single one-transistor-one-ReRAM (1T1R) cell to emulate the neuron. We show that the ReRAM-based neurons can be integrated within the synaptic crossbar to build extremely dense Process Element (PE)–spiking neural network in memory array–with high throughput. We provide microarchitecture and circuit designs to enable the deep spiking neural network computing in memory with an insignificant area overhead. Simulation results on MNIST and CIFAR-10 datasets with spiking Resnet (SResnet) and spiking Squeezenet (SSqueez) show that compared to the baseline CPU only solution, our proposed architecture achieves energy saving between 1222 × and 1853 × and speed improvement between 791 × to 1120 ×.

Electron beam-based metrology after CMOS.

The magnitudes of the challenges facing electron-based metrology for post-CMOS technology are reviewed. Directed selfassembly, nanophotonics/plasmonics, and resistive switches and selectors, are examined as exemplars of important post-CMOS technologies. Materials, devices, and architectures emerging from these technologies pose new metrology requirements: defect detection, possibly subsurface, in soft materials, accurate measurement of size, shape, and roughness of structures for nanophotonic devices, contamination-free measurement of surface-sensitive structures, and identification of subtle structural, chemical, or electronic changes of state associated with switching in non-volatile memory elements. Electron-beam techniques are examined in the light of these emerging requirements. The strong electron-matter interaction provides measurable signal from small sample features, rendering electron-beam methods more suitable than most for nanometer-scale metrology, but as is to be expected, solutions to many of the measurement challenges are yet to be demonstrated. The seeds of possible solutions are identified when they are available.

Performance benchmarking of tunnel transistors for energy efficient 4-bit adder architectures at low V<SUB align="right">DD

Tunnel field-effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. This paper presents design analysis and benchmarking of TFET based three different 1-bit full adders (8T-XOR Logic, 6T-XOR Logic and MUX Based) are used for designing 4-bit adders in two different topologies targeting a VDD below 500 mV. These topologies are 22T/18T 1-bit full adder based 4-bit carry propagate adder (22T/18TCPA) and multiplexer logic 1-bit full adder based 4-bit carry propagate adder (MCPA). The performance of TFET based 4-bit adder topologies has been benchmarked with 20 nm double gate Si FinFET technology. Tunnel FETs are desirable candidates for building energy efficient and reliable arithmetic blocks with supply voltage scaling. We demonstrate that TFET's steep slope characteristics enable the 22TCPA design to be energy efficient option along with improved reliability and 18TCPA design is the best in terms of energy efficiency and reliability amongst all designs at low supply voltages.

Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on-state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra-low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co-design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co-design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.

A Comparative Security Analysis of Current and Emerging Technologies

During the past few decades, the electronics community has witnessed a growing demand for packing more and more functionalities onto a single chip. The CMOS industry has been fulfilling this demand by continually shrinking the feature sizes, now down to the 20-nm regime. However, scaling of CMOS technology beyond 20 nm is challenging because of exacerbated short-channel effects, process variations, and reliability problems. These drawbacks of CMOS technology have led to the exploration of new nanotechnologies such as nanoelectromechanical systems (NEMS) and carbon nanotube (CNT). These emerging technologies are considered promising alternatives to CMOS technology because of their potential benefits in power, performance, and reliability. However, security analysis of these emerging technologies, which is critical for current pervasive applications, remains unaddressed. In this article, the authors offer a security analysis of NEMS and CNT. They highlight the key technology-specific features of these post-CMOS technologies that can inform the design of secure systems.

Test Algorithms for ECC-Based Memory Repair in Ultimate CMOS and Post-CMOS

In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield. In technologies affected by high defect densities, conventional repair induces very high costs. To reduce it, we can use ECC-based repair, consisting in using the ECC for fixing words comprising a single faulty cell and self-repair to fix all other faulty words. However, as we show in this paper, for high defect densities the diagnosis circuitry required for ECC-based repair may induce very large hardware cost. To fix this issue, we introduce a new family of memory test algorithms that exhibit a property we termed as “single-read double-fault detection”. This approach gains interest in ultimate CMOS and post-CMOS technologies, where the defect densities are expected to increase significantly, and/or in very-low power design, as very-low voltage sharply increases defect densities.

Understanding CMOS Technology Through TAMTAMS Web

In the last decades, the CMOS technology has undergone an extraordinary evolution. Because of the continuous scaling process, CMOS transistors are now so small that millions can be easily fitted in a single chip. Shrinking transistor sizes have complex consequences on the performance of both the transistor itself and the system that is based upon it. Understanding and teaching the CMOS scaling process and its consequences on circuits are an increasingly difficult task. Furthermore, the scaling process is reaching an end, due to the continuously growing fabrication costs and the unavoidable physical limits on the smallest size achievable. As a consequence, many emerging technologies, such as carbon nanotubes and nanowires, are being studied as possible CMOS substitutes. Describing and teaching these new technologies, alongside the scaled transistor itself, adopting a complete and well-organized approach is a process that presents further difficulties. To solve these problems, we have started in the past years the development of TAMTAMS, a tool conceived to analyze CMOS circuits, from device to system level. The tool is based on models derived from the literature or, in some cases, internally developed and verified. It allows to analyze the main characteristics of a CMOS transistor, such as currents, threshold voltage, or mobility, considering different technology nodes and parameters, and to understand how they influence the circuits performance. The tool structure is open and modular, allowing, therefore, easy integration of further CMOS technologies and to compare them. In this paper, we present a total overview of the original tool, TAMTAMS Web. While the general concept behind the tool is still the same, the tool was completely rewritten around a Web interface. TAMTAMS Web is freely accessible to students and to any one interested in CMOS technology. As a future development, several post-CMOS technologies will be added to TAMTAMs Web, allowing, therefore, a comparison with the state-of-the-art CMOS. TAMTAMS Web is actively used in the Integrated System Technology (IST) held at the Politecnico di Torino. It defines a new way of learning, because students learn and understand the modern electronic technology both using TAMTAMS Web as an instrument, and being part of the development process, as part of the IST course.

All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron.

Artificial synaptic devices implemented by emerging post-CMOS non-volatile memory technologies such as Resistive RAM (RRAM) have made great progress recently. However, it is still a big challenge to fabricate stable and controllable multilevel RRAM. Benefitting from the control of electron spin instead of electron charge, spintronic devices, e.g., magnetic tunnel junction (MTJ) as a binary device, have been explored for neuromorphic computing with low power dissipation. In this paper, a compound spintronic device consisting of multiple vertically stacked MTJs is proposed to jointly behave as a synaptic device, termed as compound spintronic synapse (CSS). Based on our theoretical and experimental work, it has been demonstrated that the proposed compound spintronic device can achieve designable and stable multiple resistance states by interfacial and materials engineering of its components. Additionally, a compound spintronic neuron (CSN) circuit based on the proposed compound spintronic device is presented, enabling a multi-step transfer function. Then, an All Spin Artificial Neural Network (ASANN) is constructed with the CSS and CSN circuit. By conducting system-level simulations on the MNIST database for handwritten digital recognition, the performance of such ASANN has been investigated. Moreover, the impact of the resolution of both the CSS and CSN and device variation on the system performance are discussed in this work.

Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets.

Non-Boolean computing based on emerging post-CMOS technologies can potentially pave the way for low-power neural computing platforms. However, existing work on such emerging neuromorphic architectures have either focused on solely mimicking the neuron, or the synapse functionality. While memristive devices have been proposed to emulate biological synapses, spintronic devices have proved to be efficient at performing the thresholding operation of the neuron at ultra-low currents. In this work, we propose an All-Spin Artificial Neural Network where a single spintronic device acts as the basic building block of the system. The device offers a direct mapping to synapse and neuron functionalities in the brain while inter-layer network communication is accomplished via CMOS transistors. To the best of our knowledge, this is the first demonstration of a neural architecture where a single nanoelectronic device is able to mimic both neurons and synapses. The ultra-low voltage operation of low resistance magneto-metallic neurons enables the low-voltage operation of the array of spintronic synapses, thereby leading to ultra-low power neural architectures. Device-level simulations, calibrated to experimental results, was used to drive the circuit and system level simulations of the neural network for a standard pattern recognition problem. Simulation studies indicate energy savings by ∼ 100× in comparison to a corresponding digital/analog CMOS neuron implementation.

A Surface Micromachined CMOS MEMS Humidity Sensor

This paper reports a CMOS MEMS (complementary metal oxide semiconductor micro electromechanical system) piezoresistive humidity sensor fabricated by a surface micromachining process. Both pre-CMOS and post-CMOS technologies were used to fabricate the piezoresistive humidity sensor. Compared with a bulk micromachined humidity sensor, the machining precision and the sizes of the surface micromachined humidity sensor were both improved. The package and test systems of the sensor were designed. According to the test results, the sensitivity of the sensor was 7 mV/%RH (relative humidity) and the linearity of the sensor was 1.9% at 20 °C. Both the sensitivity and linearity were not sensitive to the temperature but the curve of the output voltage shifted with the temperature. The hysteresis of the humidity sensor decreased from 3.2% RH to 1.9% RH as the temperature increased from 10 to 40 °C. The recovery time of the sensor was 85 s at room temperature (25 °C).

TFET-Based Circuit Design Using the Transconductance Generation Efficiency <inline-formula> <tex-math notation="LaTeX">$ {g}_{m}/ {I}_{d}$ </tex-math></inline-formula> Method

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g., GHz operation with sub-0.1 mW power consumption); 2) discuss and employ a compact TFET device model in the context of the $g_{m}/I_{d}$ integrated analog circuit design methodology; and 3) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being interband tunneling rather than thermionic emission. Starting from technology computer-aided design and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate TFETs at the 20-nm gate-length node, we conclude that GNR TFETs might promise larger bandwidths at low-voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.

Error Adaptive Classifier Boosting (EACB): Leveraging Data-Driven Training Towards Hardware Resilience for Signal Inference

The continued scaling of CMOS technologies and consideration of post-CMOS technologies has elevated hardware reliability to a first-class challenge, particularly in energy- and resource-constrained embedded sensor applications. In such applications, there is an increasing emphasis on inference functions. Machine-learning algorithms play an important role by enabling the construction of data-driven models for inference over data that is too complex to model analytically. This paper explores how data-driven training can be exploited to also overcome computational errors due to hardware faults within an inference stage. FPGA emulation with randomized fault injections shows that the proposed architecture restores system performance to the level of a fault free system, with $ 1% of the hardware requiring explicit fault protection, and with digital faults affecting $>$ 2% of the circuit nodes in the rest of the hardware. To train an error-aware inference model, a training algorithm is presented whose hardware (memory) and energy requirements are reduced by 65 $\times$ and 10 $\times$ compared to previously reported algorithms (AdaBoost and FilterBoost respectively), thereby enabling model construction entirely on the device.

Exploiting Synchronization Properties of Correlated Electron Devices in a Non-Boolean Computing Fabric for Template Matching

As complementary metal-oxide-semiconductor (CMOS) scaling continues to offer insurmountable challenges, questions about the performance capabilities of Boolean, digital machine based on Von-Neumann architecture, when operated within a power budget, have also surfaced. Research has started in earnest to identify alternative computing paradigms that provide orders of magnitude improvement in power-performance for specific tasks such as graph traversal, image recognition, template matching, and so on. Further, post-CMOS device technologies have emerged that realize computing elements which are neither CMOS replacements nor suited to work as a binary switch. In this paper, we present the realization of coupled and scalable relaxation-oscillators utilizing the metal-insulator-metal transition of vanadium-dioxide (VO2) thin films. We demonstrate the potential use of such a system in a non-Boolean computing paradigm and demonstrate pattern recognition, as one possible application using such a system.

Nontraditional Computation Using Beyond-CMOS Tunneling Devices

Amongst potential post-CMOS technologies, tunnel field-effect transistors (TFETs) are attractive for low-power systems. While TFETs are functionally somewhat similar to MOSFETs, the newly proposed tunneling transistors such as SymFETs and BiSFETs demonstrate more “exotic” characteristics that are significantly different from MOSFETs. We look at the possible applications of TFETs and SymFETs for unconventional signal processing by employing their signature behaviors. We focus on networks of interconnected nonlinear elements which can process data coming from a large number of inputs (e.g., sensors) in an analog fashion. Specifically, we investigate several applications of TFET and SymFET in directional and anisotropic diffusion, estimating Gaussian distance of different patterns in analog associative memories, and estimating minimum/maximum or variance of analog data. We show that such circuits have reduced complexity and/or enhanced power efficiency.