Positive Threshold Voltage Shift Research Articles

Influence of electrical field on the susceptibility of gallium nitride transistors to proton irradiation

Radiation susceptibility of electronic devices is commonly studied as a function of radiation energetics and device physics. Often overlooked is the presence or magnitude of the electrical field, which we hypothesize to play an influential role in low energy radiation. Accordingly, we present a comprehensive study of low-energy proton irradiation on gallium nitride high electron mobility transistors (HEMTs), turning the transistor ON or OFF during irradiation. Commercially available GaN HEMTs were exposed to 300 keV proton irradiation at fluences varying from 3.76 × 1012 to 3.76 × 1014 cm2, and the electrical performance was evaluated in terms of forward saturation current, transconductance, and threshold voltage. The results demonstrate that the presence of an electrical field makes it more susceptible to proton irradiation. The decrease of 12.4% in forward saturation and 19% in transconductance at the lowest fluence in ON mode suggests that both carrier density and mobility are reduced after irradiation. Additionally, a positive shift in threshold voltage (0.32 V and 0.09 V in ON and OFF mode, respectively) indicates the generation of acceptor-like traps due to proton bombardment. high-resolution transmission electron microscopy and energy dispersive x-ray spectroscopy analysis reveal significant defects introduction and atom intermixing near AlGaN/GaN interfaces and within the GaN layer after the highest irradiation dose employed in this study. According to in-situ Raman spectroscopy, defects caused by irradiation can lead to a rise in self-heating and a considerable increase in (∼750 times) thermoelastic stress in the GaN layer during device operation. The findings indicate device engineering or electrical biasing protocol must be employed to compensate for radiation-induced defects formed during proton irradiation to improve device durability and reliability.

Origin and Recovery of Negative VTH Shift on 4H–SiC MOS Capacitors: An Analysis Based on Inverse Laplace Transform and Temperature-Dependent Measurements

SiC power MOSFETs are reported to suffer from both positive and negative threshold voltage shifts. Positive shift is well understood in the literature and attributed to electron trapping in near interface oxide traps (NIOTs). Negative shift is explained by hole generation and trapping in the oxide via impact ionization favored by the strong oxide field. However, studies on negative shift are still ongoing, and the origin and nature of the process are not fully understood. This study advances the comprehension of negative threshold voltage shift by investigating MOS capacitors subject to positive bias stress.We demonstrate that: a) a significant negative threshold shift is observed when the electric field is greater than 7.5 MV/cm; b) the detected shift is not recoverable at zero bias. Recovery can be obtained only by applying a positive gate voltage indicating a field-driven detrapping process. c) Trap-state mapping measurements were carried out to extract the activation energy of the detrapping processes, and a weak thermal activation was observed.Results collected within this paper indicate that holes are trapped at deep centers, and thermal detrapping is not possible. Hole release is only possible when a high field is applied to the insulator, possibly due to the recombination between leaking electrons and trapped holes.

Abnormal Positive Shift of Threshold Voltage in Praseodymium-Doped InZnO-TFTs Under Negative Bias Illumination Temperature Stress

Abnormal Positive Shift of Threshold Voltage in Praseodymium-Doped InZnO-TFTs Under Negative Bias Illumination Temperature Stress

Surface passivation properties of atomic-layer deposited hafnium oxide on a (100) β-Ga2O3 MOSFET

We report the effect of HfO2 passivation on the electrical characteristics of (100) β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs). The atomic-layer-deposited HfO2 layer with negative defect charges enhances the transconductance and subthreshold slope. A significant positive threshold voltage (V TH) shift of ∼32 V is induced after the passivation. Moreover, significantly less V TH shift of ∼2 V is observed under negative bias stress (NBS) for 3600 s in comparison with an Al2O3 passivated and unpassivated device. Physics-based technology computer aided design (TCAD) simulation is performed to demonstrate the surface depletion effect and the dependency on the density of negative fixed charges in the HfO2 passivation layer. Finally, the HfO2 passivated device maintains superior electrical characteristics compared to the unpassivated device at a temperature of up to 500 K.

A Comparative Study on the Degradation Behaviors of Ferroelectric Gate GaN HEMT with PZT and PZT/Al2O3 Gate Stacks.

In this paper, the degradation behaviors of the ferroelectric gate Gallium nitride (GaN) high electron mobility transistor (HEMT) under positive gate bias stress are discussed. Devices with a gate dielectric that consists of pure Pb(Zr,Ti)O3 (PZT) and a composite PZT/Al2O3 bilayer are studied. Two different mechanisms, charge trapping and generation of traps, both contribute to the degradation. We have observed positive threshold voltage shift in both kinds of devices under positive gate bias stress. In the devices with a PZT gate oxide, we have found the degradation is owing to electron trapping in pre-existing oxide traps. However, the degradation is caused by electron trapping in pre-existing oxide traps and the generation of traps for the devices with a composite PZT/Al2O3 gate oxide. Owing to the large difference in dielectric constants between PZT and Al2O3, the strong electric field in the Al2O3 interlayer makes PZT/Al2O3 GaN HEMT easier to degrade. In addition, the ferroelectricity in PZT enhances the electric field in Al2O3 interlayer and leads to more severe degradation. According to this study, it is worth noting that the reliability problem of the ferroelectric gate GaN HEMT may be more severe than the conventional metal-insulator-semiconductor HEMT (MIS-HEMT).

Barrier and channel thickness engineering to optimize fin height for enhancement mode Al0.3Ga0.7N/GaN FinHEMT

AbstractIn this work, a thorough analysis of the Al0.3Ga0.7N/GaN FinHEMT structure has been performed using three‐dimensional numerical simulations to achieve enhancement mode (E‐mode) operation. In the proposed optimized structure, the fin height (HFin) is comprised of 7 nm critical strained AlGaN barrier layer with 30% Al mole fraction and 63 nm GaN channel layer having a fixed fin width (WFin) of 160 nm. The two‐dimensional electron gas (2DEG) concentration near the hetero interface is found to vary inversely with HFin of the proposed structure. The 2DEG variation was compared between fin‐shaped full tri‐gate approach and variable side gate length tri‐gate design counterpart for a fixed HFin of 70 nm. We achieved an improved threshold voltage of −0.2 V in the optimized HFin structure as compared to −1.45 V obtained in the unoptimized structure as reported earlier. Further, upon decreasing WFin to 40 nm in the same structure having optimized HFin of 70 nm, an E‐mode operation was achieved with a positive threshold voltage of 0.4 V. The positive shift in threshold voltage is explained with the help of necessary energy band diagram.

Reducing proton radiation vulnerability in AlGaN/GaN high electron mobility transistors with residual strain relief

Strain plays an important role in the performance and reliability of AlGaN/GaN high electron mobility transistors (HEMTs). However, the impact of strain on the performance of proton irradiated GaN HEMTs is yet unknown. In this study, we investigated the effects of strain relaxation on the properties of proton irradiated AlGaN/GaN HEMTs. Controlled strain relief is achieved locally using the substrate micro-trench technique. The strain relieved devices experienced a relatively smaller increase of strain after 5 MeV proton irradiation at a fluence of 5 × 1014 cm−2 compared to the non-strain relieved devices, i.e., the pristine devices. After proton irradiation, both pristine and strain relieved devices demonstrate a reduction of drain saturation current (Ids,sat), maximum transconductance (Gm), carrier density (ns), and mobility (μn). Depending on the bias conditions the pristine devices exhibit up to 32% reduction of Ids,sat, 38% reduction of Gm, 15% reduction of ns, and 48% reduction of μn values. In contrast, the strain relieved devices show only up to 13% reduction of Ids,sat, 11% reduction of Gm, 9% reduction of ns, and 30% reduction of μn values. In addition, the locally strain relieved devices show smaller positive shift of threshold voltage compared to the pristine devices after proton irradiation. The less detrimental impact of proton irradiation on the transport properties of strain relieved devices could be attributed to reduced point defect density producing lower trap center densities, and evolution of lower operation related stresses due to lower initial residual strain.

AlGaN High Electron Mobility Transistor for High Temperature Logic

We report on AlGaN HEMT-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data revealed the GaN-channel HEMT experienced a 6.9× reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200 nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

Effect of Large-Area Exfoliation and Etching on the Electrical Behavior of Transition-Metal Dichalcogenide Field-Effect Transistors

Large-area layer transfer was used to fabricate multilayer transition-metal dichalcogenide (TMDC) thin-film transistor (TFT) arrays with areas of (40 × 40 μm2) from single-crystal flakes. The effects of plasma etching of the TFT backchannel surface and bulk defects in the layers on the electrical performance and stability of the n-channel depletion-mode TFTs were investigated. Few-layer structures (∼3 monolayers) were fabricated using a dry etching process to thin multilayer (∼60–90 nm thick) TMDC structures. The etching improved the threshold voltage of the TFTs, resulting in a positive threshold voltage shift of +40 V after etching the backchannel, correlating to a bulk trap density of approximately 1 × 1016 cm–3 eV–1 per monolayer. Etching the MoS2 surface resulted in a threshold voltage shift of 0.2 V per nanometer of MoS2 removed (for MoS2 thicknesses >15 nm). For MoS2 layers etched to <15 nm, the threshold voltage changed to ∼1.8 V per nanometer. An observed degradation of the carrier transport and electrical stability of these samples were found to be due to the proximity of the etched surface approaching the active channel region of the device. The results reveal the performance trade-offs of fabricating large-area arrays of few-layer TMDC TFTs using a mechanical exfoliation and dry etching approach.

1/f noise of short-channel indium tin oxide transistors under stress

In this work, we investigate the reliability and stability of short-channel indium tin oxide (ITO) field-effect transistors through 1/f noise characterization at elevated temperature with positive bias temperature instability (PBTI). The 1/f noise behavior of a short-channel 60-nm-long channel ITO transistor can be described by the carrier number fluctuation model, suggesting that carrier trapping and de-trapping by trap states within the 5 nm thin high-κ HfLaO dielectric are the dominant mechanisms affecting 1/f noise. Small positive threshold voltage shifts of 0.042 and 0.057 V after PBTI measurements of 3000 s at 25 and 85 °C have been obtained, respectively. The higher gate leakage current at elevated temperature leads to an earlier breakdown in the time-dependent dielectric breakdown measurement. Furthermore, 1/f noise after PBTI has also been carried out at elevated temperature, and the degradations after stress can also be attributed to the stress induced traps inside the gate dielectric.

35‐4: Carbon Nanotube Thin‐Film Transistors for Active‐Matrix Micro‐LED Display – Device Performances, Bias Stress Stability and Compact Modeling

Carbon nanotube thin‐film transistor (CNT‐TFT) is expected to be a promising candidate for backplane technologies for emerging displays including micro‐LED, due to its extraordinary driving capability. In this work, CNT‐TFTs are characterized, which exhibit excellent on‐state current, high carrier mobility, and low subthreshold swing. Different from conventional TFTs, a positive threshold voltage shift under negative bias stress is observed in these devices. The mechanism is explored and explained, and an improved stretched‐exponential model is developed for such phenomenon. To predict the driving capability of CNT‐TFT backplane technology, compact models for CNT‐TFTs and micro‐LEDs are built based on experimental data, and SPICE simulation of a 3T1C pixel circuit is carried out. The results indicate that CNT‐TFTs enables high driving current in active‐matrix micro‐LED display with relative ease, paving the way for practical applications of CNT‐TFTs.

Scalable Charge-Based Compact Model for Drain Current in Fin-Shaped GaN HEMTs

We present a novel charge-based compact model for drain current in fin-shaped GaN high-electron-mobility transistors (Fin-HEMTs). A positive threshold voltage shift is observed in Fin-HEMTs due to better gate control of the channel. The combined effect of top and side gates on the channel charge density is studied with the help of detailed TCAD simulation. For the first time, a closed-form expression for 2-D electron gas (2-DEG) density in Fin-HEMTs is derived. The fin width dependence of the 2-DEG current is modeled in a unique way by considering the modified gate capacitance and threshold voltage in Fin-HEMTs. The total drain current is modeled as the sum of 2-DEG and double-gate field effect transistor (FET) currents. In addition, the total gate capacitance including the side-gate capacitance for fin structure is also formulated. The model is generic and can be used for different fin geometries using the proposed equivalent circuits as demonstrated. A fin-width-dependent thermal resistance model is proposed and included in the drain current model using a thermal subcircuit. The proposed model is completely analytical and does not require any iteration or fitting parameters in contrast to the available models discussed in the literature. Our model shows excellent agreement with the state-of-the-art experimental data.

Impact of low-dose radiation on nitrided lateral 4H-SiC MOSFETs and the related mechanisms

Lateral type n-channel 4H-SiC metal--oxide--semiconductor field effect transistors (MOSFETs), fabricated using a current industrial process, are irradiated with gamma rays at different irradiation doses in this paper to carry out a profound study on the generation mechanism of radiation-induced interface traps and oxide trapped charges. Electrical parameters (e.g., threshold voltage, subthreshold swing and channel mobility) of the device before and after irradiation are investigated, and the influence of the channel orientation ( and ) on the radiation effect is discussed for the first time. A positive threshold voltage shift is observed at very low irradiation doses (< 100 krad (Si)); the threshold voltage then shifts negatively as the dose increases. It is found that the dependence of interface trap generation on the radiation dose is not the same for doses below and above 100 krad. For irradiation doses < 100 krad, the radiation-induced interface traps with relatively high generation speeds dominate the competition with radiation-induced oxide trapped charges, contributing to the positive threshold voltage shift correspondingly. All these results provide additional insight into the radiation-induced charge trapping mechanism in the SiO2/SiC interface.

Strain relaxation and self-heating effects of fin AlGaN/GaN HEMTs

In this paper, we present a methodology of 3D electro-thermo-mechanical simulation to analyze the strain relaxation and self-heating effects of fin AlGaN/GaN high electron mobility transistors (HEMTs). The free boundaries of narrow fins cause strain relaxation of the AlGaN barrier and a non-uniform strain distribution near the AlGaN/GaN interface. The strain relaxation not only reduces the surface piezoelectric polarization charges (PPCs), but also introduces space PPCs in AlGaN/GaN, leading to a reduction of two-dimensional electron gas density and a positive shift of threshold voltage (V th). The simulated V th shift with fin width agrees well with experimental results from literature. In addition, the inter-fin trenches facilitate more efficient lateral heat spreading and suppress the self-heating effect compared with the planar HEMTs with the same effective gate width.

Study of GaN/AlGaN air structure gate HEMTs with high linearity for RF applications

The effect of a novel float gate HEMT with Gan cap under the gate is studied, its DC and RF characteristics have been shown by using SILVACO TCAD tool, as contrast, the simulation of the conventional T shape gate hemt, which fitting well with the experimental result, is also demonstrated. The proposed structure offers approximately 5 times improvement in power gain cutoff frequency (fmax) and current gain Cut-off frequency(fT) (from 5.68 and 3.7 GHz to 30.1 and 20.1 GHz, respectively.) and it greatly enhances the linearity of the Gan based HEMT, a much flatter curve for fT/fmax versus gate voltage are also shown, and 1 V positive threshold voltage shift is gained, meanwhile the off-state drain leakage current is also improved to a certain extend, therefor the hemt obtains a much higher Ion/Ioff ratio, without sacrificing the saturate current. Besides, the degradation of drain current due to the self-heating effect is also ameliorated by applying the novel structure. Finally, the corresponding electrical characteristic changes are systematically analyzed according to the energy band and other schematic diagrams, the physical insight is given in explaining the mechanism inside.

Suppression of Kink in the Output Characteristics of AlInN/GaN High Electron Mobility Transistors by Post-Gate Metallization Annealing

In this paper, we report the effect of post-gate metallization annealing on the performance of GaN-based High Electron Mobility Transistors (HEMTs). The performances of HEMTs annealed at 200 °C (HEMT1) and at 400 °C (HEMT2) for 5 minutes in N2 ambient are compared. While there is a kink in the output characteristics of HEMT1, there is no such kink in the output characteristics of HEMT2. The kink is attributed to impact ionization in the GaN channel. Surface and interface traps of HEMT1 increase the peak electric field at the drain side gate edge and cause impact ionization. The post-gate metallization annealing at a higher temperature reduces the surface and interface traps, which reduces the peak electric field in HEMT2 and suppresses impact ionization. This is substantiated by TCAD simulations. Threshold voltage instability on the application of negative gate bias stress was also examined for these devices. A positive shift in threshold voltage was observed in HEMT1 on the application of negative gate bias stress, whereas the corresponding shift was negative in HEMT2, indicating the presence of two different types of traps in HEMT1 and HEMT2.

Localized strain relaxation effect on gamma irradiated AlGaN/GaN high electron mobility transistors

Strain localization in microelectronic devices commonly arises from device geometry, materials, and fabrication processing. In this study, we controllably relieve the local strain field of AlGaN/GaN HEMTs by milling micro-trenches underneath the channel and compare the device performance as a function of the relieved strain as well as radiation dosage. Micro-Raman results suggest that the trenches locally relax the strain in device layers, decreasing the 2DEG density and mobility. Intriguingly, such strain relaxation is shown to minimize the radiation damage, measured after 10 Mrads of 60Co-gamma exposure. For example, a 6-trench device showed only ∼8% and ∼6% decrease in saturation drain current and maximum transconductance, respectively, compared to corresponding values of ∼15% and ∼30% in a no-trench device. Negative and positive threshold voltage shifts are observed in 6-trench and no-trench devices, respectively, after gamma radiation. We hypothesize that the extent of gamma radiation damage depends on the strain level in the devices. Thus, even though milling a trench decreases 2DEG mobility, such decrease under gamma radiation is far less in a 6-trench device (∼1.5%) compared to a no-trench device (∼20%) with higher built-in strain.

Threshold voltage instability by charge trapping effects in the gate region of p-GaN HEMTs

In this work, threshold voltage instability of normally off p-GaN high electron mobility transistors has been investigated by monitoring the gate current density during a device on-state. The origin of gate current variations under stress has been ascribed to charge trapping occurring at different interfaces in the metal/p-GaN/AlGaN/GaN system. In particular, depending on the stress bias level, electrons (VG &amp;lt; 6 V) or holes (VG &amp;gt; 6 V) are trapped, causing a positive or negative threshold voltage shift ΔVTH, respectively. By monitoring the gate current variations at different temperatures, activation energies associated with the electrons and holes trapping could be determined and correlated with the presence of nitrogen (electron traps) or gallium (hole traps) vacancies. Moreover, the electrical measurements suggested the generation of a new electron-trap upon long-time bias stress, associated with the creation of crystallographic dislocation-like defects extending across different interfaces (p-GaN/AlGaN/GaN) of the gate stack.

Understanding the Degradation of 1.2-kV Planar-Gate SiC MOSFETs Under Repetitive Over-Load Current Stress

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has superior performances in terms of high switching frequency and low power loss, but its widespread applications in markets have been partly hindered by its ruggedness and reliability. Overcurrent operation is a common phenomenon which causes overheat of power devices and further leads to degradation or even device failures in power electronic systems. However, in- depth degradation mechanism and limiting factors of repetitive overcurrent capability have not been comprehensively studied yet. In this article, we investigated the conduction and the switching overcurrent stress separately to figure out the roles of each operation processes in the degradation of 1.2-kV SiC planar-gate MOSFETs for the first time. It is observed that the conduction overcurrent stress causes a positive shift of threshold voltage, while the switching overcurrent stress leads to a negative shift of threshold voltage as well as larger gate leakage current. Electrons captured at the SiC/SiO2 interface may be the reason for the positive shift of threshold voltage, while the negative shift of threshold voltage may be due to the injection and accumulation of the holes into the gate oxide at JFET and near-channel region. Both experimental results and simulation analysis show that the switching overcurrent stress plays a major role in the degradation of 1.2-kV SiC planar-gate MOSFETs under repetitive overcurrent stress. In addition, the influence of major limiting factors, including overcurrent level, overcurrent duration, and drain–source voltage, is also investigated to evaluate the reliability of SiC planar-gate MOSFETs under different overcurrent conditions, which will provide a useful guidance for dedicated design and utilization of SiC MOSFETs.

The Effect of Ionization Damage on Displacement Damage in AlGaN/GaN HEMTs

This article investigates the synergistic radiation effects on AlGaN/GaN high electron mobility transistors (HEMTs) using the individual irradiation of 1-MeV electrons and 170-keV protons, and the combined irradiation of 170-keV electrons and 170-keV protons. The electrical degradation of HEMTs is examined under the individual irradiation and the combined irradiation. The transconductance and threshold voltage were almost unchanged when the fluence of 1-MeV electron irradiation reached <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times 10^{14}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> . The AlGaN/GaN HEMTs show excellent resistance to ionization radiation. It shows a positive shift of threshold voltage after proton irradiation reached <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times 10^{13}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> . The drain current and the carrier mobility obviously decrease under proton irradiation. The negatively charged displacement defects deplete and scatter the channel carriers, leading to the degradation of the samples. The displacement damage is also the main reason during combined irradiation. However, with the participation of electron irradiation, the degradation of the transistors is much greater than that caused by individual proton irradiation. The degradation rate caused by the combined irradiation is almost three times that caused by the individual proton irradiation. In AlGaN/GaN HEMTs, there is a synergistic effect between ionization and displacement effect. This means that ionization radiation can promote displacement damage.