Positive Gate Voltage Research Articles

Ambipolar transport in Ni-catalyzed InGaAs nanowire field-effect transistors for near-infrared photodetection

Weak n-type characteristics or poor p-type characteristics are limiting the applications of binary semiconductors based on ambipolar field-effect transistors (FETs). In this work, a ternary alloy of In0.2Ga0.8As nanowires (NWs) is successfully prepared using a Ni catalyst during a typical solid-source chemical-vapor-deposition process to balance the weak n-type conduction behavior in ambipolar GaAs NWFETs and the poor p-type conduction behavior in ambipolar InAs NWFETs. The presence of ambipolar transport, contributed by a native oxide shell and the body defects of the prepared In0.2Ga0.8As NWs, is confirmed by the constructed back-gated NWFETs. As demonstrated by photoluminescence, the bandgap of the prepared In0.2Ga0.8As NWs is 1.28 eV, offering the promise of application in near-infrared (NIR) photodetection. Under 850 nm laser illumination, the fabricated ambipolar NWFETs show extremely low dark currents of 50 pA and 0.5 pA when positive and negative gate voltages are applied, respectively. All the results demonstrate that with careful design of the surface oxide layer and the body defects, NWs are suitable for use in next-generation optoelectronic devices.

Trap-Assisted Charge Storage in Titania Nanocrystals toward Optoelectronic Nonvolatile Memory.

Transistor-based memories are of particular significance in the pursuit of next-generation nonvolatile memories. The charge storage medium in a transistor-based memory is pivotal to the device performance. In this report, nitrogen doping titania nanocrystals (N-TiO2 NCs) synthesized through a low-temperature nonhydrolytic method are used as the charge storage medium in a graphene transistor-based memory. The decoration of the N-TiO2 NCs enables the device to perform as an ultraviolet (UV) light-programmable nonvolatile optoelectronic memory. Multilevel nonvolatile information recording can be realized through accurate control of the incident light dose, which is ascribed to the vast and firm hole trapping abilities of the N-TiO2 NCs induced by the N dopant. Accordingly, a positive gate voltage can be used to erase the programmed state by promoting the recombination of stored holes in N-TiO2 NCs. This study manifests the importance of trap engineering for information storage and provides an alternative path toward nonvolatile optoelectronic memory.

Optoelectronic synapse using monolayer MoS2 field effect transistors

Optical data sensing, processing and visual memory are fundamental requirements for artificial intelligence and robotics with autonomous navigation. Traditionally, imaging has been kept separate from the pattern recognition circuitry. Optoelectronic synapses hold the special potential of integrating these two fields into a single layer, where a single device can record optical data, convert it into a conductance state and store it for learning and pattern recognition, similar to the optic nerve in human eye. In this work, the trapping and de-trapping of photogenerated carriers in the MoS2/SiO2 interface of a n-channel MoS2 transistor was employed to emulate the optoelectronic synapse characteristics. The monolayer MoS2 field effect transistor (FET) exhibits photo-induced short-term and long-term potentiation, electrically driven long-term depression, paired pulse facilitation (PPF), spike time dependent plasticity, which are necessary synaptic characteristics. Moreover, the device’s ability to retain its conductance state can be modulated by the gate voltage, making the device behave as a photodetector for positive gate voltages and an optoelectronic synapse at negative gate voltages.

Abnormal Negative Bias Stress Instability of Amorphous InGaZnO Thin Film Transistors

The negative bias stress normally yields a negative threshold voltage shift of the thin film transistors due to the additional positive charges trapped in the gate dielectrics or at channel/gate insulator interface. However, a positive threshold voltage shift of the device with the post InGaZnO deposition annealing at 400oC is observed in our devices. The Na+ incorporation from Mo gate into the gate dielectric after 400oC annealing is responsible for this abnormal threshold voltage shift. The movement of Na+ ions toward the gate electrode by the negative gate bias decreases the distance between the gate electrode and the Na+ ions. Therefore, the voltage drop between the gate electrode and the Na+ ions reduces, and a corresponding positive threshold voltage shift is observed. Inserting a SiNx layer between the SiOx gate insulator and the Mo gate electrode can reduce the Na+ mobility, and thus a normal negative threshold voltage shift resumes. Experiment: A Mo layer with the thickness of 100 nm was sputtered on glass, and patterned as the gate electrode. Then 300 nm thick SiOx was deposited on the Mo gate electrode by plasma enhanced chemical vapor deposition (PECVD) at 350oC. A 50 nm a-IGZO active layer was sputtered on SiOx. PDA was performed with an O2/N2 gas with a mixing ratio of 1:4, and the annealing temperature is 350oC or 400oC for 1 hour. A 200 nm SiOx layer was deposited on the active layer by PECVD at 200oC as the etch-stop layer. After that, 100 nm Mo was sputtered as the source and drain electrodes. The channel width and length of all TFTs are 20μm and 10μm, respectively. Additional 100 nm thick SiOx was deposited by PECVD at 200oC as the passivation layer. Result and Discussion: The slightly negative VT shift of the device with 350oC PDA after negative bias stress (NBS) was mainly attributed to the hole-trapping in the gate insulator [1] or at the a-IGZO/gate insulator interface [2]-[3]. As the trapped holes increase, the VT shifts to the negative direction. However, the abnormally negative VT shift of the device with 400oC PDA after NBS was due to the motion of mobile Na+ in the gate insulator [4]. The Mo electrode has the Na+ concentration of ∼1×1015 cm−3, which was confirmed by second ion mass spectroscopy (SIMS). These results suggest that the origin of Na+ may be due to the contamination or the purity of Mo target. On the other hand, the peak concentration of Na+ in the device with 400oC PDA is approximately 5X of 350oC PDA. Fig. 1 shows the transfer characteristics of devices after NBS prebiased with a positive gate voltage (VGS=20V for 600 seconds). The larger positive VT shift of 400oC PDA TFT with prebias after NBS than the fresh devices is due to the large movement of Na+ toward gate electrode. Fig. 2(a) and (b) shows the band diagram to illustrate the Na+ effect. During the prebias period, Na+ near the SiOx/Mo gate electrode interface drifts toward the a-IGZO channel. When negative bias is applied at the Mo gate, Na+ moves toward the gate electrode. As the distance between Na+ and gate electrode decreases, the negative voltage drop at the gate electrode decreases, which “effectively” shifts the VT to the positive direction. In order to reduce the impact of Na+ movement, a 50nm SiNx layer was inserted between the SiOx insulator and the Mo gate electrode, and the VT shift after NBS with prebias recovered to negative direction. For SIMS measurement, the peak concentration of Na+ near SiOx and SiNx interface of the device with SiNx layer are smaller than near SiOx and Mo interface of the device without SiNx layer. On the other hand, the Na+ trapped in SiNx has low mobility and relatively low movement during NBS [5]. Therefore, the effectively positive voltage shift caused by Na+ movement is suppressed, and thus improves the reliability of 400oC PDA device. Acknowledgement: The support of INNOLUX and the Ministry of Science and Technology, Taiwan (MOST 108-2622-8-002-016, MOST 108-2218-E-002-027) is highly acknowledged.[1] Y. K. Moon et al., JJAP (2009) [2] E. N. Cho et al., Trans. Device Mater. Rel. (2011) [3] W. T. Chen et al., EDL (2011)[4] C. Lo et al., J-EDS (2016) [5] B.-D. Choi et al., JJAP (2005) Figure 1

Advances for Enhanced GaN-Based HEMT Devices with p-GaN Gate

With the development of high-voltage switches and high-speed RF circuits, the enhancement mode(E-mode) AlGaN/GaN HEMTs have become a hot topic in those fields. The E-mode GaN-based HEMTs have channel current at the positive gate voltage, greatly expanding the device in low power digital circuit applications. The main methods to realize E-mode AlGaN/GaN HEMT power devices are p-GaN gate technology, recessed gate structure, fluoride ion implantation technology and Cascode structure (Cascode). In this paper, the advantage and main realizable methods of E-mode AlGaN/GaN HEMT are briefly described. The research status and problems of E-mode AlGaN/GaN HEMT devices fabricated by p-GaN gate technology are summarized. The advances of p-GaN gate technology, and focuses on how these research results can improve the power characteristics and reliability of E-mode AlGaN/GaN HEMT by optimizing device structure and improving process technology, are discussed.

Energy distribution of interface states generated by oxygen plasma treatment for control of threshold voltage in pentacene thin-film transistors

Pentacene metal-oxide-semiconductor (MOS) capacitors with a SiO2 dielectric treated by oxygen plasma have been studied by capacitance-voltage (C-V) measurements to investigate the energy distribution of the interface states. Oxygen plasma treatment, which is used for control of the threshold voltage in pentacene thin-film transistors, shifted the C-V curves of pentacene MOS capacitors to a positive gate voltage as well as the transfer curves of pentacene thin-film transistors (TFTs). The shift is explained by electrons captured at interface states generated by oxygen plasma treatment. The interface states capturing the electrons are expected to locate at low energy levels. The energy distribution of the interface states locating at middle or high energy levels was extracted by a method equivalent to the Terman method. By use of the method in two steps, the interface state densities distributed at middle and high energy levels (D M and D H) were separately obtained. D M and D H were of the order of 1010–1012 cm−2 eV−1, and increased with an increase in plasma treatment time.

Deep Neural Network (DNN) Optimized Design of 2.45 GHz CMOS Rectifier With 73.6% Peak Efficiency for RF Energy Harvesting

This article presents a two-stage rectifier with novel DC-boosted gate bias for RF energy harvesting. The auxiliary gate bias enables rectifier to operate when input amplitude is smaller than its transistor threshold voltage while constraining the positive gate voltage during off state to reduce the reverse leakage current. An automated design optimization methodology using Deep Neural Network (DNN) to maximize efficiency is presented. The DNN is shown to accurately model SPICE simulated response of rectifier. Hence, the design phase turnaround time is minimized with fast prediction of optimized design parameters. The proposed rectifier has been fabricated in 65 nm standard CMOS technology. A maximum power conversion efficiency of 73.6% is measured at 2.45 GHz with input power of −6 dBm. The proposed rectifier has a measured sensitivity of −12 dBm for 1 V output voltage.

Light‐Assisted and Gate‐Tunable Oxygen Gas Sensor Based on Rhenium Disulfide Field‐Effect Transistors

Gas sensors based on transition metal dichalcogenides (TMDCs) have attracted much attention from a new perspective involving light‐assisted or gate‐voltage operation. However, their combined roles as regards the gas sensing performance and mechanism are not yet understood due to the lack of controlled studies. This study systematically investigates the oxygen sensor performance and mechanism of few‐layer‐thick rhenium disulfide (ReS2) field‐effect transistors (FETs) under light illumination and gate biasing. As a result, a combination of light illumination and positive gate voltage enhances the device response over 100% at a 1% oxygen concentration; that is, the approach achieves a practical sensitivity of 0.01% ppm−1, which outperforms most of the reports available in the literature. Furthermore, the fabricated devices exhibit long‐term stability and stable operation even under humid conditions, indicating the ability of the sensor device to operate in a real‐time application. These results contribute to the development of versatile tunable oxygen sensors based on TMDC FETs.

A facile route to enhance the mobility of MoTe2 field effect transistor via chemical doping

Abstract Modulating electrical characteristics is essential to attain a progressive performance of electronic devices such as field effect transistors (FETs). Chemical doping is very beneficial technique which is so simple and cost effective than other methods used in electronic devices for improvement of electrical characteristics. Here we report the effect of chemical doping with dopant tetracyanoquinodimethane (TCNQ) for the multilayer (ML)-MoTe2 field effect transistor (FET) to control its electrical properties. The threshold voltage (Vth) is shifted from negative to positive back gate voltage which shows p-type doping, furthermore, it was confirmed by Raman spectroscopy, the peak A1g is shifted towards higher wave number showing p-type doping effect in MoTe2 FET. Moreover, the full width at half maximum (FWHM) is reduced and the intensity ratio of the characteristic peaks (A1g and E12g) is decreased with respect to reaction time. The electrical measurements revealed improved current on/off ratio from 105 to107, mobility from 26.2 cm2/V s to 178.73 cm2/V s and charge carrier density from 3.41 × 1012 cm−2 to 7.9 × 1012 cm−2. These results offer the possibility of employing MoTe2 FETs in electronics.

Sulpho-Salicylic Acid Grafted to Ferrite Nanoparticles for n-Type Organic Semiconductors.

A disadvantage of the use of pentacene and typical organic materials in electronics is that their precursors are toxic for manufacturers and the environment. To the best of our knowledge, this is the first report of an n-type non-toxic semiconductor for organic transistors that uses sulpho-salicylic acid—a stable, electron-donating compound with reduced toxicity—grafted on a ferrite core–shell and a green synthesis method. The micro-physical characterization indicated a good dispersion stability and homogeneity of the obtained nanofilms using the dip-coating technique. The in-situ electrical characterization was based on a point-contact transistor configuration, and the increase in the drain current as the positive gate voltage increased proved the functionality of the n-type semiconductor.

(Invited) UV and Gate Stress Induced Defects in Amorphous Indium Gallium Zinc Oxide Thin Film Transistors and Self-Repair

Defects were generated in the amorphous indium gallium zinc oxide thin film transistor under combined ultraviolet light illumination and gate bias stress conditions, which showed as the positive shift of the threshold voltage and the increase of the threshold swing. When exposed to the ultraviolent light without or with the positive gate voltage bias, positively charged defects were quickly generated and saturated at the gate dielectric interface. Majority of these defects were self-repaired at room temperature under air exposure within 5 minutes. On the other hand, under the ultraviolent exposure and negative gate voltage bias condition, two types of defects were generated, i.e., those loosely trapped at the interface and those deeply trapped in the bulk of the gate dielectric layer. At room temperature, the former were quickly self-repaired and the latter were slowly self-repaired. All defects were removed when annealed at 200°C. The understanding of the defect generation and removal mechanism is important for practical applications of this type of oxide thin film transistor.

Highly accurate tuning of current–voltage characteristic shift in a photo-sensitive three terminal metal–insulator–semiconductor device

We present a planar three terminal device fabricated on a silicon-on-insulator substrate. The device is based on a two-layer dielectric stack comprising SiO2 tunneling and HfO2 layers. A so-called gate electrode is placed between two other contacts, of the source and drain, all deposited on the insulator stack. In the dark as well as under illumination, the current–voltage characteristic can be shifted in an ideal linear manner with changes in a positive gate voltage with the shift being somewhat larger under illumination. The reason for the change of shift is the ability of high-density oxygen vacancies, arranged in the filament regions within an HfO2 sublayer that was voltage stress. Namely, holes or electrons are trapped in the HfO2 sublayer, respectively, from the inverted or accumulated Si layer. This process is controlled by the gate and drain bias levels. Moreover, under illumination and at negative gate and drain voltages, the device exhibits negative differential resistance caused by capture of photo-generated minority carriers induced in the depletion region of the Si after they tunnel through the SiO2 layer by negative oxygen vacancies that migrate to the SiO2/HfO2 interface through the filament regions. Finally, the low level of saturation current in the dark and the ability to precisely control its value by illumination intensity, together with a large sensitivity of 80–85 A/W and 25 A/W, at 490 nm and 365 nm, respectively, allow additional applications that cannot be achieved with conventional MIS devices.

Lanthanum Doping in Zinc Oxide for Highly Reliable Thin-Film Transistors on Flexible Substrates by Spray Pyrolysis.

Solution-processed metal-oxide thin-film transistors (TFTs) are considered as one of the most favorable devices for next-generation, large-area flexible electronics. In this paper, we demonstrate the excellent material properties of lanthanum-zinc oxide (LaZnO) thin films deposited by spray pyrolysis and their application to TFTs. The threshold voltage of the LaZnO TFTs shifts toward positive gate voltage, and the mobility decreases with increasing lanthanum ratio in ZnO from 0 to 20%. The purification of the LaZnO precursor (P-LaZnO) further improves the device performance. The P-LaZnO TFT exhibits a field-effect mobility of 22.43 cm2 V-1 s-1, zero hysteresis voltage, and negligible threshold voltage VTH shift under positive bias temperature stress. The enhancement in the electrical properties is due to a decrease in grain size, smooth surface roughness, and reduction in the trap density in the LaZnO film. X-ray photoelectron spectroscopy (XPS) results confirm the presence of La in the TFT channel and at/near the interface of the LaZnO and ZrOx gate insulator, leading to fewer interfacial traps. The flexible P-LaZnO TFT fabricated on the polyimide substrate exhibits a mobility of 17.64 cm2 V-1 s-1 and a negligible VTH shift under bias stress. Also, the inverter made of LZO TFTs is working well with a voltage gain of 17.74 (V/V) at 4 V. Therefore, the LaZnO TFT is a promising device for next-generation flexible displays.

High‐Responsivity Graphene/4H‐SiC Ultraviolet Photodetector Based on a Planar Junction Formed by the Dual Modulation of Electric and Light Fields

AbstractUltraviolet (UV) photodetectors have been fabricated on a graphene/4H‐SiC wafer. In this device, the electrical doping in the graphene layer, under the gate, is realized by changing the gate voltage while the optical doping in the graphene layer outside the gate region is realized through the photogenerated carrier injection from SiC, by laser excitation at 325 nm. This kind of dual modulation of optical and electric fields ultimately results in the formation of a planar n–p–n or n–n–n junction in the graphene layer. The photoresponse results demonstrate that the planar n–p–n junction is formed at the negative gate voltage, and facilitates negative photoconductivity. The n–n–n junction is formed at the positive gate voltage and facilitates normal photoconductivity. The maximum responsivity, which is attributable to the high photoconductive gain in the planar n–n–n junction, is 254.1A W−1, at drain‐source voltage of −3 V and gate‐source voltage of 3 V. Based on these results, the estimated lifetime of the electrons in the graphene channel extends greatly to more than four orders of magnitude longer than that in the isolated graphene. The above results prove that this graphene/4H‐SiC combined structure possesses great potential in practical UV‐detection applications.

Numerical Performance of AlGaN/GaN High Electron Mobility TransistorsunderHydrostatic Pressure and Temperature

In this paper, drain-source current, in AlGaN/GaN high electron mobility transistors have been investigated. In order to obtain parameters of exact AlGaN/GaN high electron mobility transistors such as electron density, the wave function, band gap, polarization charge, effective mass and dielectric constant, the hydrostatic pressure and temperature effects are taken into account. It has been found that the drain-source current decreases with increasing temperature and increases with increasing hydrostatic pressure. The increase in temperature is equivalent to a negative virtual gate and an increase in the hydrostatic pressure equivalent to the positive virtual gate voltage. Moreover, the temperature and hydrostatic pressure effective mass dependence in high electron mobility transistor structures are investigated, and it is observed that the increase of hydrostatic pressure decreases the effective mass and the wave function penetrated to quantum barrier AlGaN. The calculated results are in good agreement with existing experimental data.

Post-annealing temperature-dependent electrical properties of thin-film transistors with a ZnO channel and HfOx gate insulator deposited by atomic layer deposition

Electrical properties of an oxide semiconductor thin-film transistor (TFT) with a ZnO channel layer and a HfOx gate insulator, both of which are deposited by atomic layer deposition (ALD), are investigated at varying post-annealing temperatures. The TFTs that are post-annealed at 250 and 300 °C show relative low on/off ratios < 102. They also have a counter-clockwise hysteresis in the transfer curves with slightly reduced threshold voltage upon repeatedly applying a positive gate voltage. However, the transfer curves of the devices post-annealed at 350 °C exhibit the increased on/off ratios > 102 and clockwise hysteresis with a little increased threshold voltage due to electron charging at the trap states in the HfOx/ZnO interface or inside the HfOx gate insulator. The threshold voltage shift, however, is negligible at the gate voltage of +20 V and as low as about 2.2 V at the highest gate voltage of +40 V, which guarantees stable operations of TFTs without significant degradation of electrical performance. The channel mobilities are around 4.0 cm2 V−1 s−1 at this annealing temperature range. The presented results report the dependence of electrical performance such as on/off ratio and electrical instability, possibly caused by electrical charging, on the post-annealing temperature, which requires post-annealing at 350 °C or higher temperatures for stable operations of TFTs with ALD-ZnO and HfOx.

Reliability Concern of 650-V Normally-OFF GaN Devices Under Reverse Freewheeling Stress

This brief first reports the behaviors of three different kinds of 650-V commercial normally- OFF GaN devices under repetitive reverse freewheeling stress, and the mechanisms are illustrated by experiments and mix-mode technology computer-aided design simulations. After the stress, unlike the stable behaviors of the device with ohmic-type metal/p-GaN gate stack and the device with cascode structure, there are degradations on the threshold voltage, the ON-state resistance, and the source-to-drain reverse voltage for the device with Schottky-type metal/p-GaN gate stack. During the freewheeling stress, there is a dynamic positive gate to drain voltage on the devices. Especially, the Schottky-type contact leads to a barrier height at metal/p-GaN junction and makes the p-GaN layer to become floating, which can lock the injected carriers. Worse more, there is a high electric field at the gate contact, which leads to the trapping of injected electrons. Once the stress is removed, more positive gate voltage is needed during the turn-on process to suppress the influences of unreleased electrons; as the results, the electrical parameters shift. Finally, the mix-mode simulation results prove the carrier injection, and the measured segmental shifts of gate leakage current prove the trapping process in p-GaN layer successfully.

Investigation the impact of the gate work-function and biases on the sensing metrics of TFET based biosensors

In this work, we examined the impact of gate work-function and back-gate bias to enhance sensing metrics of a Dielectric Modulated (DM) p-type Tunnel Field Effect Transistor (p-TFET) based biosensor. The sensing metrics, namely Sensitivity (S) and Selectivity (ΔS) are considerably improved by using a lower value of gate work-function and positive back gate voltages. It is shown that by appropriate selection of gate work-function and back gate bias, Band-to-Band Tunneling (BTBT) of carriers is reduced and a significant change in electrical characteristics is observed in a device with an empty cavity. Therefore, the relative change in the drain current due to the presence of biomolecules in the nanogap cavity is maximized. Results indicate a Sensitivity of ∼109 for 3-aminopropyltriethoxysilane (APTES) biomolecule, and Selectivity of ∼102 for APTES concerning Biotin biomolecule in an optimally designed p-TFET biosensor. The impact of location, as well as the charge of biomolecules, are also analyzed in this work. Results showcase the additional degree of freedom through device optimization which facilitates the tunability of sensing metrics for improved biosensor performance.

High Threshold Voltage Normally off Ultra-Thin-Barrier GaN MISHEMT with MOCVD-Regrown Ohmics and Si-Rich LPCVD-SiNx Gate Insulator

A high threshold voltage (VTH) normally off GaN MISHEMTs with a uniform threshold voltage distribution (VTH = 4.25 ± 0.1 V at IDS = 1 μA/mm) were demonstrated by the selective area ohmic regrowth technique together with an Si-rich LPCVD-SiNx gate insulator. In the conventional GaN MOSFET structure, the carriers were induced by the inversion channel at a high positive gate voltage. However, this design sacrifices the channel mobility and reliability because a huge number of carriers are beneath the gate insulator directly during operation. In this study, a 3-nm ultra-thin Al0.25Ga0.75N barrier was adopted to provide a two-dimensional electron gas (2DEG) channel underneath the gate terminal and selective area MOCVD-regrowth layer to improve the ohmic contact resistivity. An Si-rich LPCVD-SiNx gate insulator was employed to absorb trace oxygen contamination on the GaN surface and to improve the insulator/GaN interface quality. Based on the breakdown voltage, current density, and dynamic RON measured results, the proposed LPCVD-MISHEMT provides a potential candidate solution for switching power electronics.

Electric Field Effect on the Reactivity of Solid State Materials: The Case of Single Layer Graphene

AbstractThis manuscript reports the first example of charge‐doping‐induced reactivity enhancement in macroscopic‐sized solid state material. Single layer graphene is supported on a Si wafer that has a 300 nm thick SiO2 layer and is heated photothermally in air to ≈240 °C. Applying both positive and negative pulsed back gate voltages increases the rate of graphene oxidation, as measured by the change of ID/IG ratio using Raman spectroscopy. The fact that both electron and hole doping increase the reactivity argues against electrochemical oxidation and suggests a new mechanism is at play. The enhancement effect increases with the magnitude and the frequency of the square wave back gate voltage. Density functional theory calculations indicate that the activation barriers for O2 insertion into graphene and desorption of CO2 decrease in the presence of an electric field. This study suggests charge doping as a new approach that can modulate the reactivity of solid state materials in real time and compliment chemical‐based catalysis.