Positive Gate Bias Stress Research Articles

Impact of post-deposition annealing on SiO2/SiC interfaces formed by plasma nitridation of the SiC surface and SiO2 deposition

Abstract We examined the impact of post-deposition annealing (PDA) on SiO2/SiC structures formed by plasma nitridation of the SiC surface followed by sputter deposition of SiO2. The interface state density near the conduction band edge of SiC was reduced from about 2×1012 to 1×1011 eV−1cm−2 as the CO2-PDA temperature increased from 1050 to 1250℃. In addition, the sample treated by CO2-PDA exhibited substantially higher immunity against positive gate bias stress than the standard NO nitridation. Our findings indicate that defect passivation by CO2-PDA plays a crucial role in improving the performance and reliability of SiC MOS devices formed by sputter-SiO2 deposition.

Al modification layer method for enhancing InAlZnO transistors

In this work, a surface engineering method is proposed to boost electrical performance and stability of the InAlZnO (IAZO) transistors, of which an Al modification layer is deposited on surface of the IAZO channel layer. Through analysed by transmission electron microscope and X-ray photoelectron spectroscopy, the IAZO thin film with Al modification layer undergoes a reduction reaction to generate more oxygen vacancies. Hall effects measurement further demonstrates that IAZO thin films with Al modification layer exhibit higher carrier concentrations than the ones without Al modification layer. The IAZO transistors with Al modification layer exhibit better performance and stability, including a field-effect mobility of 4.36 cm2 V−1s−1 (an improvement of about three-fold), a small subthreshold swing of 105.23 mV/decade, a high on-to-off current ratio greater than 107, and a threshold voltage shift of less than 0.50 V under positive and negative gate bias stress. Moreover, the IAZO transistors with Al modification layer demonstrate high thermal stability under 400 °C for 120 min in air atmosphere. Based on this method, the IAZO inverters have been implemented with high voltage gain of 87.55 V/V. This surface engineering technology paves the way for application of high-performance oxide transistors for advanced monolithic three-dimensional integration.

Amorphous InZnSnO thin-film-transistors performance enhancement with low-energy Xenon Pulsed-light annealing

The electrical characteristics and stability of amorphous indium-zinc-tin oxide (IZTO) thin-film transistors (TFTs) were significantly improved in this study using low-energy Xenon pulsed-light annealing (PLA). In comparison to conventional furnace annealing (FA), PLA treatment significantly reduced the processing temperature and annealing time. Besides, the defect states are obviously reduced from 1.73×1012 cm-2 to 6.53×1011 cm-2 by PLA treatment, resulting in improved device electrical characteristics and enhanced reliability, including improved carrier mobility from 20.08 to 39.61 cm2/V∙s, threshold voltage from 0.82 to 0.24 V, subthreshold swing (S.S.) from 0.54 to 0.24 V/decade, and the ON/OFF current ratio from 2.32×107 to 7.31×108. In addition, the enhanced stability is observed under both positive gate-bias stress (PGBS) of VGS = 30 V and negative gate-bias stress (NGBS) of VGS = –30 V for a stress duration of 3000 s. The threshold voltage shift (ΔVTH) is reduced from 8.31 V to 1.65 V and from –3.93 V to –1.51 V, respectively. This is the first time low-energy PLA was conducted for IZTO TFT performance improvement.

Enhancing the Stability and Mobility of TFTs via Indium-Tungsten Oxide and Zinc Oxide Engineered Heterojunction Channels Annealed in Oxygen Ambient.

This study demonstrates a significant enhancement in the performance of thin-film transistors (TFTs) in terms of stability and mobility by combining indium-tungsten oxide (IWO) and zinc oxide (ZnO). IWO/ZnO heterojunction structures were fabricated with different channel thickness ratios and annealing environments. The IWO (5 nm)/ZnO (45 nm) TFT, annealed in O2 ambient, exhibited a high mobility of 26.28 cm2/V·s and a maximum drain current of 1.54 μA at a drain voltage of 10 V, outperforming the single-channel ZnO TFT, with values of 3.8 cm2/V·s and 28.08 nA. This mobility enhancement is attributed to the formation of potential wells at the IWO/ZnO junction, resulting in charge accumulation and improved percolation conduction. The engineered heterojunction channel demonstrated superior stability under positive and negative gate bias stresses compared to the single ZnO channel. The analysis of O 1s spectra showed OI, OII, and OIII peaks, confirming the theoretical mechanism. A bias temperature stress test revealed superior charge-trapping time characteristics at temperatures of 25, 55, and 85 °C compared with the single ZnO channel. The proposed IWO/ZnO heterojunction channel overcomes the limitations of the single ZnO channel and presents an attractive approach for developing TFT-based devices having excellent stability and enhanced mobility.

Spin coating high‐k multicomponent (Al,Ti,V,Zr,Hf)Ox films with sub‐nm EOT for MOS‐based electronic devices

AbstractThe facile spin coating fabrication of high‐dielectric‐constant (high‐k) multicomponent (Al,Ti,V,Zr,Hf)Ox films with an equivalent oxide thickness of ≈0.95 nm and the investigation of their thermal stability and dielectric and electrical properties of the resulting advanced metal–oxide–semiconductor (MOS)‐based electronic devices are reported in this study. Various heating conditions, including drying following spin coating, annealing after drying, and forming gas annealing, were investigated to optimize the quality of the films and reduce film defects. The favorable film‐based MOS devices exhibited robust capacitance–voltage (C–V) and current–voltage (I–V) characteristics with a remarkable k value of approximately 62 at 1 kHz. The thermal stability of the films was affirmed through a rapid thermal annealing treatment at 900°C for 5 s and observation of nondegraded C–V and I–V curves. The electrical performance of the resulting MOS field‐effect transistors (MOSFETs), including a threshold voltage of 0.4 V, an on/off ratio of 106, a saturated mobility of 40.1 cm2 V−1 s−1, and a subthreshold swing of 66.7 mV dec−1, was obtained. Moreover, hole‐ and electron‐trapping measurements through negative and positive gate bias stress instabilities, respectively, indicate the reliable performance of our MOSFETs. Our results imply that solution‐based processes are promising for fabricating fundamental semiconductor devices.

Improvement of the electrical properties of amorphous indium-gallium-zinc oxide thin-film transistors by cross-linked CYTOP passivation

In this study, we investigated the effect of a cross-linked CYTOP passivation layer on the electrical properties of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). Cross-linked CYTOP passivation showed a deeper fluorine diffusion depth than CYTOP passivation owing to the chemical reaction between the cross-linking agent and IGZO layer. The cross-linking agent reduces the weakly bonded oxygen in the IGZO layer via a chemical reaction, enhancing fluorine diffusion into the IGZO layer. Therefore, the effect of fluorine on the IGZO layer was enhanced by using cross-linked CYTOP as a passivation layer. The diffused fluorine reduced the defect states by passivating the oxygen-related defects such as oxygen vacancies and weakly bonded oxygen and increased the carrier concentration by replacing metal–oxygen bonds with metal-fluorine bonds. IGZO TFTs with cross-linked CYTOP passivation exhibited a threshold voltage of −0.35 V, saturation mobility of 1.93 cm2/V∙s, and subthreshold swing of 0.53 V/dec. Using a cross-linked passivation layer also improved the reliability under positive gate bias stress. Consequently, a cross-linked CYTOP passivation layer can effectively improve the electrical properties of IGZO TFTs by incorporating fluorine atoms into the IGZO layer.

A Comparative Study on the Degradation Behaviors of Ferroelectric Gate GaN HEMT with PZT and PZT/Al2O3 Gate Stacks.

In this paper, the degradation behaviors of the ferroelectric gate Gallium nitride (GaN) high electron mobility transistor (HEMT) under positive gate bias stress are discussed. Devices with a gate dielectric that consists of pure Pb(Zr,Ti)O3 (PZT) and a composite PZT/Al2O3 bilayer are studied. Two different mechanisms, charge trapping and generation of traps, both contribute to the degradation. We have observed positive threshold voltage shift in both kinds of devices under positive gate bias stress. In the devices with a PZT gate oxide, we have found the degradation is owing to electron trapping in pre-existing oxide traps. However, the degradation is caused by electron trapping in pre-existing oxide traps and the generation of traps for the devices with a composite PZT/Al2O3 gate oxide. Owing to the large difference in dielectric constants between PZT and Al2O3, the strong electric field in the Al2O3 interlayer makes PZT/Al2O3 GaN HEMT easier to degrade. In addition, the ferroelectricity in PZT enhances the electric field in Al2O3 interlayer and leads to more severe degradation. According to this study, it is worth noting that the reliability problem of the ferroelectric gate GaN HEMT may be more severe than the conventional metal-insulator-semiconductor HEMT (MIS-HEMT).

Improved reliability of a-IGZO thin-film transistor under positive gate bias stress by utilizing NH3 plasma treatment

In this paper, the degradation mechanisms of the bottom-gate amorphous InGaZnO thin film transistors (a-IGZO TFTs) under positive gate bias stress (PBS) are investigated. The PBS-induced degradation can be attributed to the electron capture at the interface of the gate insulator and a-IGZO and the generation of oxygen interstitial defects (Oi) in a-IGZO. The oxygen interstitial defect density (NOi) can be calculated by the degradation of SS during recovery after PBS. It is found that the proportion of degradation caused by Oi increases with the increased a-IGZO thickness. By utilizing NH3 plasma treatment, the threshold voltage shift was reduced by >40 % under PBS (@VG = 5 V, t = 1000s). Further analysis shows that NH3 plasma treatment can effectively suppress the electron capture at the interface and the generation of Oi during PBS. Thus, PBS reliability of a-IGZO TFTs is improved by the proposed method.

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Atomically Thin Amorphous Indium-Oxide Semiconductor Film Developed Using a Solution Process for High-Performance Oxide Transistors.

High-performance oxide transistors have recently attracted significant attention for use in various electronic applications, such as displays, sensors, and back-end-of-line transistors. In this study, we demonstrate atomically thin indium-oxide (InOx) semiconductors using a solution process for high-performance thin-film transistors (TFTs). To achieve superior field-effect mobility and switching characteristics in TFTs, the bandgap and thickness of the InOx were tuned by controlling the InOx solution molarity. As a result, a high field-effect mobility and on/off-current ratio of 13.95 cm2 V-1 s-1 and 1.42 × 1010, respectively, were achieved using 3.12-nanometer-thick InOx. Our results showed that the charge transport of optimized InOx with a thickness of 3.12 nm is dominated by percolation conduction due to its low surface roughness and appropriate carrier concentration. Furthermore, the atomically thin InOx TFTs showed superior positive and negative gate bias stress stabilities, which are important in electronic applications. The proposed oxide TFTs could provide an effective means of the fabrication of scalable, high-throughput, and high-performance transistors for next-generation electronic applications.

High-throughput methodology for the realization of high-entropy sub-nm equivalent-oxide-thickness high-dielectric-constant Ba(Ti,Zr,Ta,Hf,Mo)O3 film-based metal-oxide-semiconductor-related devices

This paper reports the use of a high-throughput sputtering technique for the fabrication of high-entropy high-dielectric-constant (high-k) Ba(Ti,Zr,Ta,Hf,Mo)O3 film libraries on Si substrates and sub-nm equivalent-oxide-thickness (EOT) metal−oxide−semiconductor (MOS) devices and metal−oxide−semiconductor field-effect transistors (MOSFETs). The elemental variations and amorphous microstructures are characterized using high-throughput X-ray fluorescence (XRF) and X-ray diffraction, respectively. The film library was patterned into 100 MOS configurations and the films with (Ba + Ti) = 0.41−0.47 at.%, (Mo + Zr) = 0.28−0.34 at.%, and (Ta + Hf) = 0.23−0.3 at.% exhibited favorably high k (325−374) and low tan δ (0.01−0.08) values with an impressive EOT ≈ 0.8−0.94 nm. The resulting MOSFETs after the rapid thermal annealing (RTA) exhibited excellent characteristics: an on/off current ratio of 8 × 106, saturated field-effect mobility of 138.4 cm2 V−1 s−1, a threshold voltage (VT) of 0.03 V, a subthreshold swing of 0.062 V⋅dec−1, and low interfacial defects of approximately 5.6 × 1010 eV cm−2. Small ΔVT and negligible changes in the maximum drain current were observed for the MOSFETs under various positive and negative gate-bias stress conditions before and after the RTA. Our devices outperformed various reported transistors, indicating the potential of the Ba(Ti,Zr,Ta,Hf,Mo)O3 films for use in a gate-first process for advanced gate stack-related devices.

Performance and stability of Al-doped HfGaO thin-film transistors deposited by vapor cooling condensation system

In this work, to study the features of Al atomic ratio in Al2O3-doped HfGaO (referred as AlHfGaO) channel layers of thin-film transistors, the HfGaO and various AlHfGaO films were deposited at approximately 80 K using a vapor cooling condensation system. The oxygen vacancy defects resided in AlHfGaO films and the defect density in the resulting thin-film transistors decreased with an increase of the Al atomic ratio. As defects reduced, threshold voltage and on/off current ratio increased, while threshold voltage offset and subthreshold swing decreased. In terms of the threshold voltage offset, measured by positive gate bias stress and negative gate bias stress methods, as the stability parameter of thin-film transistors, the stability was improved by using a higher Al atomic ratio in the AlHfGaO channel layers due to the suppression of the charge trapping effect.

Gate-Bias-Induced Threshold Voltage Shifts in GaN FATFETs

The threshold voltage (V TH) stability in GaN fat field-effect transistors (FATFETs) with a large channel area of ∼6.2 × 104 μm2 was studied using drain current vs gate voltage (I D–V G) characteristics. Each measurement was found to positively shift the previous I D–V G curve, and V TH eventually saturated with increasing number of measurements. The saturated V TH was ∼0.8 V for measurements in which V G ranged from −10 to 25 V and was ∼8 V for measurements in which the V G ranged from −10 to 40 V. Moreover, the positive gate bias stress increased V TH to 12.3 V. These shifts of V TH can be explained by electron trapping; according to charge-pumping measurements, the traps cannot exist in the oxide or the oxide/p-GaN interface but can exist near the surface region in p-GaN layers in GaN FATFETs. Scanning transmission electron microscopy and electron energy-loss spectroscopy analyses revealed the presence of oxygen within several atomic layers of p-GaN from the oxide/p-GaN interface. This intermixed oxygen might be the origin of the n-type behavior of the p-GaN surface; furthermore, the oxygen is speculated to be related to the traps. Surprisingly, similar incorporated oxygen was observed even in the surface region of as-grown p-GaN layers.

Surface-modified polydimethylsiloxane with soft-plasma as dielectric layer for flexible artificial synaptic transistors

The conductance of field-effect transistors (FETs) can be effectively stimulated by electrical or optical pulses, which could be potentially applied as artificial synapses. The combination of solution processable elastomers with polymer semiconductors has attracted extensive interest in all-polymer flexible synaptic electronics, due to the flexible and light weight property. In this work, a glow-discharge soft-plasma is utilized to treat the widely-used elastomer polydimethylsiloxane (PDMS) layer. Subsequently, the surface energy of PDMS is increased, from the contact angle of 100° to fully spread state and induce high charge trapping density (Δn, about 1.9 × 1012 cm−2 under 525 nm green light irradiation and positive gate-bias stress) on the surface. The PDMS surface are homogenously etched by soft plasma without damaging underneath materials, which can be used as dielectric layer in organic FETs. Thus, prepared organic FETs warrant quick charge transfer dynamics between PDMS surface and semiconductor layer. Upon which, flexible synaptic FETs are demonstrated, corresponding synaptic functions like excitatory postsynaptic current (EPSC), paired pulse facilitation (PPF), short-term plasticity (STP) are all realized. Furthermore, the handwritten digits with an accuracy of 86.2% are realized utilizing prepared synaptic devices.

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination.

In this work, an electrical stability model based on surface potential is presented for amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) under positive-gate-bias stress (PBS) and light stress. In this model, the sub-gap density of states (DOSs) are depicted by exponential band tails and Gaussian deep states within the band gap of a-IGZO. Meanwhile, the surface potential solution is developed with the stretched exponential distribution relationship between the created defects and PBS time, and the Boltzmann distribution relationship between the generated traps and incident photon energy, respectively. The proposed model is verified using both the calculation results and experimental data of a-IGZO TFTs with various distribution of DOSs, and a consistent and accurate expression of the evolution of transfer curves is achieved under PBS and light illumination.

Effect of Gate Bias Stress on the Electrical Characteristics of Ferroelectric Oxide Thin-Film Transistors with Poly(Vinylidenefluoride-Trifluoroethylene).

We investigated the effect of gate bias stress (GBS) on the electrical characteristics of ferroelectric oxide thin-film transistors (FeOxTFTs) with poly(vinylidenefluoride-trifluoroethylene). Generally, conventional oxide thin-film transistors (OxTFTs) with dielectric gate insulators exhibit a small negative shift under negative gate bias stress (NBS) and a large positive shift under positive gate bias stress (PBS) in transfer characteristic curves. In contrast, the FeOxTFTs show a small positive shift and a large negative shift under NBS and PBS, respectively. It was confirmed that sufficient changes in the electrical characteristics are obtained by 10 min NBS and PBS. The changed electrical characteristics such as threshold voltage shift, memory on- and memory off-current were maintained for more than 168 h after NBS and 24 h after PBS. It is deduced that, since the dipole alignment of the ferroelectric layer is maximized during GBS, these changes in electrical properties are caused by the remnant dipole moments still being retained during the gate sweep. The memory on- and memory off-current are controlled by GBS and the best on/off current ratio at 107 was obtained after NBS. By repeatedly alternating NBS and PBS, the electrical characteristics were reversibly changed. Our results provide the scientific and technological basis for the development of stability and performance optimization of FeOxTFTs.

Performance enhancement of solution-processed amorphous WZTO TFT with HAO gate dielectric via power ultrasound technology

In this paper, power ultrasound technology (PUT) is employed to prepare the high-k hafnium-aluminum oxide (HAO) dielectric and thin film transistor (TFT). The continuous propagation of high-intensity ultrasonic waves in the metal oxide precursor solution can improve the dissolution efficiency of the solute and speed up the formation of the HAO precursor solution. The prepared HAO films have a smooth surface roughness of 0.36 nm and high optical transmittance of 85 %. Moreover, HAO films obtain excellent electrical properties with a relative permittivity of 15.9 and a leakage current density of 9.1 × 10−8 A/cm2 at 2 MV/cm as well. Finally, we successfully fabricate TFT with HAO dielectric using PUT, these TFTs exhibit switch characteristics with field effect mobility of 18.7 cm2v−1s−1, threshold voltage (Vth) of −0.47 V, and Vth shift of 0.35 V under positive gate bias stress. The results show that the PUT is a promising method that can remarkably decrease the preparation time of the precursor solution and improve the TFT performance.

Microwave-Irradiated Metal-Oxide Thin-Film Transistors With Recessed Gate Structure and Their Applications in Logic Circuits

The effects of a recessed gate structure on the device performance of sol-gel-based metal-oxide thin-film transistors (oxide-TFTs) consisting of aluminum oxide dielectric and indium-gallium-zinc oxide semiconducting films fabricated through effective microwave irradiation are investigated, as compared with elevated and non-patterned gate structures. Low-voltage operating oxide-TFTs with an optimized recessed gate structure exhibited improved device performance including OFF-state current of approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{11}}$ </tex-math></inline-formula> A and field-effect mobility of 3.4 cm2/V-s in the linear regime, compared with those with elevated (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{9}}$ </tex-math></inline-formula> A and 1.9 cm2/V-s) and non-patterned (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{10}}$ </tex-math></inline-formula> A and 2.8 cm2/V-s) gate structures. Furthermore, the charge transport mechanism responsible for improved device performance and operational stability against prolonged positive and negative gate bias stresses in the oxide-TFTs with the recessed gate structure is investigated through activation energy and velocity distribution that are determined from direct-current and time-domain non-quasi-static transient analyses, respectively. Finally, enhancement-load-type nMOS inverters operating at 5 V are developed for logic circuits, which exhibit a relatively high dc gain of 32.2 in the recessed gate structure, compared with that of 17.1 and 27.1 in the elevated and the non-patterned gate structures, respectively.

Low‐Voltage, High‐Performance, Indium‐Tin‐Zinc‐Oxide Thin‐Film Transistors Based on Dual‐Channel and Anodic‐Oxide

AbstractOxide semiconductor thin‐film transistors (TFTs) with low‐voltage operation, excellent device performance, and bias stability are highly desirable for portable and wearable electronics. Here, the development of low‐voltage indium‐tin‐zinc‐oxide (ITZO) TFTs with excellent device performance and bias stability based on a dual‐channel layer and an anodic‐oxide dielectric layer are reported. An ultra‐thin anodic AlxOy film as a gate dielectric layer is prepared using an anodization process. The dual‐channel layer consists of an oxygen‐uncompensated channel layer and an oxygen‐compensated capping layer. It is confirmed that the dual‐channel structure is effective for enhancing device performance and bias stability in comparison with the single‐channel structure. As a result, the dual‐channel ITZO TFT gated with anodic AlxOy exhibits an effective saturation mobility of 12.56 cm2 Vs−1, a threshold voltage of 0.28 V, a subthreshold swing of 76 mV dec−1, a low‐voltage operation of 1 V, and good operational stability (threshold voltage shift (ΔVTH) &lt; −0.03 V under a negative gate bias stress and ΔVTH &lt; 0.15 under positive gate bias stress of 3600 s). The work shows that the ITZO TFTs, based on a dual‐channel layer and an anodic‐oxide gate dielectric layer, have great potential for low‐power, portable, and wearable electronics.

Effect of Back-Channel Surface on Reliability of Solution-Processed In0.51Ga0.15Zn0.34O Thin-Film Transistors with Thin Active Layer.

We have investigated the degradation mechanism of solution-processed indium-gallium-zinc-oxide (IGZO) thin-film transistors. The threshold voltage shift (ΔVth) followed a linear function under negative gate bias stress (NBS), while it showed a stretched-exponential behavior under positive gate bias stress. The slope of ΔVth for stress time was rarely changed with variations below 0.3 mV/s. The thickness of the fabricated IGZO layer (In0.51Ga0.15Zn0.34O) was approximately 10 nm. The Debye length (LD) was larger than IGZO thickness (tIGZO) due to the fully depleted active layer under NBS. Therefore, the degradation phenomenon under NBS was related to the adsorption at back-channel surface. The back-channel surface could be affected by the gate bias under NBS, and the molecules adsorbed at the IGZO layer were positively charged and induced extra electrons by NBS. We verified that the number of positively charged adsorbates had a proportional relationship with the ΔVth based on the two-dimensional technology computer-aided design (TCAD) simulation. Furthermore, we investigated the degradation phenomenon with the ΔVth equation regarding the adsorbates, and the result confirmed that the adsorption process could cause the linear ΔVth. We experimentally confirmed the effect of back-channel surface by comparing the ΔVth between different atmospheric conditions and LD. Consequently, the reaction at the back-channel surface should be considered to develop the metal-oxide semiconductor devices.