Positive Bias Temperature Instability Effects Research Articles

Investigating the Current Collapse Mechanisms of p-GaN Gate HEMTs by Different Passivation Dielectrics

In this letter, the dynamic R on degradation mechanisms of the p-GaN gate HEMTs induced by off -state stress are investigated with different passivation dielectrics AlON and SiN. The degradation mechanisms are twofold, including V TH shift and surface trapping in the gate-to-drain access region, whose impacts are successfully distinguished. Surface trapping by SiN passivation is evidently proved to be the dominant factor that can almost induce a full current collapse. The V TH positive shift diminishes the drain current by shrinking the overdrive V GS, which however, can be compensated by a higher V GS overdrive in applications. SiN passivation can effectively suppress the positive bias temperature instability effect, probably by passivating the p-GaN fast traps with hydrogen during passivation. Last, the transient measurements unveil that both the surface trapping and V TH shift have a very slow recovery process.

Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications

In this paper, silicon-based Asymmetric-Elevated-Source-Drain Tunnel Field-Effect Transistor (AESD-TFET), for gate lengths (LGs), viz. 70, 45, 32, 22, and 13 nm, is investigated for the first time to find its suitability in sub-400-mV low-stand-by-power (LSTP) digital operation, followed by finding its reliability and stability against the adverse effect of Positive Bias Temperature Instability (PBTI) for LG = 13 nm corresponding to the (recent) state-of-the-art technology node for the “More Moore” options in realizing LSTP digital functions. The whole work is executed with the help of 2-D numerical methods, via a model-calibration against a couple of experimental works on Elevated-Drain TFET (ED-TFET) and Elevated-Source TFET (ES-TFET), respectively, followed by a comparison of performances between the three, in terms of threshold voltage (VT), average subthreshold swing (SSavg), OFF-state current (IOFF), ION/IOFF ratio, OFF-state leakage power, and drain-induced barrier lowering (DIBL), and then a measurement of shifts in VT, IOFF, ION/IOFF, and SSavg for different PBTI stress conditions for temperature ≥ 300 K. For the optimum value of LG (i.e. 13 nm), a reduction of 56% and 66% in DIBL, a drop of 15.84% and 45.74% in SSavg, a reduction of about 1 decade and 3 decades in IOFF, and an improvement of nearly 1 decade and 2 decades in ION/IOFF have been obtained for the AESD-TFET against the ES- and ED-TFET devices, respectively. The same has also been found to show maximum stability against the PBTI effect under the two-temperature conditions (i.e. 300 K and 398 K) in terms of IOFF, ION/IOFF and SSavg with the lowest possible shifts in VT (∼ 0%) and SSavg (9%), besides maintaining the most excellent absolute values of the aforesaid parameters.

Interface Passivation Strategy for Ge pMOSFET From a TID Perspective

The interface quality between the gate dielectric and germanium (Ge) channel plays a crucial role for Ge MOSFETs. The impact of different interface passivation techniques on the total ionizing dose (TID) effect of Ge pMOSFET with enclosed-layout and Al2O3/TiN gate-stack is experimentally investigated under different bias conditions. The N-passivation and O-passivation of Ge pMOSFETs are realized by nitrogen-plasma-passivation (NPP) and rapid-thermal-oxidation, respectively. Negative threshold voltage ( $V_{\text {th}}$ ) shift and positive $V_{\text {th}}$ shift are observed for devices irradiated under on-state and TG-state, respectively, which are partially due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) stresses. The NBTI and PBTI effects are evaluated to obtain “pure” $V_{\text {th}}$ shifts induced by TID irradiation. The O-passivated Ge pMOSFETs show larger pure radiation-induced $V_{\text {th}}$ shifts than N-passivated devices, which is attributed to less irradiation-induced border trap density in the N-based interfacial layer (IL) than the O-based IL. Therefore, N-based IL is more suitable for Ge MOSFET than the O-based IL from a perspective of radiation hardness. The results may provide interface material-design guideline for radiation-hardened and high-performance Ge MOSFET fabrication.

Comprehensive Investigation of Multitraps-Induced Degradation in HfO2-Based nmosfets With Interfacial Layer by Three-Dimensional KMC Method

This paper investigates trap-induced degradation in nmosfets with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric by three-dimensional Kinetic Monte Carlo method. Multiple microscopic mechanisms including trapping/detrapping, traps coupling, and trap generation/recombination are considered in simulation. The impacts of interfacial layer (IL) SiOx on positive bias temperature instability (PBTI) and trap-assisted tunneling (TAT) are comprehensively investigated. PBTI characteristics show the variations of power laws with time, and power laws are greatly affected by stress condition, trap density, and dielectric thickness. Therefore, impressionable power laws make much complexion in lifetime prediction. Meanwhile, it is found that IL markedly reduces PBTI effects. Significantly, TAT currents of fresh devices increase with IL thickening in the same effective oxide thickness (EOT), whereas TAT currents after stress decrease with IL thickening in a specific range. It can be concluded that the IL in the proper range of thickness can effectively suppress PBTI and TAT currents.

Analysis of Stability Degradation of SRAMs Using a Physics-Based PBTI Model

For the static random access memories (SRAMs) with high-k/metal gate transistors, positive bias temperature instability (PBTI)-induced stability degradation can be significant. In this letter, we analyze the temporal variations of the READ/WRITE operations and static noise margin of a conventional 6T-SRAM cell using a physics-based PBTI model. We show that the dependence of BTI effects on intrinsic variations and the design parameters of SRAM are significant A 10 mV increase in intrinsic variations can lead to double the BTI-induced read failure rate. Furthermore, SRAM is more sensitive to PBTI effects as compared with negative bias temperature instability These results validate that stochastic modeling of PBTI is required for reliable SRAM design.

Impact of Lanthanum on Positive-Bias Temperature Instability – Insight from First-Principles Simulation

The impact of lanthanum (La) on positive-bias temperature instability (PBTI) is examined via first-principles simulation of the electronic properties of the oxygen vacancy (V O) and vacancy-interstitial (V O-Oi) paired defects in the hafnium dioxide (HfO2) gate dielectric. The purpose is to understand the recently reported retardation of PBTI recovery in La-doped HfO2 gate n-MOSFETs, indicating that La doping has made part of the stress induced electron trapping become more permanent. Simulation results show that the formation energy of both defects are significantly decreased by La doping, implying that these defects are more readily formed in the La-doped HfO2 as compared to the undoped counterpart. The higher density of V O’s should increase PBTI effect, contrary to the experimental observation of a reduced PBTI effect. The discrepancy may be reconciled by the smaller gate current in the La-doped n-MOSFET, believed to be due to the larger tunneling barrier that results from La dipoles at the HfO2/SiO x interface. With a smaller gate current, electron trapping – the main mechanism of PBTI – is correspondingly reduced. But the trap state of V O in the La-doped HfO2 remains as shallow as that in the undoped counterpart and could not account for the reduction in the PBTI recovery observed experimentally. On the other hand, the trap state of the V O-Oi defect is found to be much deeper, and the greater ease of its formation in the La-doped HfO2 could explain the reduced PBTI recovery observed experimentally.

Impact Analysis of NBTI/PBTI on SRAM VMINand Design Techniques for Improved SRAM VMIN

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM VMIN, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM VMIN. Two different types of SRAM VMIN (SNM-limited VMIN and time-limited VMIN) are explained. Simulation results show that SNM-limited VMIN is more sensitive to NBTI while time-limited VMIN is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the VMIN degradation induced by NBTI/PBTI.

Reliability of thin ZrO 2 gate dielectric layers

In this work we examine the positive bias temperature instability (PBTI) and stress induced leakage current (SILC) reliability of nFET devices with thin (2.5 nm) ZrO 2 gate dielectric layers. nFET devices show anomalous PBTI behavior in the form of a negative threshold voltage ( V t ) shift during positive bias stress with little temperature dependence and it is not ‘frozen out’ at lower temperatures, indicating a single non-diffusion based mechanism. Correlations between the PBTI and the stress induced leakage current (SILC) suggest that the PBTI effect originates from trapping into empty defects which are initially detected as SILC and located just below the silicon conduction band. These defects also appear to be linked to the time dependent dielectric breakdown behavior.

Positive Bias Temperature Instability Effects in nMOSFETs With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks

The positive bias temperature instability (PBTI) and the stress-induced leakage current (SILC) effects are thoroughly examined in nFETs with SiO2/HfO2/TiN dual-layer gate stacks under a wide range of bias and temperature stress conditions. Experimental evidence of the SILC increase with time is obtained suggesting the activation of a trap generation mechanism. Threshold voltage (V T) instability is found to be the result of a complicated interplay of two separate mechanisms; filling of preexisting electron traps versus trap generation each one dominating at different stress condition regimes. Furthermore, V T instability relaxation experiments, undertaken at judiciously chosen conditions, show that the preexisting and stress-induced traps exhibit similar detrapping kinetics indicating that both types of traps may have similar characteristics. Finally, it is shown that the role of the SILC effect (and the associated trap generation component) on V T instability is process dependent and that SILC reduction is accompanied by enhancement of the PBTI device lifetime.

Positive bias temperature instability effects of Hf-based nMOSFETs with various nitrogen and silicon profiles

Positive bias temperature instability (PBTI) effects of HfO/sub 2/-based nMOSFETs with various nitrogen profiles in HfO/sub 2/ were investigated. The nitrogen profile was modulated by an inserting Si layer (/spl sim/6/spl Aring/) into hafnium oxynitride gate dielectrics. The Si layer is used to trap nitrogen and to suppress nitrogen out-diffusion during subsequent anneals. Compared to control HfO/sub x/N/sub y/ without Si insertion, the Si-inserted HfO/sub x/N/sub y/ samples exhibited reduced PBTI degradation, especially if the Si layer was placed further from the Si interface. The improvement can be attributed to the reduction of oxide bulk trapped as well as reduced interface trapped charge generation resulting from compensation effect of inserted Si layer.