Positive Bias Stress Research Articles

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination.

In this work, an electrical stability model based on surface potential is presented for amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) under positive-gate-bias stress (PBS) and light stress. In this model, the sub-gap density of states (DOSs) are depicted by exponential band tails and Gaussian deep states within the band gap of a-IGZO. Meanwhile, the surface potential solution is developed with the stretched exponential distribution relationship between the created defects and PBS time, and the Boltzmann distribution relationship between the generated traps and incident photon energy, respectively. The proposed model is verified using both the calculation results and experimental data of a-IGZO TFTs with various distribution of DOSs, and a consistent and accurate expression of the evolution of transfer curves is achieved under PBS and light illumination.

Ultra-thin gate insulator of atomic-layer-deposited AlO x and HfO x for amorphous InGaZnO thin-film transistors

To strengthen the downscaling potential of top-gate amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), the ultra-thin gate insulator (GI) was comparatively implemented using the atomic-layer-deposited (ALD) AlO x and HfO x . Both kinds of high-k GIs exhibit good insulating properties even with the physical thickness thinning to 4 nm. Compared to the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs with 4 nm AlO x GI, the 4 nm HfO x enables a larger GI capacitance, while the HfO x -gated TFT suffers higher gate leakage current and poorer subthreshold slope, respectively originating from the inherently small band offset and the highly defective interface between a-IGZO and HfO x . Such imperfect a-IGZO/HfO x interface further causes noticeable positive bias stress instability. Both ALD AlO x and HfO x were found to react with the underneath a-IGZO channel to generate the interface defects, such as metal interstitials and oxygen vacancies, while the ALD process of HfO x gives rise to a more severe reduction of a-IGZO. Moreover, when such a defective interface is covered by the top gate, it cannot be readily restored using the conventional oxidizing post-treatments and thus desires the reduction-resistant pre-treatments of AOSs.

30.3: Impact of Top Gate Insulator Deposition Temperature on Electrical Performance of Dual‐Gate a‐InZnO TFTs

The electrical characteristics and stability of dual‐gate amorphous InZnO thin film transistors (a‐IZO TFTs) with top gate insulators (TGIs) deposited under different conditions were investigated. It is found that the TFT with 150°C SiO2 as TGI has higher mobility, while TFT with 300°C SiO2 as TGI has lower off‐state leakage current and better stability under bias stress. Experimental results show that the TFT with stacked TGI deposited at 150°C first and then 300°C can combine the merit of the 150°C SiO2 and 300°C SiO2, achieving high saturation mobility (23.9 cm2/V·s), low off‐state leakage current (10‐14 ~10‐12 A) and also good stability under negative bias stress (NBS) and positive bias stress (PBS) of 3600 s @30 V, with only negative drift of 0.02 V and 0.15 V, respectively. Moreover, it also performs well under negative bias temperature illumination stress (NBTIS) and positive bias temperature illumination stress (PBTIS).

9.2: Mechanism of H2O‐induced Instability of Self‐Aligned Top‐Gate Amorphous InGaZnO TFTs

The influence of H2O on self‐aligned top‐gate (SATG) a‐ InGaZnO thin‐film transistor (TFT) was systematically investigated by performing the high‐temperature high‐humidity (HTHH) test (50 °C, 80% RH). Though initial electrical characteristics were well maintained, the stability under positive bias stress (PBS) was considerably deteriorated, including an abnormal negative Vth shift, degraded SS, and increased off current. The mechanism of H2O‐induced instability was proposed to be the dissociation of H2O molecules and the migration of hydrogen (H) atoms into the a‐IGZO channel. The hydrogen diffusion and doping effects in SATG a‐IGZO TFTs were further proved by SiNx‐passivated TFTs with regulated H content in SiNx layers.

9.1: Effect of Nitrogen Doping Content on Electrical Properties and Stability of a‐IGZO TFT

To improve the electrical properties and stability of thin‐film transistor (TFT) based on the indium gallium zinc oxide (IGZO) channel, the effect of nitrogen‐doping content on the electrical properties of IGZO films and the IGZO TFT were evaluated. It is found that the mobility and carrier concentration of IGZO films gradually decreases ( μ from 18.11 to 11.25 cm2/ V.s, n from 1.76×107 to 4.38×107 cm‐3 ) with the increase of N2 flow content (0‐8sccm). N‐doping can evidently improve the positive bias stress(PBS) stability of IGZO TFT. Typically, the low‐content N‐doping (1 sccm) can significantly boost the stability of IGZO:N TFT (ΔVth = 3.3 V vs ΔVth=9.54 V for the undoped counterpart), while the electrical properties is at almost no degradation with the mobility and on‐off current ratio (Ion/Ioff)as high as 16.59 cm2 /V.s and 3.55×107, and the sub‐threshold swing (SS) and threshold voltage (Vth) as low as 0.32 V/dec and 1.49 V, respectively. These outstanding reliability performance indicates that the N‐doping with appropriate low‐content is a facile and economical way to improve the electrical properties and stability of IGZO TFT.

Charge Trapping and Emission Properties in CAAC-IGZO Transistor: A First-Principles Calculations.

The c-axis aligned crystalline indium-gallium-zinc-oxide field-effect transistor (CAAC-IGZO FET), exhibiting an extremely low off-state leakage current (~10-22 A/μm), has promised to be an ideal candidate for Dynamic Random Access Memory (DRAM) applications. However, the instabilities leaded by the drift of the threshold voltage in various stress seriously affect the device application. To better develop high performance CAAC-IGZO FET for DRAM applications, it's essential to uncover the deep physical process of charge transport mechanism in CAAC-IGZO FET. In this work, by combining the first-principles calculations and nonradiative multiphonon theory, the charge trapping and emission properties in CAAC-IGZO FET have been systematically investigated. It is found that under positive bias stress, hydrogen interstitial in Al2O3 gate dielectric is probable effective electron trap center, which has the transition level (ε (+1/-1) = 0.52 eV) above Fermi level. But it has a high capture barrier about 1.4 eV and low capture rate. Under negative bias stress, oxygen vacancy in Al2O3 gate dielectric and CAAC-IGZO active layer are probable effective electron emission centers whose transition level ε (+2/0) distributed at -0.73~-0.98 eV and 0.69 eV below Fermi level. They have a relatively low emission barrier of about 0.5 eV and 0.25 eV and high emission rate. To overcome the instability in CAAC-IGZO FET, some approaches can be taken to control the hydrogen concentration in Al2O3 dielectric layer and the concentration of the oxygen vacancy. This work can help to understand the mechanisms of instability of CAAC-IGZO transistor caused by the charge capture/emission process.

Effect of Titanium Cation Doping on the Performance of In2O3 Thin Film Transistors Grown via Atomic Layer Deposition

Indium oxide semiconductors, as one of the channel materials for thin film transistors (TFTs), have been extensively studied. However, the high carrier concentration and excess oxygen defects of intrinsic In2O3 can cause the devices to fail to work properly. We overcame this hurdle by incorporating the titanium cation (Ti4+) into In2O3 via atomic layer deposition (ALD). The InTiOx TFTs with an In:Ti atomic ratio of 15:1 demonstrated excellent electrical and optical properties, such as a lower threshold voltage (Vth) of 0.17 V, a lower subthreshold swing (SS) of 0.13 V/dec., a higher Ion/Ioff ratio of 107, and a transmittance greater than 90% in the visible region. With the doping ratio increasing from 20:1 to 10:1, the mobility decreased from 9.38 to 1.26 cm2/Vs. The threshold voltage shift (ΔVth) of InTiO (15:1) under 5 V positive bias stress (PBS) for 900 s is 0.93 V, which is less than other devices. The improvement in stability with increasing Ti4+ concentrations is attributed to the reduction of oxygen defects. Therefore, these InTiO (15:1) TFTs with excellent performance show great potential for future applications in transparent electronic devices.

Effect of Gate Bias Stress on the Electrical Characteristics of Ferroelectric Oxide Thin-Film Transistors with Poly(Vinylidenefluoride-Trifluoroethylene).

We investigated the effect of gate bias stress (GBS) on the electrical characteristics of ferroelectric oxide thin-film transistors (FeOxTFTs) with poly(vinylidenefluoride-trifluoroethylene). Generally, conventional oxide thin-film transistors (OxTFTs) with dielectric gate insulators exhibit a small negative shift under negative gate bias stress (NBS) and a large positive shift under positive gate bias stress (PBS) in transfer characteristic curves. In contrast, the FeOxTFTs show a small positive shift and a large negative shift under NBS and PBS, respectively. It was confirmed that sufficient changes in the electrical characteristics are obtained by 10 min NBS and PBS. The changed electrical characteristics such as threshold voltage shift, memory on- and memory off-current were maintained for more than 168 h after NBS and 24 h after PBS. It is deduced that, since the dipole alignment of the ferroelectric layer is maximized during GBS, these changes in electrical properties are caused by the remnant dipole moments still being retained during the gate sweep. The memory on- and memory off-current are controlled by GBS and the best on/off current ratio at 107 was obtained after NBS. By repeatedly alternating NBS and PBS, the electrical characteristics were reversibly changed. Our results provide the scientific and technological basis for the development of stability and performance optimization of FeOxTFTs.

Performance enhancement of solution-processed amorphous WZTO TFT with HAO gate dielectric via power ultrasound technology

In this paper, power ultrasound technology (PUT) is employed to prepare the high-k hafnium-aluminum oxide (HAO) dielectric and thin film transistor (TFT). The continuous propagation of high-intensity ultrasonic waves in the metal oxide precursor solution can improve the dissolution efficiency of the solute and speed up the formation of the HAO precursor solution. The prepared HAO films have a smooth surface roughness of 0.36 nm and high optical transmittance of 85 %. Moreover, HAO films obtain excellent electrical properties with a relative permittivity of 15.9 and a leakage current density of 9.1 × 10−8 A/cm2 at 2 MV/cm as well. Finally, we successfully fabricate TFT with HAO dielectric using PUT, these TFTs exhibit switch characteristics with field effect mobility of 18.7 cm2v−1s−1, threshold voltage (Vth) of −0.47 V, and Vth shift of 0.35 V under positive gate bias stress. The results show that the PUT is a promising method that can remarkably decrease the preparation time of the precursor solution and improve the TFT performance.

All-Water-Driven High-k HfO2 Gate Dielectrics and Applications in Thin Film Transistors.

In this article, we used a simple, non-toxic, environmentally friendly, water-driven route to fabricate the gate dielectric on the Si substrate and successfully integrate the In2O3/HfO2 thin film transistor (TFT). All the electrical properties of In2O3 based on HfO2 were systematically analyzed. The In2O3/HfO2 device exhibits the best electrical performance at an optimized annealing temperature of 500 °C, including a high µFE of 9 cm2 V-1 s-1, a high ION/IOFF of 105, a low threshold voltage of 1.1 V, and a low sub-threshold of 0.31 V dec-1. Finally, test the stability of the bias under positive bias stress (PBS) and negative bias stress (NBS) with threshold shifts (VTH) of 0.35 and 0.13 V while these optimized properties are achieved at a small operating voltage of 2 V. All experimental results demonstrate the potential application of aqueous solution technology for future low-cost, energy-efficient, large-scale, and high-performance electronics.

Turn-around of threshold voltage shift in amorphous InGaZnO TFT under positive bias illumination stress

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) have attracted significant attention in display devices and 3D-stacked dynamic random-access memory (DRAM) devices. They have superior advantages, while they have much remained to be studied such as threshold voltage (VT) instability. We investigated the transfer characteristics of a-IGZO TFTs under positive bias stress (PBS) and positive bias illumination stress (PBIS). The behaviors of VT shift under PBS and PBIS differed due to illumination. The direction of the VT shift depended on the illumination condition (on or off), including the turn-around of the VT shift under PBIS. The two mechanisms of ionized oxygen vacancies and trapped electrons competed, and one mechanism became dominant under PBS and PBIS. The dominant mechanism determined the direction of the VT shift; turn-around occurred if the dominant mechanism changed. In addition, the subthreshold swing and field-effect mobility consistently described the mechanisms using the corresponding energy band diagrams. Understanding the behavior of the VT shift under various stress conditions provides insights into the instability of a-IGZO TFTs.

A-InGaZnO Thin-Film Transistors With Novel Atomic Layer-Deposited HfO2 Gate Insulator Using Two Types of Reactant Gases

Plasma-enhanced chemical vapor deposition is often utilized to fabricate amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with mobility of approximately 7 cm2/( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> ) using a SiOx gate insulator. For use in high-resolution organic light-emitting diode displays, this value must be markedly improved. Therefore, we used various reactants to create a HfO2 bilayer via atomic layer deposition (ALD) and examined the electrical properties of IGZO TFTs, such as their mobility and subthreshold swing (SS). By adjusting the thickness of HfO2 with H2O reactant gas, the amount of hydrogen that diffused into the IGZO channel was controlled. The IGZO TFT with a specific HfO2 bilayer gate insulator exhibited high saturation mobility of 16.75 cm2/( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> ) and an improved SS of 159 mV/dec compared to a conventional device with a HfO2 gate insulator formed using only O3 reactant gas. Furthermore, the fabricated HfO2 bilayer devices presented excellent reliability under positive bias stress and were more robust against the short-channel effect. Thus, based on the findings of this study, to improve the electrical properties of a-IGZO TFTs, the ALD process is suggested to be used to deposit a high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> gate insulator.

Electrical Performance Enhancement and Low-Frequency Noise Estimation of In2O3-Based Thin Film Transistor Based on Doping Engineering

In this work, solution-derived InErO thin films were deposited to act as the channel layers of thin film transistors (TFTs). The effect of Er doping content on the morphology, oxygen defects, optical properties of indium oxide (In2O3) films, and electrical performance of InErO/Al2O3 TFTs was systematically investigated. Based on experimental results, it can be inferred that InErO-TFTs with 5% Er doping content has demonstrated improved electrical performance, including field effect mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}$ </tex-math></inline-formula> ) of 17.55 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{2}}\,\,\cdot \,\,\text{V}^{-{1}}\,\,\cdot \,\,\text{s}^{-{1}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text{ON}}/{I} _{\text{OFF}}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.70\times 10^{{7}}$ </tex-math></inline-formula> , a subthreshold swing (SS) of 0.16 V/dec and threshold voltage shift of 0.10 and 0.09 V under positive bias stress (PBS) and negative bias stress (NBS) for 1800 s, respectively. The illumination NBS (NBIS) measurements have indicated the degraded device stability by reducing the light wavelength, which can be due to the ionization of oxygen vacancies. Low-frequency noise (LFN) characterizations on devices have shown that the interfacial density of states of In2O3-based TFTs decreases after Er doping. To demonstrate the potential applications of InErO-TFTs in logic circuits, a resistor-loaded unipolar inverter based on InErO/Al2O3 has been integrated, demonstrating good dynamic response behavior and high gain of 10. These results have indicated the great potential of solution-driven InErO-based TFTs for future applications in low-cost and high-performance electronics.

Microwave-Irradiated Metal-Oxide Thin-Film Transistors With Recessed Gate Structure and Their Applications in Logic Circuits

The effects of a recessed gate structure on the device performance of sol-gel-based metal-oxide thin-film transistors (oxide-TFTs) consisting of aluminum oxide dielectric and indium-gallium-zinc oxide semiconducting films fabricated through effective microwave irradiation are investigated, as compared with elevated and non-patterned gate structures. Low-voltage operating oxide-TFTs with an optimized recessed gate structure exhibited improved device performance including OFF-state current of approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{11}}$ </tex-math></inline-formula> A and field-effect mobility of 3.4 cm2/V-s in the linear regime, compared with those with elevated (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{9}}$ </tex-math></inline-formula> A and 1.9 cm2/V-s) and non-patterned (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{10}}$ </tex-math></inline-formula> A and 2.8 cm2/V-s) gate structures. Furthermore, the charge transport mechanism responsible for improved device performance and operational stability against prolonged positive and negative gate bias stresses in the oxide-TFTs with the recessed gate structure is investigated through activation energy and velocity distribution that are determined from direct-current and time-domain non-quasi-static transient analyses, respectively. Finally, enhancement-load-type nMOS inverters operating at 5 V are developed for logic circuits, which exhibit a relatively high dc gain of 32.2 in the recessed gate structure, compared with that of 17.1 and 27.1 in the elevated and the non-patterned gate structures, respectively.

Low‐Voltage, High‐Performance, Indium‐Tin‐Zinc‐Oxide Thin‐Film Transistors Based on Dual‐Channel and Anodic‐Oxide

AbstractOxide semiconductor thin‐film transistors (TFTs) with low‐voltage operation, excellent device performance, and bias stability are highly desirable for portable and wearable electronics. Here, the development of low‐voltage indium‐tin‐zinc‐oxide (ITZO) TFTs with excellent device performance and bias stability based on a dual‐channel layer and an anodic‐oxide dielectric layer are reported. An ultra‐thin anodic AlxOy film as a gate dielectric layer is prepared using an anodization process. The dual‐channel layer consists of an oxygen‐uncompensated channel layer and an oxygen‐compensated capping layer. It is confirmed that the dual‐channel structure is effective for enhancing device performance and bias stability in comparison with the single‐channel structure. As a result, the dual‐channel ITZO TFT gated with anodic AlxOy exhibits an effective saturation mobility of 12.56 cm2 Vs−1, a threshold voltage of 0.28 V, a subthreshold swing of 76 mV dec−1, a low‐voltage operation of 1 V, and good operational stability (threshold voltage shift (ΔVTH) &lt; −0.03 V under a negative gate bias stress and ΔVTH &lt; 0.15 under positive gate bias stress of 3600 s). The work shows that the ITZO TFTs, based on a dual‐channel layer and an anodic‐oxide gate dielectric layer, have great potential for low‐power, portable, and wearable electronics.

Low-temperature crystallization of indium oxide thin films with a photoactivable additive

In this study, we report a simple route to the low-temperature crystallization of solution-processed indium oxide thin films by introducing ammonium nitrate in the sol–gel metal oxide precursor solution as photoactivable additive and applying deep ultraviolet (DUV) irradiation onto the as-spun oxide films in an inert atmosphere. Thermal and structural analyses revealed that the initial temperatures for condensation and crystallization were reduced down to 130 and 200 °C, respectively, by the in situ generation of reactive chemical species enabled by DUV-assisted nitrate photolysis. Furthermore, transmission electron microscopy confirmed that the degree of indium oxide film crystallinity was gradually enhanced as the amount of nitrate in the precursor solution was increased. Finally, electrical characterizations showed that carrier mobility, threshold voltage, subthreshold swing, and threshold voltage shift under the positive bias stress of sol–gel indium oxide thin-film transistors were improved from 0.21 to 5.03 cm2/V s, from 4.18 to 1.64 V, from 1.33 to 0.72 V/dec, and from 6.44 to 4.04 V, respectively, by combining ammonium nitrate and DUV photoactivation.

Effect of Back-Channel Surface on Reliability of Solution-Processed In0.51Ga0.15Zn0.34O Thin-Film Transistors with Thin Active Layer.

We have investigated the degradation mechanism of solution-processed indium-gallium-zinc-oxide (IGZO) thin-film transistors. The threshold voltage shift (ΔVth) followed a linear function under negative gate bias stress (NBS), while it showed a stretched-exponential behavior under positive gate bias stress. The slope of ΔVth for stress time was rarely changed with variations below 0.3 mV/s. The thickness of the fabricated IGZO layer (In0.51Ga0.15Zn0.34O) was approximately 10 nm. The Debye length (LD) was larger than IGZO thickness (tIGZO) due to the fully depleted active layer under NBS. Therefore, the degradation phenomenon under NBS was related to the adsorption at back-channel surface. The back-channel surface could be affected by the gate bias under NBS, and the molecules adsorbed at the IGZO layer were positively charged and induced extra electrons by NBS. We verified that the number of positively charged adsorbates had a proportional relationship with the ΔVth based on the two-dimensional technology computer-aided design (TCAD) simulation. Furthermore, we investigated the degradation phenomenon with the ΔVth equation regarding the adsorbates, and the result confirmed that the adsorption process could cause the linear ΔVth. We experimentally confirmed the effect of back-channel surface by comparing the ΔVth between different atmospheric conditions and LD. Consequently, the reaction at the back-channel surface should be considered to develop the metal-oxide semiconductor devices.

Robustness of Passivated ALD Zinc Tin Oxide TFTs to Aging and Bias Stress

Thin-film electronics fabricated with amorphous oxide semiconductors (AOS) are being studied for beyond-display technologies because of their superior electron transport. To widen the commercial applications, robust devices fabricated using scalable deposition techniques are required. Here, we fabricate bottom-gate, top contact thin-film transistors (TFTs) using zinc tin oxide, an AOS deposited by atomic layer deposition (ALD), and study robustness to aging and bias stress for devices stored in a dark air ambient with and without Al2O3 passivation. All samples exhibit excellent mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}$ </tex-math></inline-formula> ) and subthreshold swing (SS) robustness to aging. Most of the device aging occurs within the first 25 days, after which the performance stabilizes. Changes due to positive bias stress, which are dominated by interactions with ambient molecules, are greatly reduced by passivation. Passivation, however, results in an increase in contact resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{C}$ </tex-math></inline-formula> ), SS, and negative bias illumination stress (NBIS) instability. The increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{C}$ </tex-math></inline-formula> is attributed to the diffusion of oxygen vacancies that occurs during the passivation process, while the increase in SS and NBIS instability is attributed to subgap interface defects. The experimental results are compared to Silvaco ATLAS simulations to confirm the proposed physical mechanisms and allow quantification of the associated defects and non-idealities.

High-performance a-ITZO TFTs with high bias stability enabled by self-aligned passivation using a-GaOx

Maintaining gate bias stability under negative bias stress (NBS) and positive bias stress (PBS) is a long-standing issue in amorphous oxide semiconductor thin-film transistors (TFTs). The passivation of the channel layer is crucial for improving device stability. We show that amorphous gallium oxide, which possesses appropriate energy levels (lower electron affinity and higher ionization potential) for indium–tin–zinc oxide (ITZO) TFTs, can be etched selectively by tetramethyl ammonium hydroxide-containing developers that enable self-alignment passivation, such as easy contact hole formation during the drain and source lithography processes. The self-aligned passivation process led to a-ITZO TFTs with high mobility (&amp;gt;50 cm2 V−1 s−1) and low subthreshold swing (&amp;lt;90 mV/dec). The threshold voltage shifts under NBS and PBS using a bias gate voltage of ±20 V for 1 h were −0.09 and 0.15 V, respectively. This passivation can obviate the need for the conventional CVD-derived passivation process by utilizing the DC sputtering of gallium oxide, which may reduce hydrogen issues.

Fatigue Effect of Stretchable a-InGaZnO TFT on PI/PDMS Substrate under Repetitive Uni/Biaxial Elongation Stress

We examine the fatigue effects of repeated elongation stress for a fabricated a-IGZO thin-film transistor (TFT) on an island polyimide (PI)/poly(dimethylsiloxane) (PDMS) substrate. The repeated elongation stress evaluation was performed in both a uniaxial direction with 10, 30, and 50% strain and biaxial direction with 10, 20, and 30% strain for 50 000 cycles. The a-IGZO TFTs on the island PI exhibit the following parameters: Vth: −0.91 ± 0.30 V, μsat: 26.3 ± 0.61 cm2/(V s), and SS: 0.40 ± 0.02 V/decade. As a result of the repeated elongation stress in the maximum evaluated elongation (uniaxis: 50% and biaxis: 30%), the subthreshold swing (SS) increased by about 0.20 V/decade in all directions, and the saturation mobility decreased only in the x-axis direction (Δμsat: 26.30 → 21.43 cm2/(V s)). Through XPS analysis and TCAD simulation, it was confirmed that SS deteriorated due to an increase of the oxygen-vacancy-related defects (NGA and NGD) in the IGZO channel layer after repeated elongation stress. The transmission line method (TLM) confirmed that contact resistance increased when stretched only in the x-axis direction. In addition, the positive bias stress (PBS) test showed abnormal behavior including an additional SS-degradation-induced Vth negative shift after repeated elongation stress in all directions. Consequently, the degradation mechanism of both the electrical properties and bias stability for the stretchable a-IGZO TFT was determined after elongation stresses.