Polysilicon Sacrificial Layer Research Articles

Development of an Implantable Capacitive Pressure Sensor for Biomedical Applications.

In this study, a subminiature implantable capacitive pressure sensor is proposed for biomedical applications. The proposed pressure sensor comprises an array of elastic silicon nitride (SiN) diaphragms formed by the application of a polysilicon (p-Si) sacrificial layer. In addition, using the p-Si layer, a resistive temperature sensor is also integrated into one device without additional fabrication steps or extra cost, thus enabling the device to measure pressure and temperature simultaneously. The sensor with a size of 0.5 × 1.2 mm was fabricated using microelectromechanical systems (MEMS) technology and was packaged in needle-shaped metal housing that is both insertable and biocompatible. The packaged pressure sensor immersed in a physiological saline solution exhibited excellent performance without leakage. The sensor achieved a sensitivity of approximately 1.73 pF/bar and a hysteresis of about 1.7%, respectively. Furthermore, it was confirmed that the pressure sensor operated normally for 48 h without experiencing insulation breakdown or degradation of the capacitance. The integrated resistive temperature sensor also worked properly. The response of the temperature sensor varied linearly with temperature variation. It had an acceptable temperature coefficient of resistance (TCR) of approximately 0.25%/°C.

Single-side micromachined ultra-small thermopile IR detecting pixels for dense-array integration

This paper presents a technology to fabricate ultra-small (100 × 100 μm) thermopile infrared (IR) sensing devices with a novel front-side micromachining process for integration of dense IR detection array. The thermopile IR detection unit is constructed into double-level suspending films, where the IR absorber and n/p-polysilicon thermopile are located at the central-supported upper level and the surrounding-supported lower level, respectively. The separated design for IR absorber and thermopile temperature-detection helps to achieve a high thermocouple fill-factor of 0.9 in terms of the structural area. A single-step wet etching method is proposed to simultaneously release the umbrella-shaped upper-level absorber and the thermal insulation cavity beneath the lower-level thermopile layer. By pre-depositing a polysilicon sacrificial layer, the etching method breakthroughs the restriction of anisotropic over-etch to the single crystalline silicon substrate, thereby maximizing the thermocouple number in the lower-layer film and minimizing the opened area of the etching holes. Finite-element-method simulation results show that the detector with 20 pairs of thermocouples exhibits maximized responsivity than those with more or less pairs of thermocouples. Benefit from the optimized heat dissipation design, the thermopile detection unit in atmospheric environment achieves a high normalized detectivity of 2.1 × 107 cm Hz1/2 W−1, a high responsivity of 52 V W−1 and sound respond time of 1.4 ms. Thanks to the ultra-small unit area, many unites can be densely integrated into IR detection arrays of various scales. As an example, an integrated 4 × 4 IR sensing array is herein fabricated. The 16 integrated pixels demonstrate good consistency in responsivity, with the deviation being less than ±7%. Featuring the tiny-size pixels for dense-array integration and the single-sided micromachining process that is compatible with integrated circuit fabrication, the proposed thermopile IR sensing devices are promising in IR detection applications including consumer-electronic level IR focal plane arrays.

A MEMS Fabrication Process with Thermal-Oxide Releasing Barriers and Polysilicon Sacrificial Layers for AlN Lamb-Wave Resonators to Achieve fs·Qm > 3.42 × 1012.

This paper presents a micro-electro-mechanical systems (MEMS) processing technology for Aluminum Nitride (AlN) Lamb-wave resonators (LWRs). Two LWRs with different frequencies of 402.1 MHz and 2.097 GHz by varying the top interdigitated (IDT) periods were designed and fabricated. To avoid the shortcomings of the uncontrollable etching of inactive areas during the releasing process and to improve the fabrication yield, a thermal oxide layer was employed below the platted polysilicon sacrificial layer, which could define the miniaturized release cavities well. In addition, the bottom Mo electrode that was manufactured had a gentle inclination angle, which could contribute to the growth of the high-quality AlN piezoelectric layer above the Mo layer and effectively prevent the device from breaking. The measured results show that the IDT-floating resonators with 12 μm and 2 μm electrode periods exhibit a motional quality factor (Qm) as high as 4382 and 1633. The series resonant frequency (fs)·Qm values can reach as high as 1.76 × 1012 and 3.42 × 1012, respectively. Furthermore, Al is more suitable as the top IDT material of the AlN LWRs than Au, and can contribute to achieving an excellent electrical performances due to the smaller density, smaller thermo-elastic damping (TED), and larger acoustic impedance difference between Al and AlN.

Test Structure for Measuring the Selectivity in XeF2 and HF Vapour Etch Processes

Etch selectivity between layers is an important parameter in the fabrication of microelectronics and microsystems. This is particularly true in the case of isotropic gas/vapour etching methods used to release free standing structures through the selective etching of sacrificial layers. Commonly used structural materials have been reported to be largely inert when exposed to a given vapour etchant, indicating high selectivity when measured against typical sacrificial layers. However, there is growing evidence that these structural layers are actually etched at an enhanced rate if they are located in the proximity of the sacrificial layer being removed. Hence, removal rates given in the literature, which have resulted from measurements of layers that have been etched in isolation, can no longer be trusted to characterize critical etch processes in device fabrication. In this paper, a test structure is reported that enables a far more appropriate determination of the etch selectivity between sacrificial and structural materials. The method is demonstrated with the two most common vapour etch processes. Firstly, the XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> vapour etch of a polysilicon sacrificial layer located above a silicon nitride structural layer, and secondly, the HF vapour etch of silicon dioxide placed above a silicon nitride structural layer. Both test structure datasets are presented. The polysilicon and silicon nitride layers, etched with XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> show a selectivity of 5:4. The silicon dioxide and silicon nitride layers etched with HF, show a selectivity of 6:1 to 8:1.

The technology of planarizing sacrificial layer on wide cavity for MEMS devices

In order to prepare a polysilicon sacrificial layer on a wide cavity for a mirco-electromechanical system structure, this paper studied four kinds of CMP methods for polysilicon planarization. The dishing amount, polishing uniformity, surface roughness and wafer bow height were compared and discussed. A new CMP process has been developed for application to MEMS structures. Polysilicon on the backside of the wafer and outside of cavities was etched out. Then, the wafer was gross and fine polished with silicon slurry. Experimental results showed that the dishing amount was about 20 nm and showed good polishing uniformity, which meant local and global planarization. Meanwhile, its surface roughness was less than 1 nm, and the wafer bow height had no significant change pre- and post-CMP. This result suggests that the polysilicon CMP process developed in this work is effective and suits for application in MEMS fabrication.

Design and fabrication of ultrathin silicon-nitride membranes for use in UV-visible airgap-based MEMS optical filters

MEMS-based airgap optical filters are composed of quarter-wave thick high-index dielectric membranes that are separated by airgaps. The main challenge in the fabrication of these filters is the intertwined optical and mechanical requirements. The thickness of the layers decreases with design wavelength, which makes the optical performance in the UV more susceptible to fabrication tolerances, such as thickness and composition of the deposited layers, while the ability to sustain a certain level of residual stress by the structural strength becomes more critical. Silicon-nitride has a comparatively high Young's modulus and good optical properties, which makes it a suitable candidate as the membrane material. However, both the mechanical and optical properties in a silicon-nitride film strongly depend on the specifics of the deposition process. A design trade-off is required between the mechanical strength and the index of refraction, by tuning the silicon content in the silicon-nitride film. However, also the benefit of a high index of refraction in a silicon-rich film should be weighed against the increased UV optical absorption. This work presents the design, fabrication, and preliminary characterization of one and three quarter-wave thick silicon-nitride membranes with a one-quarter airgap and designed to give a spectral reflectance at 400 nm. The PECVD silicon-nitride layers were initially characterized, and the data was used for the optical and mechanical design of the airgap filters. A CMOS compatible process based on polysilicon sacrificial layers was used for the fabrication of the membranes. Optical characterization results are presented.

An Integrated Surface Micromachined Convex Microhotplate Structure for Tin Oxide Gas Sensor Array

This paper describes the fabrication process for a novel convex microhotplate (MHP) structure using surface micromachining technology. The process is used to fabricate an integrated 4times4 tin oxide gas sensor array. Surface micro-machining is selected for its simplified process and CMOS compatibility. However, limited sacrificial layer thickness usually leads to higher power consumption. In this work, a convex MHP structure is developed to increase the thermal efficiency, which is critical for large dimension and low-power gas sensor array integration. Before the structure release process, 700degC-950degC annealing process was carried out on the 190 times190 mum2 MHP with 2.8 mum polysilicon sacrificial layer. It is shown that higher annealing temperature leads to lower tensional stress of the MHP membrane and larger curvature of the released structure, which enables higher thermal efficiency. Among the four annealing temperatures, the 950degC annealed MHP has the largest curvature of 2.438 cm-1 and the highest thermal efficiency of 13degC/mW. Experimental results showing the responses of the sensor array to different combustible gases are also illustrated in this paper. Comparison of power consumption with other designs reported in the literature illustrates the effectiveness of the proposed process.

Dry etch release processes for micromachining applications

The authors report on the comparative study of two dry etch processes for polysilicon sacrificial layer release using vapor phase xenon difluoride (XeF2) continuous etching and inductively coupled plasma (ICP) etching with sulfur hexafluoride (SF6) gas. Test structures of 0.5μm thick polysilicon have been patterned and etch channels varying in widths from 1to500μm have been fabricated successfully for the purpose of comparison. The influence of etch pressure, aperture opening size, and ICP etch power on the undercut etching rate as well as selectivity between mask and substrate have been studied. It has been possible to achieve an undercut etch rate of up to 11.6μm∕min under a pressure of 3Torr in XeF2 etch gas, while for SF6 plasma, an undercut etch rate of 2.56μm∕min at 65mTorr is obtained. Moreover, the optimized process has been employed for the fabrication of silicon carbide (SiC) resonators.

Nanothick Layer Transfer of Hydrogen-implanted Wafer Using Polysilicon Sacrificial Layer

AbstractAn ion implantation-wafer bonding-layer splitting based 2-D nanostructure material fabrication method using polysilicon sacrificial layer for forming nanothick SOI materials without using post-thinning processes is presented in this paper. Polysilicon layer was initially deposited on the thermal oxidized surface of silicon wafer prior to the ion implantation step to achieve the hydrogen-rich buried layer which depth from the top surface is less than 100 nm in the as-implanted silicon wafer. Before this as-implanted wafer being bonded with a handle wafer, the polysilicon layer was removed by a wet etching method. A nanothick silicon layer was then successfully transferred onto a handle wafer after wafer bonding and layer splitting steps. The thickness of the final transferred silicon layer was 100 nm measured by transmission electron microscopy (TEM).

Polycrystalline silicon-carbide surface-micromachined vertical resonators-part I: growth study and device fabrication

This manuscript is the first of a two-part series describing the fabrication and testing of MHz frequency, polycrystalline silicon-carbide (poly-SiC) micromechanical resonators made from films deposited by atmospheric-pressure chemical-vapor deposition (APCVD). In Part I, the development of deposition and patterning techniques suitable for the fabrication of vertically actuated, clamped-clamped beam resonant structures is detailed. Recipe development involved film deposition and material analysis on both planar and patterned substrates. We found that a carbonization-based deposition process modeled after epitaxial growth of 3C-SiC on Si produced the highest quality poly-SiC films for use with sub-micron thick polysilicon sacrificial layers, regardless of topology. Devices utilizing beam thicknesses up to 1 /spl mu/m were fabricated and successfully released. Details about the testing of the released structures are presented in Part 2 of this series (see Wiser, Tabib-Azar, Mehregan, and Zorman, Polycrystalline silicon-carbide surface-micromachined vertical resonators-Part II: Electrical testing and material property extraction, J. Microelectromech. Syst., vol. 14, no. 3, Jun. 2005).

A novel planarization process for polysilicon sacrificial layers in a micro-thermal system

Abstract The objective of this study is to solve the difficulties encountered during planarization and etching of a polysilicon film that is deposited and used as a sacrificial layer in an oxide structure in a micro-thermal system such as a micro-channel device as mentioned in the previous paper. This polysilicon film has a relatively wide and deep ditch. Two different chemical–mechanical–polishing (CMP) processes that have been used to flatten the polysilicon-made sacrificial layer will be presented and the results are not very successful. A novel planarization technique using wet etch process is developed which has been shown to be able to flatten very effectively a surface with wide and deep ditch.

Growth of Polycrystalline Silicon Carbide on Thin Polysilicon Sacrificial Layers for Surface Micromachining Applications

ABSTRACTPolycrystalline silicon carbide (poly-SiC) films were deposited by atmospheric pressure chemical vapor deposition (APCVD) at epitaxial growth temperatures on planar, 100 nm-thick polysilicon sacrificial layers using two recipes that included or excluded a pre-growth carbonization step. Poly-SiC films grown using the carbonization-based recipe exhibited a relatively high degree of (111) 3C-SiC texture and had uniform, well-defined, void-free poly-SiC/polysilicon interfaces. In contrast, poly-SiC films grown without carbonization were randomly oriented, had numerous poly-SiC inclusions that sometimes completely penetrated the polysilicon underlayer, and had a higher surface roughness than the films grown with carbonization. Analysis of micromechanical clamped-clamped (C-C) beam resonators fabricated from films grown using the two differing recipes shows that the carbonization step is needed to protect the thin polysilicon sacrificial layer from voids and inclusions and thus maintain the proper spacing between the drive electrodes and the resonant beams.

High Performance PST Thin Films on Polysilicon Sacrificial Layers for Uncooled IR Detectors

Materials merit figures nearly 4 times that of PZT have been reported for sputtered lead scandium tantalate thin films. To achieve the required PST ferroelectric crystal phase, post-deposition annealing to temperatures above that allowable for silicon readout circuit survival is required. This paper describes the deposition of thin film lead scandium tantalate (Pb 2 ScTaO 6 ) over a polysilicon sacrificial layer, compatible with high temperature annealing, for use with a 'composite' wafer approach. A Tantalum oxide barrier layer is used to prevent PbO diffusion into the polysilicon during the high temperature annealing stage. Materials are characterised by X-ray diffraction and transmission electron microscopy. Some annealed films have shown B-site ordering. Induced pyroelectric coefficients over 1.2 2 10 m 3 Cm m 2 K m 1 have been measured in the annealed films, with materials merit figure exceeding 8 2 10 m 5 Pa m 1/2 at 9.3V/ w m.

High Performance PST Thin Films on Polysilicon Sacrificial Layers for Uncooled IR Detectors

High Performance PST Thin Films on Polysilicon Sacrificial Layers for Uncooled IR Detectors

An improved TMAH Si-etching solution without attacking exposed aluminum

In MEMS fabrication technology, it is often desirable to etch silicon substrate or polysilicon sacrificial layer after metallization is completed. Most of the etching solution would attack the aluminum. In this paper, an improved tetramethyl ammonium hydroxide (TMAH) etching method is reported. The advantages of the process are to achieve high silicon etching rate (0.9–1.0 μm/min at 85°C) and smooth silicon surface (less than 0.2 μm root-mean-square). Another important advantage is that no significant aluminum etching is observed during this process. The etchant used in the study consists of 5 wt.% TMAH solution, 1.4 wt.% (or above) dissolved silicon, and 0.4–0.7 wt.% (NH 4) 2S 2O 8 ammonium peroxodisulfate. The aluminum etching rate is significantly reduced by the addition of the ammonium peroxodisulfate, which also significantly improved the silicon surface roughness. When dissolving a suitable amount of silicon in TMAH etchant, along with a suitable amount of ammonium peroxodisulfate, the aluminum etching rate is reduced to zero. After TMAH etching the aluminum surfaces are protected by the coating of by-products, which prevents the underlying aluminum film from being etched by TMAH solution. The etching process demonstrated in this work is readily applicable to MEMS (micro-electromechanical system) device fabrication, such as polysilicon sacrificial layer removal, after the metallization is completed.

Micromachining Techniques for Advanced SiC MEMS

ABSTRACTThis paper reviews the development of a multilayer, micromolding-based surface micromachining process for SiC microelectromechanical systems (MEMS). The micromolding process uses polysilicon and SiO2 thin films that are deposited onto polysilicon and SiO2 sacrificial layers, patterned into micromolds by reactive ion etching, filled with polycrystalline SiC (poly-SiC), planarized by mechanical polishing, and eventually dissolved and released in selective wet chemical etchants. In addition, a SiC lift-off technique that exploits the microstructural differences between SiC films deposited on Si, SiO2 and Si3N4 surfaces has been developed. The micromolding and lift-off techniques are being used as the basic patterning processes for a four-layer, poly-SiC surface micromachining process that we call the MUSiC (Multi-User SiC) process.

Fabrication and characterization of surface micromachined capacitive ultrasonic immersion transducers

In this paper, several innovative steps used in fabricating surface micromachined capacitive ultrasonic immersion transducers are reported. The investigation is focused on major steps in the device fabrication processes necessary to optimize transducer performance. Such steps include membrane formation, vacuum sealing, and electrode metallization. Three transducer membrane structures are evaluated: a nitride membrane with an oxide sacrificial layer; a polysilicon membrane with an oxide sacrificial layer; and a nitride membrane with a polysilicon sacrificial layer. Three vacuum sealing mechanisms are compared, each of which requires a different degree of lithographic sophistication, uses a particular sealing mechanism, and results in a sealed cavity. Submicrometer via sealing requires sophisticated lithography but is amenable to LPCVD nitride, LTO, and other sealing procedures. Standard g-line lithography results in vies which seal only with high sticking coefficient species, such as LTO. A novel etch channel structure, which results in lateral sealing and requires neither sophisticated lithography nor a particular sealing material, is demonstrated. Finally, the impact of electrode metallization on the impedance, bandwidth, and efficiency of the transducers is discussed. The experiments in the paper are guided by theoretical analysis and computer simulations when applicable. The new process results in optimized devices which have a broad-band 50-/spl Omega/ real part impedance in the megahertz range. A transducer dynamic range in excess of 100 dB is achieved around 4.5 MHz. An untuned transducer exhibits more than 100% bandwidth when connected to electronics with 50-/spl Omega/ input impedance. In addition, beam pattern measurement shows the immersion devices behave like uniform piston transducers and are readily suitable for array applications. The fabrication techniques and results herein reported indicate that surface micromachined ultrasonic immersion transducers are an attractive alternative to piezoelectric transducers in immersion applications.

Integrated Pyroelectric Infrared Sensor Using Pvdf thin Film Deposited by Electro-Spray Method

AbstractA pyroelectric infrared sensor using a poly(vinylidene fluoride) (PVDF) thin film has been integrated with a read-out circuit on a silicon substrate. The PVDF thin film with a thickness of 1-2 µm was deposited on the sensing area by an electro-spray (ESP) method. A form I crystal and a large pyroelectric coefficient of 4 nCcm−2K−1 were observed just after the deposition without any poling treatments. The fabrication process of the sensor was based on a standard MOS LSI process and a polysilicon sacrificial layer etching technique. In order to reduce the heat capacitance and the thermal conduction, the PVDF thin film was supported on a thin Si3N4 membrane structure formed by etching a part of the silicon substrate under the sensing area. The sensor with a sensing area of 400x400 µm2 had a responsivity of 98 V/W, a detectivity of l.4× 107 cmHz1/2W−1, an NEP of 2.9× 10−99 Hz1/2W at a frequency of 100 Hz and a time constant of 1.3 msec.