Abstract
In order to prepare a polysilicon sacrificial layer on a wide cavity for a mirco-electromechanical system structure, this paper studied four kinds of CMP methods for polysilicon planarization. The dishing amount, polishing uniformity, surface roughness and wafer bow height were compared and discussed. A new CMP process has been developed for application to MEMS structures. Polysilicon on the backside of the wafer and outside of cavities was etched out. Then, the wafer was gross and fine polished with silicon slurry. Experimental results showed that the dishing amount was about 20 nm and showed good polishing uniformity, which meant local and global planarization. Meanwhile, its surface roughness was less than 1 nm, and the wafer bow height had no significant change pre- and post-CMP. This result suggests that the polysilicon CMP process developed in this work is effective and suits for application in MEMS fabrication.
Published Version
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