Polysilicon Depletion Research Articles

Frequency dispersion and dielectric relaxation in postdeposition annealed high-κ erbium oxide metal–oxide–semiconductor capacitors

The origin of frequency dispersion in postdeposition rapid thermal and furnace annealing treated Pt/Er2O3/Si/Pt, metal–insulator–semiconductor–metal (MISM) structure is systematically investigated. The cause of frequency dispersion in Pt/Er2O3/Si/Pt, MISM structure is attributed to the dielectric relaxation in high-κ Er2O3, after suppressing the extrinsic effects such as parasitic, lossy interfacial layer, surface roughness, polysilicon depletion, quantum confinement, and oxide tunneling. Further, the Havrilian–Negami law is used to model the frequency dispersion in postdeposition rapid thermal and furnace annealing treated Pt/Er2O3/Si/Pt, MISM structure up to 250 kHz. It is suggested that to obtain an accurate capacitance value, the dissipation factor must be minimum for the MISM structure with nanometer scale oxides/insulators. Additionally, a methodology is proposed for simple and efficient correction of measured capacitance from capacitance–voltage and capacitance–frequency characteristics. Moreover, the flatband voltage shift/hysteresis, frequency dependent border traps are estimated ∼0.45 V, ∼3.35 × 1012 traps/cm2 and ∼0.18 V, ∼1.84 × 1012 traps/cm2 for postdeposition rapid thermal and furnace annealing treated Pt/Er2O3/Si/Pt, MISM structures, respectively. Therefore, postdeposition furnace annealing treatment is superior to achieve high-quality high-κ Er2O3 (κ ∼16), with low frequency dispersion of ∼9% up to 250 kHz and minimal hysteresis (∼0.18 V) for next-generation complementary metal–oxide–semiconductor technology.

Depletion effect of polycrystalline-silicon gate electrode by phosphorus deactivation

A study of the polycrystalline silicon depletion effect generated from the subsequent thermal process is undertaken. Although phosphorus out-diffusion, which causes the polycrystalline silicon depletion effect, is increased with an increase in the thermal process temperature, the polysilicon depletion effect is stronger when inducing rapid thermal annealing in lower temperatures of 600–800°C than in 900°C. This indicates that the major reason for the polysilicon depletion effect is not the out-diffusion of phosphorus but the electrical deactivation of phosphorus, which is segregated at the grain boundary. Therefore, by increasing the size of polycrystalline silicon grain, we can efficiently reduce the polysilicon depletion effect and enhance the tolerance to deactivation.

Temperature-Dependent Remote-Coulomb-Limited Electron Mobility in $\hbox{n}^{+}$-Polysilicon Ultrathin Gate Oxide nMOSFETs

Additional electron mobility due to remote scatterers in n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -polysilicon 1.65-nm gate oxide (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) n-channel metal-oxide-semiconductor field-effect transistors is experimentally extracted at three different temperatures (i.e., 233, 263, and 298 K). The core of the extraction process consists of simulated temperature-dependent universal mobility curves and Matthiessen's rule in a mobility universality region. Resulting additional mobility for the first time experimentally exhibits a negative temperature coefficient, confirming interface plasmons in a polysilicon depletion region to be dominant remote Coulomb scatterers. We also present corroborative evidence as quoted in the literature, including: 1) calculated temperature-dependent remote Coulomb mobility due to ionized impurity atoms in a polysilicon depletion region; 2) experimentally assessed additional mobility at room temperature; and 3) simulated remote Coulomb mobility due to interface plasmons in a polysilicon depletion region as well as its temperature coefficient. Validity of Matthiessen's rule used in this paper is verified.

Impact of Control-Gate and Floating-Gate Design on the Electron-Injection Spread of Decananometer nand Flash Memories

This letter investigates the impact of control-gate (CG) and floating-gate (FG) doping and geometry on the electron-injection spread (EIS) of nanoscale nand Flash memories. Doping of CG polysilicon rules the reduction of the CG-to-FG capacitance when moving from the read to the program conditions, as a result of polysilicon depletion. The capacitance reduction is shown, however, to be nearly negligible for the EIS resulting from incremental step pulse programming, which, for the commonly adopted voltage steps, is mainly determined by the capacitance value in read conditions. Finally, the scaling trend of the CG-to-FG capacitance and of the EIS is addressed, discussing the evolution of the FG polysilicon in terms of geometry and dimensions.

Effect of Floating-Gate Polysilicon Depletion on the Erase Efficiency of nand Flash Memories

This letter presents a detailed experimental investigation of the erase transients of decananometer NAND Flash memories, showing a drop and then a recovery of the erase efficiency as the erase bias is increased. The modulation of the erase efficiency is studied as a function of the erase time, temperature, and the number of applied pulses: Longer erase times or higher temperatures are shown to reduce the efficiency drop, while this is enhanced when the erase pulse is split into a sequence of short pulses. Experimental evidences are explained as a result of the deep-depletion condition that exists in the floating-gate polysilicon for moderate erase biases and short erase times, reducing the electric field in the tunnel oxide and the electron-tunneling current discharging the floating gate.

Modeling of Polysilicon Depletion Effect in Recessed-Channel MOSFETs

The polysilicon depletion effect is one of the key factors that degrade MOSFETs' performance. In this letter, a polysilicon depletion model for recessed-channel (RC) MOSFETs is presented. The model shows good agreement with numerical device simulation results. We also compare the polysilicon depletion effect of RC MOSFETs to that of planar MOSFETs.

Influence of the Tunneling Gate Current on C-V Curves

This paper presents a study of the tunneling gate current influence on the Capacitance vs. Voltage curve in deep submicrometer CMOS technology. Two-dimensional numerical simulations are performed considering thin gate oxide and N+ polysilicon as a gate material. The influence of the tunneling gate current on the polysilicon depletion region is also analysed. It is observed that the tunneling current masks the polysilicon depletion effect due to the large increase of the substrate silicon depletion region.

Compact Gate Capacitance Model with Polysilicon Depletion Effect for MOS Device

The MOS gate capacitance model presented here is determined by directly solving the coupled Poisson equations on the poly and silicon sides, and includes the polysilicon (poly) gate depletion effect. Our compact gate capacitance model exhibits an excellent fit with measured data and parameter values extracted from data are physically acceptable. The data are collected from 0.5, 0.35, 0.25 and 0.18㎛ CMOS technologies.

Modeling of Inversion Layer Centroid and Polysilicon Depletion Effects on Ultrathin-Gate-Oxide MOSFET Behavior: The Influence of Crystallographic Orientation

An empirical expression is developed for the inversion layer centroid and the polysilicon-gate depletion region thickness for bulk MOSFETs with different crystallographic orientations. In particular, results for the most commonly used wafer orientations, i.e., (100), (110), and (111), are given. These expressions are used to accurately model the inversion charge (Qinv) and the gate-to-channel capacitance (Cgc) of MOSFETs with gate oxides of nanometric thickness (tox < 1 nm) and different surface orientations. The Poisson and Schrodinger equations are self-consistently solved for different values of silicon and polysilicon doping concentrations in these devices. The results show important reductions of both Qinv and Cgc because of the polysilicon depletion effect and the displacement of the inversion charge centroid from the interface to the silicon bulk as a consequence of quantum effects. These effects are very noticeable for gate-oxide thicknesses of around 1 nm and must be taken into account in the development of accurate MOSFET models. The authors show that this task can be performed by means of a corrected gate-oxide thickness, which includes both the effect of the inversion layer centroid ZI and the polydepletion region thickness Z D. To do this, the authors have developed an accurate model for ZI as a function of the inversion charge concentration, the depletion charge concentration, and the silicon doping concentration for the (100), (110), and (111) wafer orientations. The in-plane channel directions have been swept for each wafer orientation in order to study the validity of the model in depth. Similarly, an expression for ZD as a function, of the polydoping concentration is provided. The gate-to-channel capacitance is also carefully and extensively analyzed. An analytical model for Cgc is provided and tested for different values of oxide thickness, polysilicon doping, substrate doping, and gate voltage

An electron mobility model for ultra-thin gate-oxide MOSFETs including the contribution of remote scattering mechanisms

The effect of remote scattering mechanisms (such as remote Coulomb scattering and remote surface-roughness scattering) on electron mobility in ultra-thin oxide MOSFETs was studied. We highlighted the important role these scattering mechanisms play in state-of-the-art devices, mainly at low temperatures. As a consequence, the effects of these remote mechanisms on the electron mobility should be taken into account in accurate ultra-thin gate-oxide device simulations. We have developed a mobility model which takes into account the contribution of remote scattering mechanisms in ultra-thin oxide MOSFETs (including both the polysilicon-oxide surface-roughness and Coulomb scattering due to the polysilicon depletion charge). The proposed expression allowed us to reproduce the Monte Carlo simulation results obtained for several of these ultra-thin gate oxide devices. We also used this model along with previously developed models to account for the different scattering mechanisms usually included in mobility analytical calculations to reproduce the experimental results for very thin oxide MOSFETs.

Effect of gate poly-silicon depletion on MOSFET input impedance

One of the most challenging problems encountered in developing RF circuits is accurate prediction of MOS behavior at microwave signal and data frequencies. An attempt is made in this work to accurately model the device input impedance for the 1-20-GHz frequency range. The effect of device length and single-leg width on the input impedance is studied with the aid of extensive measured data obtained from devices built in 0.11-/spl mu/m and 0.18-/spl mu/m technologies. The measured data illustrates that the device input impedance has a nonlinear frequency dependency. It is also shown that this variation in input impedance is a result of gate poly-silicon depletion, which can be modeled by an external RC network connected at the gate of the device. Excellent agreement between the simulation results and the measured data validates the model in the device active region.

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.

Development of plasma etching process for sub-50 nm TaN gate

TaN has been identified as a possible candidate to replace polysilicon for sub-50 nm gate CMOS transistors. However, TaN gate etching in CD (critical dimensions) range below 100 nm presents a great challenge and not much information is available in this area. Using thin layer of SiO 2 as a hard mask, TaN etching was evaluated in DPS (decoupled plasma source) etcher with four gas chemistries: Cl 2, Cl 2/BCl 3/Ar, Cl 2/BCl 3, and Cl 2/Ar. Due to lesser CD gain and higher selectivity to gate dielectrics, Cl 2/Ar was chosen for further optimization by DOE. Based on the analysis of the effects of input parameters on the etch responses, we developed a two-step etch process with sub-50 nm minimal CD, profile close to vertical, and capability to stop on 5 nm HfAlO high-k dielectric. 60-nm gate transistors with TaN-HfAlO gate stack (equivalent oxide thickness of 2.5 nm) were fabricated with reasonably low gate leakage of 10 − 2 A/cm 2 at gate bias of 1 V and absence of polysilicon depletion effect.

Random Telegraph Noise in 30 nm FETs with Conventional and High-κ Dielectrics

The magnitude of fractional current variation in ultra-small (30 nm channel length) MOSFETs due to single charge trapping-detrapping events at any position within the gate dielectric is studied using numerical simulation. These random telegraph signals in the drain current indicate the amplitude of low frequency MOSFET noise. Simulations are performed for realistic devices with poly-silicon gates subject to poly-silicon depletion, and for both SiO2 and HfO2 as dielectric materials.

Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface—Part I

We report here that Fermi pinning at the polysilicon/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. We show that this fundamental characteristic affects the observed polysilicon depletion. In Part I, the theoretical background is reviewed and the impact of the different gate stack regions are separated out by investigating the relative threshold voltage shifts of devices with Hf-based dielectrics. The effects of the interfacial bonding are examined in Part II.

Thermally Stable Fully Silicided Hf-Silicide Metal-Gate Electrode

We demonstrate, for the first time, thermally stable fully silicided (FUSI) Hf-silicide gate electrode whose work function (4.2 eV) is very close to that of n/sup +/ polysilicon. No polysilicon depletion effect and excellent thermal stability with negligible change in equivalent oxide thickness and flatband voltage even after high-temperature annealing at 950 /spl deg/C are demonstrated. These results indicate that FUSI Hf-silicide is a promising candidate for n-MOSFET metal-gate electrode for dual-metal CMOS process.

Fermi-Level Pinning at the Polysilicon/Metal–Oxide Interface—Part II

We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

Quantum mechanical modeling of gate capacitance and gate current in tunnel dielectric stack structures for nonvolatile memory application

Multilayered dielectric stack structures, with a layered or crested potential profile, have been proposed for use as the tunnel dielectric of nonvolatile memories for fast low-voltage programming and longer charge retention. In this work, self-consistent quantum mechanical (QM) numerical calculations, using an in-house developed charge quantization simulation program, were conducted to analyze the gate tunneling current and capacitance of metal–insulator–semiconductor (MIS) devices with tunnel dielectric stack structures. The self-consistent QM simulator takes into account polysilicon depletion, quantization effects on the carrier density, and wave penetration effects. The gate current density–gate voltage (Jg–Vg) simulation uses a recursive method for calculating the transmission probability through the dielectric stack structure. The physical model was used to fit with capacitance–voltage and Jg–Vg measurements on MIS devices with different single-layer dielectric and multilayered dielectric stack structures. The simulation of the Jg–Vg characteristics of a layered-barrier structure of HfO2/Al2O3/HfO2, which can be potentially applied as the tunnel dielectric of nonvolatile memory devices, is also presented and compared with results from metal–oxide–semiconductor devices with a single layer of SiO2 or HfO2 as gate dielectric. It was found that the layered-barrier structure has the steepest Jg–Vg characteristics of the three structures with identical equivalent-oxide thickness. This results in a small ratio of program voltage to retention voltage for the layered-barrier structure, which makes it attractive for nonvolatile memory application.

Subnanometer Scaling of HfO[sub 2]/Metal Electrode Gate Stacks

The equivalent oxide thickness (EOT) of high-k n-channel metal oxide semiconductor (NMOS) transistors was scaled using 3 methods, reduction of the bottom interfacial layer (BIL) using interface engineering, thickness reduction of the dielectric, and use of metal gate electrodes to minimize top interfacial growth formation and polysilicon depletion. NMOS transistors fabricated using these methods demonstrate 0.72 nm EOT using the BIL with scaled /metal gates and 0.81 nm EOT using the BIL with scaled /metal gates. Charge pumping, mobility, and device performance results of these high-k NMOS transistors is discussed. © 2004 The Electrochemical Society. All rights reserved.

Investigations of Metal Gate Electrodes on HfO2 Gate Dielectrics

ABSTRACTAs traditional poly-silicon gated MOSFET devices scale, the additional series capacitance due to poly-silicon depletion becomes an increasingly large fraction of the total gate capacitance, excessive boron penetration causes threshold voltage shifts, and the gate resistance is elevated. To solve these problems and continue aggressive device scaling we are studying metal electrodes with suitable work-functions and sufficient physical and electrical stability. Our studies of metal gates on HfO2 indicate that excessive inter-diffusion, inadequate phase stability, and interfacial reactions are mechanisms of failure at source drain activation temperatures that must be considered during the electrode selection process. Understanding the physical properties of the metal gate – HfO2 interface is critical to understanding the electrical behavior of MOS devices. Of particular interest is Fermi level pinning, a phenomenon that occurs at metal – dielectric interfaces which causes undesirable shifts in the effective metal work function. The magnitude of Fermi level pinning on HfO2 electrodes is studied with Pt and LaB6 electrodes. In addition, the intrinsic and extrinsic contributions to Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the work function of platinum-HfO2-silicon capacitors. The presence of interfacial oxygen vacancies or Pt-Hf bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone. Interface chemistry and defects influence the effective metal work function.