Polyphase Filter Research Articles

A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

The design, implementation, and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters (PPF) are presented. The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion. Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band. Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip, the mixer exhibits a high image rejection ratio (IRR) of 58 dB, a power consumption of 11 mW, and a 1-dB gain compression point of −15 dBm.

$Ka/Ku$-Band pHEMT Gilbert Mixers With Polyphase and Coupled-Line Quadrature Generators

In this paper, three kinds of Kalpha/Ku-band Gilbert mixers are demonstrated using 0.15- mum AlGaAs/InGaAs pseudomorphic high electron mobility transistor technology. Thanks to the semiinsulating GaAs substrate, microwave passive components have a low-loss feature, and polyphase filters work up to higher frequencies. Highly accurate tantalum-nitride thin-film resistors utilized in polyphase filters result in perfect quadrature operation. Therefore, our proposed single-sideband up-converter operates at 15 GHz with a 63-dB sideband rejection ratio, and another 34-GHz in-phase/quadrature (I/Q) subharmonic down-converter reaches <0.4-dB magnitude and < 1deg phase errors. More than 50-dB local oscillator (LO) leakage suppression is achieved in the I/Q subharmonic mixer. On the other hand, a 40-GHz stacked-LO subharmonic mixer with a novel compensation technique is also proposed and demonstrated to improve LO speed and reduce the amount of transistors, as compared to previous work.

High-performance active polyphase filter design for digital TV tuner

This paper presents the polyphase filter design for the tuner of DTV front-end system. The polyphase filter is designed with an active circuit to improve the chip performance. Most of passive capacitor and resistor components are replaced with MOS transistors. The proposed method not only can reduce the chip area but also gain the signal level. For the prototyping implementation, the current channel bands in Taiwan are referred, which the frequency range is from 530 to 602MHz for DTV programs. In experiments, the polyphase filter can achieve 85dB for the image rejection in the center frequency. The main signal can be gained about 2–5dB without using extra amplifier. The chip size is about 0.09mm2, and the average power dissipation is about 15mW, when the chip technology employed TSMC 0.35μm CMOS process. The proposed chip outperforms with less area and higher gain.

A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 $\mu$m CMOS

Quadrature bandpass SigmaDelta modulators based on polyphase filters are suited for analog-to-digital conversion in GSM/EDGE low-IF receivers. This paper presents a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is a desirable solution for implementation in low power applications. A new compensation scheme for the polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25 mum CMOS technology. The designed SigmaDelta modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a peak SNDR of 86.8 dB. The chip area is 0.5 times 1.4 mm2 including pads.

A multiband carrier generation architecture for UHF, 2.4 GHz, and 5 GHz ISM applications

Novel multiband carrier generation architecture is proposed that can be applicable for RFID reader, WLAN 802.11a-b-g, and ZigBee sensor network, and implemented with 0.18 μm CMOS technology. In the proposed architecture, a quadrature voltage controlled oscillator (QVCO) is implemented by coupling two differential cross-coupled LC VCOs to generate in-phase (I) and quadrature (Q) signals operating at one-thirds of the 5 GHz frequency range. As well, the differential second harmonic signal of the VCO core frequency is generated by mixers, and then converted to I/Q signals via a single-stage tunable polyphase filter. By single sideband mixing of the I/Q signals of the QVCO and the polyphase filter, a cleaner carrier signal can be generated in the frequency band of 5 GHz. By including extra frequency dividers, the architecture can also be reconfigured to generate UHF band and 2.4 GHz band. The proposed architecture draws about 32 mA including the QVCO core current consumption of 2.8 mA from 1.8 V supply. The measured tuning frequency of the QVCO core ranges from 1.57 to 1.84 GHz. The measured phase noise is −104.5 dBc/Hz at 1 MHz offset from 4.84 GHz. The chip layout occupies an area of 1.44 × 1.4 mm2 on Si substrate, including the DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.

A New Transceiver Architecture for the 60-GHz Band

A new ldquohalf-RFrdquo architecture incorporates a polyphase filter in the signal path to allow the use of a local oscillator frequency equal to half the input frequency. The receiver performs 90deg phase shift and two downconversion steps to produce quadrature baseband outputs. The transmitter upconverts the quadrature baseband signals in two steps, applies the results to a polyphase filter, and sums its outputs. Each path employs a dedicated 30-GHz oscillator and is fabricated in 90-nm CMOS technology. The receiver achieves a noise figure of 5.7-7.1 dB and gain/phase mismatch of 1.1 dB/2.1deg while consuming 36 mW. The transmitter produces a maximum output level of -7.2 dBm and an image rejection of 20 dB while drawing 78 mW.

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse‐grained processing elements that can be configured as complex DSP functions that are the basic building blocks of Polyphase‐FIR filters, phase shifters, DFTs, and Polyphase‐DFT circuits. The homogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to its nearest neighbors via configurable switch (SW) elements, enables array expansion for parallel processing and facilitates time sharing computation of high‐throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimization technique has been employed to reduce the overall number of vector‐matrix products to be mapped on the RSA. The hardware complexity and throughput of the RSA‐based DFT structures have been evaluated and compared against several conventional modular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphase filter circuits are also presented. The RSA architecture offers significant flexibility and computational capacity for applications that require real time reconfiguration and high‐density computing.

10 GHz dual-conversion low-IF downconverter with microwave and analogue quadrature generators

A 10 GHz dual-conversion low-IF downconverter using 0.18-µm CMOS technology is demonstrated. The high-frequency quadrature RF and LO1 signals are generated by broadside-coupled quadrature couplers while a two-section polyphase filter is utilised for the low-frequency LO2 quadrature signal generation. As a result, the demonstrated downconverter achieves a conversion gain of 7 dB, IP1 dB of −16 dBm, IIP3 of −5 dBm and noise figure of 26 dB at a 1.8 V supply. The image-rejection ratio of the first/second image signal is 33/42 dB for IF frequency ranging from 10 to 60 MHz, respectively.

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering

Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuit-level techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X.

Analysis of a high frequency and wide bandwidth active polyphase filter based on CMOS inverters

An active polyphase filter capable of high frequency quadrature signal generation has been analyzed. The resistors of the classical passive polyphase filter have been replaced by transconductors, CMOS inverters (F. Tillman and H. Sjoland, Proceedings of the Norchip Conference (pp. 12---15), Nov. 2005; Analog Integrated Circuits and Signal Processing, 50(1) 7---12, 2007). A three-stage 0.13 μm CMOS active polyphase filter has been designed. Simulations with a differential input signal show a quadrature error less than 1° for the full stable input voltage range for frequencies from 6 GHz to 14 GHz. Phase errors in the differential input signal are suppressed at least three times at the output. Corner simulations at 10 GHz show a maximum phase error of 3° with both n- and pMOS slow, in all other cases the error is less than 0.75°. The three-stage filter consumes 34 mA from a 1.2 V supply. To investigate the robustness of the filter to changes in inverter delay, an inverter model was implemented in Verilog-A. Linear c in and g in were used, whereas g m , c out , and g out were non-linear. It was found that the filter could tolerate substantial delays. Up to 40° phase shift resulted in less than 1.5° quadrature phase error at the output.

A dual-band direct-conversion RF front-end for WiMedia UWB receiver

This paper describes a direct-conversion RF front-end designed for a dual-band WiMedia UWB receiver. The front-end operates in band group BG1 and BG3 frequencies. It includes multi-stage LNAs, down-conversion mixers, a polyphase filter for quadrature local oscillator (LO) signal generation, and LO buffers. The UWB receiver is targeted for a mobile handset, where several other radios can be simultaneously on. Therefore, special attention was paid on minimizing the interference from different wireless systems. The front-end achieves approximately 26-dB gain and 4.9---5.6-dB noise figure (NF) across three sub-bands of BG1. In BG3 mode it obtains 23---26-dB gain and 6.9---7.7-dB NF. The front-end consumes 48.1 and 42.7 mA from a 1.2-V supply voltage in BG1 and BG3 operation modes, respectively. The chip was implemented in a 0.13-μm CMOS.

A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators

This paper presents a strategy for successful polyphase-filter design for continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulators. Based on a low-pass filter with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is suited for implementation in low-power applications - analytical equations are derived. A new compensation scheme is proposed and implemented by cross-coupling additional resistors, without the necessity of extra-active components. Translation to intermediate frequency in second- and fourth-order polyphase filters with the proposed compensation scheme are compared to analytical considerations and simulation. Nonlinearities introduced by mismatch of feedforward coefficients and finite gain-bandwidth of amplifiers are considered.

A Complementary-Coupled CMOS LC Quadrature Oscillator

SUMMARY A novel CMOS LC quadrature oscillator (QO) whichadopts complementary-coupling circuitry has been proposed. The perfor-mance improvement in I/Q phase error and phase noise of the proposedQO, is explained in comparison with conventional QOs. The proposedQO is implemented in 0.18μm CMOS technology along with conventionalQOs. The measurement result of the proposed QO shows −133.5dBc/Hzof phase noise at 1MHz offset and 0.6 ◦ I/Q phase difference, while oscil-lating at 1.77GHz. The proposed QO shows more than 6.5dB phase noiseimprovement compared to that of the conventional QOs over the offset fre-quency range of 10K–1MHz, while dissipating 4mA from 1.4V supply. key words: complementary metal oxide semiconductor (CMOS), quadra-ture oscillator, phase noise, I / Q phase error 1. Introduction The need for quadrature signal increases continuously in to-day’s radio transceiver design for various applications suchas image rejection mixers, I/Q (de)modulators. At present,the flip-flop (frequency divider) based quadrature genera-tion is a popular method [1]. However, the drawback ishigher frequency VCO operation and poor phase error ac-curacy. The poly-phase filter is another quadrature signalgeneration circuit [2], where the drawback is the signal at-tenuation, and this leads to the addition of a power-hungrybuffer and a large chip size. The quadrature oscillator (QO)has been considered as another attractive solution which in-volves the coupling of two differential

Analysis and Design of Passive Polyphase Filters

Passive RC polyphase filters (PPFs) are analyzed in detail in this paper. First, a method to calculate the output signals of an n-stage PPF is presented. As a result, all relevant properties of PPFs, such as amplitude and phase imbalance and loss, are calculated. The rules for optimal pole frequency planning to maximize the image-reject ratio provided by a PPF are given. The loss of PPF is divided into two factors, namely the intrinsic loss caused by the PPF itself and the loss caused by termination impedances. Termination impedances known a priori can be used to derive such component values, which minimize the overall loss. The effect of parasitic capacitance and component value deviation are analyzed and discussed. The method of feeding the input signal to the first PPF stage affects the mechanisms of the whole PPF. As a result, two slightly different PPF topologies can be distinguished, and they are separately analyzed and compared throughout this paper. A design example is given to demonstrate the developed design procedure.

A 0.6–2.7 GHz Semidynamic Frequency Divide-by-3 Utilizing Wideband RC Polyphase Filter in 0.18 $\mu$m CMOS

A wideband complementary metal oxide semiconductor (CMOS) semidynamic frequency divide-by-3 covering more than two octave bandwidths is presented. The wideband operation without requiring a quadrature signal source is realized by employing a three-stage RC polyphase filter. The transfer function analysis on Type-II two- and three-stage polyphase filters is performed to provide analytic solutions of the peak phase error and peak attenuation. Implemented in 0.18 mum CMOS, the divide-by-3 operates over the input frequency range between 0.6 and 2.7 GHz while dissipating 15 mA from a 1.8 V supply.

Polar format agorithm using chirp scaling for spotlight SAR image formation

A novel implementation of the polar format algorithm (PFA) using the principle of chirp scaling (PCS) for spotlight synthetic aperture radar (SAR) image formation is addressed. A PFA completely free of interpolation has been achieved in moderate squinted imaging geometry. The presented approach consists of the range and azimuth scaling of the polar samples, in which only fast Fourier transforms (FFTs) and complex vector multiplications are involved. Following different processing chains, the dechirped and the chirped SAR signals are treated separately in this paper. Relative to the classic polyphase filter that uses the long sinc kernel, the new solution is able to attain a comparable result, but is much quicker by exploiting inherent properties of the linear frequency modulated (LFM) signal. Point target simulation has validated the presented methodology.

Integrated VCOs for Medical Implant Transceivers

The 402–405 MHz medical implant communication service (MICS) band has recently been allocated by the US Federal Communication Commission (FCC) with the potential to replace the low-frequency inductive coupling techniques in implantable devices. This band was particularly chosen to provide full-integration, low-power, faster data transfer, and longer communication range. This paper investigates the design of a voltage-controlled oscillator (VCO) that will be an essential building block of such wireless implantable devices operating in the MICS service band. Three different integrated quadrature VCOs that meet the requirements of the MICS standard are designed in 0.18 μm TSMC CMOS process to propose an optimum choice. Their performances in terms of power consumption, die area, linearity, and phase noise are compared. The fabricated VCOs are a four-stage differential ring VCO, an LC tank VCO directly loaded with a poly-phase filter, and an 800 MHz LC tank VCO with a high-frequency master-slave divider. All three architectures target a VCO gain of Kvco = 15 MHz/V with 3 calibration control and 2 frequency-shift keying (FSK) control signals and are designed for 1.5 V supply voltage in a 0.18-μm standard CMOS process.

A Very Wideband Active RC Polyphase Filter with Minimum Element Value Spread Using Fully Balanced OTA Based on CMOS Inverters

This paper presents a very wideband active RC polyphase filter (ARCPF). We propose a unit section of the ARCPF, which is an ordinary RCPF followed by opamps with parallel RC feedback. In the proposed unit section, pole and zero can be assigned independently. By using the unit ARCPFs, a very wideband image rejection filter can be realized by cascading the sections, which can greatly reduce the element value spread. To realize this, CMOS inverter based fully differential OTA which can operate under low supply voltage is also presented. This paper describes a six-stage active RC polyphase filter with 1-100 MHz passband in 0.18μm CMOS technology.

소수분주비를 갖는 광대역 가변 능동 주파수 분주기 마이크로파 집적 회로

A semidynamic frequency divide-by-1.5 MMIC comprises a tunable polyphase filter, tunable image-rejection mixer, and a static divide-by-2 in the feedback path. Wideband suppression of unwanted tones is achieved by employing a tunable image-rejection mixer and a tunable single-stage polyphase filter. Implemented in GaInP/GaAs HBT technology, the divide-by-1.5 MMIC operates over the input frequency range of 4.5 to 9.2 GHz with better than -20 dBc suppressions of tones, while dissipating 29 mA from 4.1 V supply.

A 5.2 GHz 47 dB Image Rejection Double Quadrature Gilbert Downconverter Using 0.35 m SiGe HBT Technology

A 5.2 GHz 1 dB conversion gain, IP1 dB = -19 dBm and IIP3 = -9 dBm double quadrature Gilbert downconversion mixer with polyphase filters is demonstrated by using 0.35 μm SiGe HBT technology. The image rejection ratio is better than 47 dB when LO=5.17 GHz and IF is in the range of 15 MHz to 45 MHz. The Gilbert downconverter has four-stage RC-CR IF polyphase filters for the image rejection. Polyphase filters are also used to generate LO and RF quadrature signals around 5 GHz in the double quadrature downconverter.