Polymorphic Gates Research Articles

Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications

Various hardware security concerns, such as hardware Trojans and IP piracy, have sparked studies in the security field employing alternatives to CMOS chips. Spintronic devices are among the most-promising alternatives to CMOS devices for applications that need low power consumption, non-volatility, and ease of integration with silicon substrates. This article looked at how hardware can be made more secure by utilizing the special features of spintronics devices. Spintronic-based devices can be used to build polymorphic gates (PGs), which conceal the functionality of the circuits during fabrication. Since spintronic devices such as magnetic tunnel junctions (MTJs) offer non-volatile properties, the state of these devices can be written only once after fabrication for correct functionality. Symmetric circuits using two-terminal MTJs and three-terminal MTJs were designed, analyzed, and compared in this article. The simulation results demonstrated how a single control signal can alter the functionality of the circuit, and the adversary would find it challenging to reverse-engineer the design due to the similarity of the logic blocks’ internal structures. The use of spintronic PGs in IC watermarking and fingerprinting was also explored in this article. The TSMC 65nm MOS technology was used in the Cadence Spectre simulator for all simulations in this work. For the comparison between the structures based on different MTJs, the physical dimension of the MTJs were kept precisely the same.

Satisfiability Attack-Resistant Camouflaged Two-Dimensional Heterostructure Devices.

Reverse engineering (RE) is one of the major security threats to the semiconductor industry due to the involvement of untrustworthy parties in an increasingly globalized chip manufacturing supply chain. RE efforts have already been successful in extracting device level functionalities from an integrated circuit (IC) with very limited resources. Camouflaging is an obfuscation method that can thwart such RE. Existing work on IC camouflaging primarily involves transformable interconnects and/or covert gates where variation in doping and dummy contacts hide the circuit structure or build cells that look alike but have different functionalities. Emerging solutions, such as polymorphic gates based on a giant spin Hall effect and Si nanowire field effect transistors (FETs), are also promising but add significant area overhead and are successfully decamouflaged by the satisfiability solver (SAT)-based RE techniques. Here, we harness the properties of two-dimensional (2D) transition-metal dichalcogenides (TMDs) including MoS2, MoSe2, MoTe2, WS2, and WSe2 and their optically transparent transition-metal oxides (TMOs) to demonstrate area efficient camouflaging solutions that are resilient to SAT attack and automatic test pattern generation attacks. We show that resistors with resistance values differing by 5 orders of magnitude, diodes with variable turn-on voltages and reverse saturation currents, and FETs with adjustable conduction type, threshold voltages, and switching characteristics can be optically camouflaged to look exactly similar by engineering TMO/TMD heterostructures, allowing hardware obfuscation of both digital and analog circuits. Since this 2D heterostructure devices family is intrinsically camouflaged, NAND/NOR/AND/OR gates in the circuit can be obfuscated with significantly less area overhead, allowing 100% logic obfuscation compared to only 5% for complementary metal oxide semiconductor (CMOS)-based camouflaging. Finally, we demonstrate that the largest benchmarking circuit from ISCAS'85, comprised of more than 4000 logic gates when obfuscated with the CMOS-based technique, is successfully decamouflaged by SAT attack in <40 min; whereas, it renders to be invulnerable even in more than 10 h when camouflaged with 2D heterostructure devices, thereby corroborating our hypothesis of high resilience against RE. Our approach of connecting material properties to innovative devices to secure circuits can be considered as a one of a kind demonstration, highlighting the benefits of cross-layer optimization.

Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks

Untrusted foundries pose threats of integrated circuit (IC) piracy and counterfeiting, and this has motivated research into logic locking. Strong logic locking approaches potentially prevent piracy and counterfeiting by preventing unauthorized replication and use of ICs. Unfortunately, recent work has shown that most state-of-the-art logic locking techniques are vulnerable to attacks that utilize Boolean Satisfiability (SAT) solvers. In this article, we extend our prior work on using silicon nanowire (SiNW) field-effect transistors (FETs) to produce obfuscated ICs that are resistant to reverse engineering attacks, such as the sensitization attack, SAT and approximate SAT attacks, as well as tracked signal attacks. Our method is based on exchanging some logic gates in the original design with a set of polymorphic gates (PLGs), designed using SiNW FETs, and augmenting the circuit with a small block, whose output is untraceable, namely, URSAT. The URSAT may not offer very strong resilience against the combined AppSAT-removal attack. Strong URSAT is achieved using only CMOS-logic gates, namely, S-URSAT. The proposed technique, S-URSAT + PLG-based traditional encryption, designed using SiNW FETs, increases the security level of the design to robustly thwart all existing attacks, including combined AppSAT-removal attack, with small penalties. Then, we evaluate the effectiveness of our proposed methods and subject it to a thorough security analysis. We also evaluate the performance penalty of the technique and find that it results in very small overheads in comparison to other works. The average area, power, and delay overheads of implementing 64 baseline key-bits of S-URSAT for small benchmarks are 5.03%, 2.60%, and −2.26%, respectively, while for large benchmarks they are 2.37%, 1.18%, and −1.93%.

Design of the RRAM-Based Polymorphic Look-Up Table Scheme

The polymorphic gates are the circuit cells that deliver different functions with the different external input, supply voltage or temperature. It is an effective method to resist the reverse engineering attacks, for the attackers cannot distinguish the correct function based on the netlist of the circuit. The researchers have found out that the RRAM based Look-Up Table (LUT) has higher performance and less area, comparing with the CMOS based counterparts. However, the attackers can tell the functions of the previous proposed RRAM based LUTs by measuring the resistance states of the RRAM cells. This work proposes an RRAM based polymorphic gate, which implements 16 basic logic functions with 8 RRAM cells in 4 working cycles. Furthermore, the multi-input LUT scheme is proposed based on the polymorphic gate. It is difficult for the attackers to distinguish the circuit function, because the function of the LUT is determined by the applied voltages and the resistance states of the RRAM devices, and the n-input LUT circuit is implemented with the constant area regardless of the number of inputs.

Emerging Technology-Based Design of Primitives for Hardware Security

Hardware security concerns such as intellectual property (IP) piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this article, emerging technologies are investigated by leveraging their unique properties for applications in the hardware security domain. Security, for the first time, will be treated as one design metric for emerging nano-architecture. Five example circuit structures including camouflaging gates, polymorphic gates, current/voltage-based circuit protectors, and current-based XOR logic are designed to show the high efficiency of silicon nanowire FETs and graphene SymFET in applications such as circuit protection and IP piracy prevention. Simulation results indicate that highly efficient and secure circuit structures can be achieved via the use of non-CMOS devices.

A Matching Outputs Approach to Evolutionary Design of Polymorphic Self-Checking Circuits

In order to solve the problem of losing optimum structure in the stage of fitness evaluation, a matching outputs approach to evolutionary design of polymorphic self-checking circuits is proposed in this paper. By adding NOT gate to outputs of the candidate circuits, the fitness and the diversity of the population are increased when the matching degree of the output is lower than 1/2. The experiments of evolutionary design for 1-bit self-checking adder are conducted by combining the polymorphic gates with conventional gates. Experimental results show that the proposed method can detect all the stuck-at-faults. The generation of evolution is decreased by 28% to 32% compared with ordinary method in designing polymorphic self-checking circuits. The proposed method enjoys advantages of faster convergence and less iteration.

Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit

A unique unclonable chip ID has been implemented using various platforms in the recent years. In this paper, we investigate the use of polymorphic gates as a new mechanism for implementing a unique chip ID in systems already containing some polymorphic gates. The proposed solution exploits the fact that switching time of polymorphic gates (controlled by V dd ) is slightly different even for neighboring gates on the same die because of fabrication variations. We applied a partial reconfiguration in order to generate 48-bit IDs on the reconfigurable polymorphic REPOMO32 chip that we have developed in our previous research. We achieved 94.44% stable bits which is reasonably close to existing approaches. DOI: http://dx.doi.org/10.5755/j01.itc.42.1.925

On the completeness of the polymorphic gate set

Polymorphic gates are special kinds of logic gates that can exhibit different functions under the control of environmental parameters, such as light, temperature, and VDD. These polymorphic gates can be used to build polymorphic circuits that perform different functions under different environments. Because polymorphic gates are different from traditional logic gates, the existent completeness theory for the traditional logic gate set is not suitable for the polymorphic gate set. So far, only the definition of the complete polymorphic gate set is given. There is no approach to judging whether a given polymorphic gate set is complete. The contributions of this article include three aspects. First, the impact of logic-1 and logic-0 on the completeness of the polymorphic gate set is discussed. Second, the theory and two related algorithms for judging the completeness of polymorphic gate sets with two modes are given. Finally, the theory and related algorithms for complete polymorphic gate sets with more than two modes are proposed.

Designing polymorphic circuits with polymorphic gates: a general design approach

A general design approach to design polymorphic circuits with polymorphic gates is proposed. These polymorphic circuits can adaptively adjust their functionalities with the changes of the electrical characteristics of components induced by the change of environment. The single function circuits that can work correctly and maintain their functionalities in different environments can be regarded as a special kind of polymorphic circuits. The general design approach for these circuits is proposed, and based on this approach, the general design approach to designing polymorphic circuits is also proposed. It is proved that a polymorphic circuit with any two different functions in two different environments can be implemented with a complete polymorphic gate set, and a definition on the gate set is given and the completeness is also discussed. Finally, these general design approaches are analysed and some experiments are performed to demonstrate their efficiency.