Polysilicon Electrodes Research Articles

A Novel High-Speed Split-Gate Trench Carrier-Stored Trench-Gate Bipolar Transistor with Enhanced Short-Circuit Roughness.

A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times.

Strain Engineering in Si Split-Gate Trench Power MOSFETs by Partial Oxidation of Polysilicon Electrodes

Performance improvement of Si split-gate trench power MOSFETs due to conventional scaling is approaching a physical and economical limit. Strain engineering, however, enables enhanced device characteristics without the need for further shrinkage as a result of an increased charge carrier mobility in monocrystalline Si. In this work, thermally grown SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathbf {2}}$ </tex-math></inline-formula> functional strain layers are introduced into a state-of-the-art Si trench power MOSFET by partial oxidation of the source and gate electrode. The influence of the additional SiO2 layers on the strain distribution in monocrystalline Si is described by the thermomechanical (TM) strain simulation and the resulting device properties are assessed by means of detailed electrical analysis. For the strain-modified devices, the simulation shows higher longitudinal tensile strains in the direction of current flow and stronger out-of-plane compressive strains perpendicular to it, which have a beneficial effect on the electron mobility. The electrical characterization revealed improved ON-state resistances at gate voltages of 4.5 V ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ON}4.5$ </tex-math></inline-formula> ) and 10 V ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ON}10$ </tex-math></inline-formula> ) of up to 16.8% and 13.8%, respectively, while the breakdown voltage did not change. In the presence of the SiO2 layer in the gate electrode, the threshold voltage was reduced, which also contributed to the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ON}$ </tex-math></inline-formula> improvement. The functional strain layer in the gate electrode mainly influences the mobility in the channel, while it primarily alters the mobility in the drift region when introduced into the source electrode. However, the modification of mechanical strain in the channel area shows less impact on the overall device performance compared to the drift region.

X-ray nanodiffraction analysis of residual stresses in polysilicon electrodes of vertical power transistors

The influence of residual stress concentrations on the mechanical stability and functional properties of vertical power transistors is not fully understood. In this work, residual stresses are analyzed in two polycrystalline Si electrodes using synchrotron X-ray nanodiffraction and finite element (FE) modeling. Diffraction scanning was performed over 42 transistors with a step size of 100 nm and the data were subsequently averaged in order to compensate for relatively poor diffraction statistics. The experiment revealed compressive in-plane and out-of-plane stresses of -185 to -225 MPa and -65 to -95 MPa, respectively, in the lower electrode and equiaxial tensile stresses of 70 to 150 MPa in the upper electrode, which appear to be dependent on doping and increase proportionally from compressive to tensile with the electrodes’ dimensions and grain size. The results are interpreted in terms of processing route and correlated with the FE simulation. The comparison shows overall good agreement for in-plane and out-of-plane residual stresses but indicates a limitation of the FE stress simulation regarding the impact of doping and grain size effects.

Silicon Carbide-Gated Nanofluidic Membrane for Active Control of Electrokinetic Ionic Transport.

Manipulation of ions and molecules by external control at the nanoscale is highly relevant to biomedical applications. We report a biocompatible electrode-embedded nanofluidic channel membrane designed for electrofluidic applications such as ionic field-effect transistors for implantable drug-delivery systems. Our nanofluidic membrane includes a polysilicon electrode electrically isolated by amorphous silicon carbide (a-SiC). The nanochannel gating performance was experimentally investigated based on the current-voltage (I-V) characteristics, leakage current, and power consumption in potassium chloride (KCl) electrolyte. We observed significant modulation of ionic diffusive transport of both positively and negatively charged ions under physical confinement of nanochannels, with low power consumption. To study the physical mechanism associated with the gating performance, we performed electrochemical impedance spectroscopy. The results showed that the flat band voltage and density of states were significantly low. In light of its remarkable performance in terms of ionic modulation and low power consumption, this new biocompatible nanofluidic membrane could lead to a new class of silicon implantable nanofluidic systems for tunable drug delivery and personalized medicine.

A split-gate trench IGBT with low Miller capacitance and dV/dt noise

A novel trench insulated gate bipolar transistor (IGBT) with a split-gate structure is proposed herein, where the polysilicon electrode in the trench is divided into two parts and insulated by the polysilicon oxide, thus decreasing the overlap between the gate electrode and n-drift region. Due to this split-gate structure, much lower Miller capacitance can be achieved. The performance of the proposed split-gate IGBT device, in particular the turn-on dV/dt controllability, is discussed. The simulation results show that the proposed split-gate IGBT can achieve a much better tradeoff between the maximum reverse-recovery dVKA/dt of the free-wheeling diode and the turn-on loss (Eon) of the IGBT compared with the conventional IGBT design. The reverse-recovery dVKA/dt can be decreased by 56% at the same Eon as in the IGBT. Moreover, a feasible manufacturing process for the split-gate structure is proposed.

Silicon Nanofluidic Membrane for Electrostatic Control of Drugs and Analytes Elution.

Individualized long-term management of chronic pathologies remains an elusive goal despite recent progress in drug formulation and implantable devices. The lack of advanced systems for therapeutic administration that can be controlled and tailored based on patient needs precludes optimal management of pathologies, such as diabetes, hypertension, rheumatoid arthritis. Several triggered systems for drug delivery have been demonstrated. However, they mostly rely on continuous external stimuli, which hinder their application for long-term treatments. In this work, we investigated a silicon nanofluidic technology that incorporates a gate electrode and examined its ability to achieve reproducible control of drug release. Silicon carbide (SiC) was used to coat the membrane surface, including nanochannels, ensuring biocompatibility and chemical inertness for long-term stability for in vivo deployment. With the application of a small voltage (≤ 3 V DC) to the buried polysilicon electrode, we showed in vitro repeatable modulation of membrane permeability of two model analytes—methotrexate and quantum dots. Methotrexate is a first-line therapeutic approach for rheumatoid arthritis; quantum dots represent multi-functional nanoparticles with broad applicability from bio-labeling to targeted drug delivery. Importantly, SiC coating demonstrated optimal properties as a gate dielectric, which rendered our membrane relevant for multiple applications beyond drug delivery, such as lab on a chip and micro total analysis systems (µTAS).

Performance analysis of electrostatic plasma-based dopingless nanotube TFET

In this paper, the nanotube electrostatic plasma-based tunnel field-effect transistor (EP-NTTFET) has been proposed. The use of external bias on the side contacts of the source/drain region helps in the induction of charge carriers even with the use of the polysilicon electrode. The analog parameters are studied such as OFF-current, ON-current, ION/IOFF, sub-threshold slope, threshold voltage, transconductance, TGF, cut-off frequency and DIBL with channel length (LC), Nanotube radius (TSi) and Source voltage (VS) variation. The channel length (LC) varies from 10 to 50 nm, OFF-current varies from 3.79 × 10–13 A/um to 6.79 × 10–19 A/um, sub-threshold slope improves from 36.88 mV/decade to 9.6 mV/decade and ION/IOFF current ration improves from the order of 107 to 1013. The nanotube radius (TSi) varies from 3.5 nm to 12 nm, so ON-current varies from 2.6 × 10–5 A/um to 4.78 × 10–5 A/um, OFF-current increases and sub-threshold slope increases from 18.28 mV/decade to 26.9 mV/decade. The source voltage (VS) varies from – 0.2 V to – 1.2 V, so ON-current varies from 7.88 × 10–6 A/um to 3 × 10–5 A/um, OFF-current increases from 6.5 × 10–19 A/um to 2.25 × 10–15 A/um, sub-threshold slope improves from 24.84 mV/decade to 20.83 mV/decade and threshold voltage decreases from 0.36 V to 0.25 V. To reduce the thermal budget with simple fabrication steps and lower random dopant fluctuations (RDFs) electrostatics plasma-based nanotube TFET is used. The proposed device EP-NTTFET provides higher ON current, higher ION/IOFF current ratio, better sub-threshold slope, and lower threshold voltage.

Microsacle PolySilicon Hemispherical Shell Resonating Gyroscopes with Integrated Three-dimensional Curved Electrodes

A novel approach for fabrication of polysilicon hemispherical resonator gyroscopes with integrated 3-D curved electrodes is developed and experimentally demonstrated. The 3-D polysilicon electrodes are integrated as a part of the hemispherical shell resonator’s fabrication process, and no extra assembly process are needed, ensuring the symmetry of the shell resonator. The fabrication process and materials used are compatible with the traditional semiconductor process, indicating the gyroscope has a high potential for mass production and commercial development. Without any trimming or tuning of the n=2 wineglass frequencies, a 28 kHz shell resonator demonstrates a 0.009% frequency mismatch between two degenerate wineglass modes, and a 13.6 kHz resonator shows a frequency split of 0.03%. The ring-down time of a fabricated resonator is 0.51 s, corresponding to a Q of 22000, at 0.01 Pa vacuum and room temperature. The prototype of the gyroscope is experimentally analyzed, and the scale factor of the gyro is 1.15 mV/°/s, the bias instability is 80 °/h.

Чувствительность матриц ПЗС с электронным умножением

The sensitivity and basic electrical characteristics of the developed direct illumination matrices with charge-coupled devices and electronic multiplication were investigated at room temperatures and low illumination. Photomatrices of 576´288 and 640´512 format were designed using frame transfer architecture and 1.5-µm design rules with photosensitive cell sizes of 20´30 and 16´16 µm, respectively, and manufactured using n-channel technology with buried channel, four levels of polysilicon electrodes and two levels of metallization. To analyze the possibilities of the developed EMCCD matrices used in monitoring systems at low-light conditions, an experimental assessment of the matrices sensitivity was carried out. The assessment was based on a comparison of the luxmeter readings and Johnson's criteria using the standard 1951 USAF resolution target test table for the minimum size of line pairs distinguished by the observer (one pair consists of a dark and a light lines). The characteristics obtained with illumination of 5∙10–4 lux (glow of the starry sky with light clouds) and 10–2 lux (glow of the starry sky and the quarter of the Moon) corresponds to the parameters of generation 2+ electron-optical converters, which implies the possibility to use such matrices in night vision devices. At Åv ≈ 5∙10–4 lux, the camera with the developed EMCCD matrices will detect a human figure at the distance of about 200 m. With illumination of 10–2 lux at this distance a human figure can be identified.

Reliability Analysis of LPCVD SiN Gate Dielectric for AlGaN/GaN MIS-HEMTs

In this paper, we investigate Low Pressure Chemical Vapor Deposition (LPCVD) SiN as a gate isolation material for AlGaN/gallium nitride (GaN) MIS-high electron mobility transistor power transistors. We compared the dielectric failure by forward-biased constant-current stress time-dependent dielectric breakdown measurements and statistical Weibull analysis. Several 4” AlGaN/GaN-on-Si wafers have been processed with different gate isolations and processes. Our investigation includes the dependence of the dielectric breakdown on the process flow (influence of dry etch), the thickness of the dielectric (12–20 nm), the area scaling, and the gate electrode, where we also consider the recently presented poly-silicon electrode. Additionally, we show the influence of the current density through the gate on the charge-to-breakdown characteristics as well as the influence of the temperature on the breakdown behavior. Using the poly-silicon electrode and 20 nm LPCVD SiN as gate isolation, we achieved a charge-to-breakdown of ${Q}_{\text {BD, 10}~\text {mA}/\text {cm}^{2}} ={3.7} ~ \text {kC}/\text {cm}^{{2}}$ at $\text {T} = {130} {^{\circ }}\text {C}$ for ${j} = {10} ~ \text {mA}/\text {cm}^{{2}}$ . A 20-years lifetime (100 ppm, $\text {T} = {130} {^{\circ }}\text {C}$ ) extrapolation for a scaled area of ${0.2} ~ \text {mm}^{{2}}$ ( $\buildrel \wedge \over = {W}_{G} = {100} ~ \text {mm}$ ) leads to a positive gate voltage of ${V}_{\text {G}} = {9.4} ~ \text {V}$ .

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77–300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Electrostatic tuning in linear regime for 25.9-MHz micromechanical resonator with 120-nm capacitive gap

In this paper, electrostatic tuning in the linear regime for a high-frequency single-crystal silicon resonator is investigated. An electrostatic actuated I-shaped bulk acoustic resonator (IBAR) is fabricated in our experiment owing to its advantage of a large electrode area. The single-crystal silicon resonator is actuated by electrostatic force. The electrostatic force is improved by reducing the capacitive gap to 120 nm. The fabrication of the capacitive gap is based on the process for a high-aspect-ratio self-aligned stepped polysilicon electrode for a single-crystal silicon microstructure. The effective stiffness of an IBAR is softened by increasing the bias voltage, which is applied between the polysilicon electrodes and the resonant structure. For the tuning frequency in the linear regime, the ac actuation voltage is small to avoid electrical nonlinearity. The resonant frequency of the IBAR is measured to be 25.9 MHz in a vacuum. The temperature coefficient of frequency (TCF) of our device is approximately −14 ppm/ °C, which is attained by boron doping. When the resonator operates in the linear regime, frequency tuning can achieve 1833 ppm over 130 °C by changing the bias voltage from 2 to 23 V at room temperature. The temperature drift of the full operating range of a high-frequency resonator is compensated by electrostatic tuning for the first time.

Study on the mechanism of a charge-coupled device detector irradiated by millisecond pulse laser under functional loss.

The damage mechanism of a CCD detector was studied by building an experimental system containing a millisecond pulse laser irradiating a CCD detector. The experimental results show that the damage on the CCD detector was mainly thermal damage, along with mechanical damage. A melting phenomenon was caused by the thermal damage, so that a crater was observed on the surface of the CCD detector. Caused by melting of the polysilicon electrodes and a temperature rise in the silicon dioxide, the shift register impedance values were sharply reduced. Most of the substrate clock signals were broken and disappeared due to melting of channels in the silicon substrate layer, which caused a functional loss for the CCD detector. The mechanical damage on the melting edge of the CCD detector created heave; the temperature gradient caused this damage. In this paper, the decrease in vertical shift register impedance values was consistent with previous test results.

Fabrication of high aspect ratio self-aligned stepped polysilicon electrode for single-crystal silicon microstructure

This paper reports a self-aligned process for the fabrication of a high aspect ratio stepped polysilicon electrode with sub-micron capacitive gaps, which increases the coupling factor in capacitive driving and sensing. In contrast to the previous works, the polysilicon electrodes, which are formed by refilling the trenches and etching back, are anchored on the surfaces of steps in the trenches and etched by two-step deep reactive ion etching. The polysilicon electrodes are self-aligned and perfectly symmetric. Because of the `U'-shaped profile produced by the refilling process, the polysilicon electrode is less sensitive to a stress gradient in Low-pressure chemical vapor deposition (LPCVD) polysilicon layer. A thin layer of heavily doped polysilicon and a low-stress polysilicon layer, instead of uniform, heavily doped polysilicon, are used to form the polysilicon electrodes without sacrificing the electrical performance, which decreases the deposition time for LPCVD significantly due to the much faster deposition of normal low-stress polysilicon. To validate the study, a single-crystal silicon length extensional mode resonator with a 300-nm capacitive gap is fabricated based on this process. The frequency of the resonator is measured to be 25.5955 MHz, with a quality factor of 67,656 under 20 Pa.

A Core-Displacement Method Tunable Inductor using Micro-Electro-Mechanical-Systems Technology

In this paper, we introduce a new electrostatic tunable inductor with a simple tuning mechanism employing Micro-Electro-Mechanical-Systems. The proposed structure consists of a spiral inductor, a NiFe core material which is attached to a polysilicon support and electrodes of the electrostatic actuation. The inductance tuning mechanism is based on core-displacement and skin effect. When the electrostatic voltage is applied, the core is moved up and distance between the inductor and the core is increased, so magnetic stored energy of inductor is changed and hence the inductance tuning is achieved. The structure is simulated employing finite element method software such as COMSOL and ANSOFT HFSS. According to electromagnetic and electrostatic simulation results, a 69% tuning range at the frequency of 8 GHz and a quality factor of 13.3 has been achieved which is very suitable for RF applications. The simulation results show an electrostatic actuation voltage of the 25.3 V for the designed structure.

(Invited) Electrical Characterization and Reliability Assessment of Double-Gate FinFETs

The performance and reliability of doped and undoped (100)<100> and (110)<110> sidewall silicon-on-insulator (SOI) FinFETs with an Hf-based gate dielectric were evaluated. The electron mobility of the (110) FinFET sidewall is comparable to the (100) FinFET sidewall devices, which is opposite of the typical planar MOSFET electron mobility dependence on orientation, wherein (110) degrades significantly. In addition, TiN metal gate-induced strain cannot completely explain the similarity in (110) and (100) electron mobility because, although lower in magnitude, the two orientations with polysilicon electrodes resulted in similar mobility values. When investigating the orientation dependence of negative bias temperature instability (NBTI), (110) was found to cause more degradation than (100), and FinFETs with higher fin body doping demonstrated even more degradation.

Less than 10-nm Gap Silicon and Polysilicon Electrodes for Sensing pH and Yeast Concentration

Less than 10-nm Gap Silicon and Polysilicon Electrodes for Sensing pH and Yeast Concentration

Fabrication process for CMUT arrays with polysilicon electrodes, nanometre precision cavity gaps and through-silicon vias

Capacitive micromachined ultrasound transducers (CMUTs) can be used to realize miniature ultrasound probes. Through-silicon vias (TSVs) allow for close integration of the CMUT and read-out electronics. A fabrication process enabling the realization of a CMUT array with TSVs is being developed. The integrated process requires the formation of highly doped polysilicon electrodes with low surface roughness. A process for polysilicon film deposition, doping, CMP, RIE and thermal annealing that resulted in a film with sheet resistance of 4.0 Ω/□ and a surface roughness of 1 nm rms has been developed. The surface roughness of the polysilicon film was found to increase with higher phosphorus concentrations. The surface roughness also increased when oxygen was present in the thermal annealing ambient. The RIE process for etching CMUT cavities in the doped polysilicon gave a mean etch depth of 59.2 ± 3.9 nm and a uniformity across the wafer ranging from 1.0 to 4.7%. The two presented processes are key processes that enable the fabrication of CMUT arrays suitable for applications in for instance intravascular cardiology and gastrointestinal imaging.

Recent progress in ab initio simulations of hafnia-based gate stacks

The continuous size downscaling of complementary metal–oxide–semiconductor (CMOS) transistors has led to the replacement of SiO2 with a HfO2-based high dielectric constant (or high-k) oxide, and the polysilicon electrode with a metal gate. The approach to this technological evolution has spurred a plethora of fundamental research to address several pressing issues. This review focusses on the large body of first principles (or ab initio) computational work employing conventional density functional theory (DFT) and beyond-DFT calculations pertaining to HfO2-based dielectric stacks. Specifically, structural, thermodynamic, electronic, and point-defect properties of bulk HfO2, Si/HfO2 interfaces, and metal/HfO2 interfaces are covered in detail. Interfaces between HfO2 and substrates with high mobility such as Ge and GaAs are also briefly reviewed. In sum, first principles studies have provided important insights and guidances to the CMOS research community and are expected to play an even more important role in the future with the further optimization and “scaling down” of transistors.

Improvement of RRAM Device Performance Through On-Chip Resistors

ABSTRACTResearch in non-volatile memories (NVM) has intensified in the past few years due to the ever increasing demand for information storage and the near ubiquity of handheld electronics. Resistive memory is a leading contender in this NVM market due to its high endurance, random accessibility, scalability and low programming voltage.The addition of an external series resistor or imposing current compliance is often used to limit the current through RRAM devices and to prevent “over-programming” and stuck-at-one (SA1) errors. Here, we demonstrate that utilizing an external series resistor is not efficient in preventing over-programming and an on-chip resistor is more desirable.Poly-silicon bottom electrode based devices (with the poly-silicon electrode acting like an on-chip resistor) and metal bottom electrode devices were fabricated and tested. The presence of the on-chip resistor is shown to enhance the endurance of the RRAM device. This technique of including an on-chip resistor prevents stored current discharge through the device as the device transitions from a high resistance to a low resistance state. A SPICE simulation is also employed to illustrate the benefit of this approach.