poly-Si Thin-film Transistors Research Articles

Polycrystalline silicon thin-film transistor utilizing self-assembled monolayer for crystallization

Crystallization employing an N-(2-aminoethyl)-3-aminopropyltrimethoxysilane self-assembled monolayer (AEAPS-SAM) to coordinate Ni metal catalyst was found to produce large grain poly-Si. A small concentration of Ni could be deposited controllably onto an AEAPS-SAM covered with Si by immersing it in Ni solution for 1–60min. Larger grains and a lower Ni concentration in the poly-Si could be obtained by shorter immersion. Immersion for 1min produced grains, as large as 47μm and a Ni concentration as low as 7.4×1018atoms/cm3. A poly-Si thin-film transistor fabricated with AEAPS-SAM poly-Si of 1min immersion had a field-effect mobility of 98cm2/(Vs), which is one order of magnitude higher than that of a thin-film transistor fabricated without the AEAPS-SAM treatment.

Schottky Barrier Controlled Conduction in Poly-Si TFTs With Metal Source and Drain

Two types of poly-Si thin-film transistors (TFTs) with the source (S) and drain (D) regions replaced by Al-metal-replaced junction TFT and self-aligned metal electrode (SAME) TFT-are characterized. Their IV characteristics are explained with a unified transport model based on the Schottky barriers at channel ends. Channel current is the sum of hole- and electron-current, which are limited by carrier injection via thermal emission or tunneling across the hole- and electron-barrier formed between poly-Si channel and metal S/D, respectively. The observed temperature dependence of transfer characteristics agrees well with the model. For SAME TFTs, barrier height of carrier transport is found to be modulated by a doped interfacial layer between the intrinsic poly-Si channel and Al electrodes at channel ends. By modulating the hole- and electron-barrier, three different types of device behaviors, such as p-type, n-type, and ambipolar TFTs can be obtained. Correlation between the doping effect and subthreshold swing and ON-state current, as well as channel length-dependent characteristics, are revealed.

Thermal Sensor Using Poly-Si Thin-Film Transistors With Self-Aligned and Offset Gate Structures

We propose a thermal sensor using poly-Si thin-film transistors (TFTs) with self-aligned and offset gate structures. First, the temperature dependences of the transistor characteristic are compared between the self-aligned and offset TFTs. It is found that both the TFTs have the temperature dependence of the off-leakage current, whereas the off-leakage current of the self-aligned TFT is larger than that of the offset TFT. Next, the self-aligned and offset TFTs are included in a cell circuit to detect the temperature utilizing the off-leakage current, which is composed of a pair of 1-transistor and 1-capacitor. It is found that low and high temperatures can be detected using the self-aligned and offset TFTs, respectively. We think that it is promising to integrate this thermal sensor in certain applications using TFTs.

Meyer–Neldel Rule for Effective Channel Mobility in the Subthreshold Region of Poly-Si Thin-Film Transistors

It is verified that the entire subthreshold region of poly-Si thin film transistors (TFTs) is a pseudo-subthreshold region dominated by drift current, where the carrier effective channel mobility is found to follow the Meyer–Neldel rule (MNR). Characteristic MN energies extracted from both metal-induced laterally crystallized poly-Si TFTs and excimer laser annealed TFTs are all close to the optical phonon energy of Si, providing strong evidence to the MNR. Carrier thermionic emission over grain boundary barriers activated by multiphonon absorption process is the origin of the MNR.

Channel Width Splitting Effect on Driving Characteristics of Silicide Seed-Induced Laterally Crystallized Poly-Si Thin-Film Transistors

The electrical performance of low-temperature polycrystalline silicon thin-film transistors (TFTs) is greatly affected by structures such as channel geometry, lightly doped drain, film thickness, etc. In this paper, the split channel polycrystalline silicon TFTs are fabricated through the silicide seed induced lateral crystallization method by dividing channel width with fixed numerical channel size. The number of channels splitting from 1 to 10 significantly improves driving characteristics such as driving current, field-effect mobility, subthreshold slope, and threshold voltage. It is found that the two main causes of improvements are the enlargement of effective channel width and a decrease in series resistance due to the crystal filtering effect on narrowly split channels, which lead to trap-state density reduction during lateral crystal growth. The causes of enlarged effective channel width and the decreased series resistance by the crystal filtering effect are demonstrated through capacitance-voltage and trap-state density extraction.

Impact of the Hydrogenation Process on the Performance of Self-Aligned Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors

We investigated hydrogenation of low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) from the point of view of the gettering phenomenon, specifically, using self-aligned metal double-gate p-channel LT poly-Si TFTs that had a small subthreshold swing value and a high field-effect mobility. Hydrogenation of TFTs was carried out by forming gas annealing. Our results indicate that the conventionally used hydrogenation temperature of 400 °C is considerably high because annealing at this temperature results in the re-emission of gettered hydrogen. Moreover, when annealing in forming gas, hydrogenation actually occurs during cooling from 400 °C, but not at 400 °C. The most important parameter for effective hydrogenation is the rate of cooling from 400 °C, but not the hydrogenation temperature of 400 °C.

Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness

N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C-V characterization, the ionized dopant concentration in the channel is determined to be around 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and the fixed charge density to be around -6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding.

Analytical Drain Current Model for Poly-Si Thin-Film Transistors Biased in Strong Inversion Considering Degradation of Tail States at Grain Boundary

This paper presents an analytical hot-carrier effect model for n-channel poly-Si thin-film transistors biased in strong inversion based on degradation of tail states at grain boundary near drain after stress. Via a stress-time-dependent tail state model, the degradation of tail state distribution and drain current after stress could be predicted as verified by the experiment data. Based on this model, both the tail state density and the characteristic decay energy of the tail state distribution in the damaged region increase with the stress time, which determine the degradation of the drain current.

Evaluation of Thermal Annealing Before and After Formation of Gate Insulator Films by Extracting Trap Densities for SPC Poly-Si TFTs

We have evaluated the effects of thermal annealing before formation of gate insulator films (preannealing) and thermal annealing after formation of gate insulator films (postannealing) by extracting trap densities for solid-phase crystallized poly-Si thin-film transistors. It is suggested that the preannealing densifies the poly-Si films and induces additional internal stress after the thermal oxidation of the gate insulator films. On the other hand, the postannealing also relieves the internal stress. These conflicting effects indicate that the order of the thermal annealing is very important to improve device performance.

Effect of nickel concentration on source/drain series resistance and channel resistance of Ni-metal-induced crystallization thin-film transistors

The Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been employed to fabricate low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Most studies have focused only on reducing Ni contamination because Ni residues cause high leakage current in MIC–TFTs. Also of concern is the source/drain (S/D) series resistance, which degrades the device performance (driving ability) that might vary with the Ni concentration in MIC–TFTs. Improving the driving ability of MIC–TFTs requires a detailed understanding of how Ni residues affect S/D series resistance. This study investigates how Ni concentration affects S/D series resistance by using the transmission line method. The results of this study provide further insight into how Ni concentration and resistance are related. The results show that the S/D series resistance and channel resistance decreased with a reduction in Ni concentration in MIC poly-Si because of better crystalline quality and lower degradation of the donor concentration. This phenomenon was caused by the Ni concentration forming less NiSi2 nucleation sites to generate a large grain size; Ni atoms serve as acceptor-like dopants in silicon, which counteract with the effects of n-type doping, subsequently reducing the donor concentration in the S/D region.

Self-Aligned Planar Metal Double-Gate Polycrystalline-Silicon Thin-Film Transistors Fabricated at Low Temperature on Glass Substrate

A multigate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) is a recently popular topic in the field of Si devices. In this study, self-aligned planar metal double-gate poly-Si TFTs consisting of an embedded bottom metal gate, a top metal gate fabricated by a self-alignment process, and a lateral poly-Si film with a grain size greater than 2µm were fabricated on a glass substrate at 550°C. The nominal field-effect mobility of an n-channel TFT is 530cm2/Vs, and its subthreshold slope is 140mV/dec. The performance of the proposed TFTs is superior to that of top-gate TFTs fabricated using equivalent processes.

Degradation of Polycrystalline Silicon TFT CMOS Inverters under AC Operation

Degradation of polycrystalline silicon (poly-Si) thin-film transistor (TFT)-based CMOS inverters under AC operation is studied. Based on a previous drain current model of poly-Si TFTs including the kink effect, the voltage transfer characteristics of both fresh and stressed inverters are well described. It is determined that hot carrier of the n-TFT and negative bias temperature instability of the p-TFT are competing degradation mechanisms controlling the observed two-stage degradation of the inverter. Based on such mechanisms, degradation of inverter under various AC operation conditions can be qualitatively predicted. It is found that under given frequency and amplitude of the input pulse voltage, inverter's degradation can still be effectively suppressed by increasing the pulse falling time, and/or decreasing the low voltage duration.

Analysis of the current conduction in poly-Si thin film transistors

The current conduction in polycrystalline silicon thin film transistors is analyzed in weak inversion, partially weak and strong inversion, and strong inversion regions. These operation regions can be determined from the dependence of the surface potential on the gate voltage under various channel potentials. In each different operation region, the source of the current conduction is analyzed based on the surface potential under the different channel potentials by some simple formulas. In comparison with other works and the calculated current components—the diffusion and drift current in the strong inversion, the current conduction is verified for both fully and partially depleted devices. It is found that the diffusion current dominates in the weak inversion region. Both diffusion and drift currents are important in the partially weak and strong inversion region. In the strong inversion region, the current conduction is determined by the drift component. It yields a new way to analyze the current conduction in polycrystalline silicon thin film transistors.

An Experimental Study of Block-Oxide Source/Drain-Tied Polycrystalline-Silicon Thin-Film Transistors With Additional Polycrystalline-Silicon Body

This paper presents an experimental comparison of the block-oxide (BO) source/drain-tied (SDT) (BOSDT) polycrystalline-silicon (poly-Si) thin-film transistor (poly-Si TFT) with additional poly-Si body (APSB) against the zero-BO (ZBO) SDT (ZBOSDT) poly-Si TFT with APSB. The APSB scheme is created when the isolation process takes place after annealing of the source/drain regions. The experimental results show the superior electrical characteristics of the BOSDT-APSB poly-Si TFT over the ZBOSDT-APSB poly-Si TFT. The BO scheme is indeed useful in reducing the source and drain charge sharing. Although the ZBOSDT-APSB poly-Si TFT exhibits worse electrical properties, the combination of a ZBO (a buried oxide layer only under the poly-Si body) with an APSB can still be used to keep diminishing the charge-sharing effect. Furthermore, both devices can increase the cooling capability through their source/drain-tied structure.

Low-Operating-Voltage Ultrathin Junctionless Poly-Si Thin-Film Transistor Technology for RF Applications

In this letter, for the first time, we experimentally investigate the radio-frequency (RF) characteristics and low-frequency noise (LFN) of n-type planar junctionless (JL) poly-Si thin-film transistors (TFTs). The fabricated JL devices show remarkable dc performance with good current drive and a high on-current/off-current ratio of 8 × 107. Furthermore, with the implementation of an in situ phosphorus-doped channel architecture and a salicide process, the JL device with a channel length of 0.4 μm exhibits a cutoff frequency (ft) of 3.36 GHz and a maximum oscillation frequency (fmax) around 7.37 GHz at a drain bias of 2 V. As far as LFN is concerned, the JL device shows approximately four orders of magnitude lower drain-current noise power spectral density (Sid) over conventional inversion-mode counterparts. These results demonstrate that the JL poly-Si TFT technique is promising for RF modules implemented in system-on-panel applications.

High-Performance Polycrystalline-Silicon Nanowire Thin-Film Transistors With Location-Controlled Grain Boundary via Excimer Laser Crystallization

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) are demonstrated using excimer laser crystallization to control the locations of grain boundaries two-dimensionally. Via the locally increased thickness of the amorphous-silicon (a-Si) film as the seeds, the cross-shaped grain boundary structures were produced among these thicker a-Si grids. The NW TFTs with one primary grain boundary perpendicular to the channel direction could be therefore fabricated to achieve an excellent field-effect mobility of 346 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s and an on/off current ratio of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> . Furthermore, the grain-boundary-location-controlled NW TFTs also exhibited better reliability due to the control of grain boundary locations. This technology is thus promising for applications of low-temperature poly-Si TFTs in system-on-panel and 3-D integrated circuits.

다결정 실리콘 박막 트랜지스터를 이용한 0.5μm 급 SONOS 플래시 메모리 소자의 개발 및 최적화

본 연구에서는 0.5 ㎛ 급 다결정 실리콘 박막 트랜지스터를 제작하고 이를 최적화 했다. 실험 결과, 비정질 실리콘을 증착 후 저온 어닐링을 통해 보다 큰 grain 크기를 가지는 active 영역을 형성하는 것이 소자의 SS(Subthreshold Swing), DIBL(Drain Induced Barrier Lowering), 그리고 on-current의 성능 향상을 가져온다는 것을 확인 할 수 있었다. 또한 이를 바탕으로 SONOS 플래시 메모리를 제작하였으며 그 특성을 분석했다. 게이트로부터 전자의 back tunneling 현상을 억제함과 동시에 제작한 소자가 원활한 program/erase 동작을 하기 위해서는 O/N/O 두께의 최적화가 필요하다. 따라서 시뮬레이션을 통해 이를 분석하고 O/N/O 두께를 최적화 하여 SONOS 플래시 메모리의 특성을 개선하였다. 제작한 소자는 2.24 V의 threshold voltage(Vth) memory window를 보였으며 메모리 동작을 잘 하는 것을 확인 할 수 있었다.

Performance improvement with a combined scheme of rapid thermal annealing and multi-channel structure for poly-Si TFTs with various device dimensions

This study presents a combined scheme of rapid thermal annealing (RTA) and multi-channel structure for improving the performance of polycrystalline silicon (poly-Si) thin film transistors (TFTs). Results show that RTA treatment can improve device performance by decreasing the number of in-grain defects and improving the quality of the gate oxide. The multi-channel structure improves the electrical characteristics of the poly-Si TFTs by decreasing the number of grainboundary defects. Thus, the combined scheme can effectively reduce defect states and improve the gate-oxide’s quality simultaneously, resulting in a significant improvement in the performance of poly-Si TFTs. In addition, the performance improvement is particularly apparent for the TFTs with a thinner gate oxide and smaller channel length. Therefore, the proposed scheme is a good candidate for improving the electrical characteristics of TFTs for use in small-to-medium size displays.

Self-Heating and Kink Effects in SLS Single-Crystal-Like Nanowire Transistors

In this paper, the electrical characteristics of sequential-lateral-solidification (SLS) single-crystal-like nanowire (NW) poly-Si thin-film transistors (TFTs) with various gate structures are compared and comprehensively studied. The self-heating and kink effects of all SLS TFT devices with various gate structures are analyzed. Owing to the nanoscale nitride hard mask, each NW is easily transformed within one crystalline grain of the SLS poly-Si film with the regularly arranged grains; thus, each NW performs with a single-crystal-like device channel. Therefore, NW-type SLS TFTs with gate-all-around (GAA) and trigated (TRI) structures exhibit better electrical characteristics as compared with the conventional planar SLS TFTs. At moderate VGS and VDS biases, GAA devices exhibit better electrical characteristics. However, the self-heating effect and the local electric fields located at three sharp corners result in the severe degradation of electrical characteristics for GAA-SLS TFTs operated or stressed at high VGS and VDS biases.

High Mobility P-Channel Thin-Film Transistors with Ultralarge-Grain Polycrystalline Silicon Formed Using Nickel-Induced Crystallization

In this study, p-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using an active layer of ultralarge-grain (ULG) silicon and multistack gate insulators of SiNx/SiO2 were fabricated and investigated. The ULG silicon thin films were formed by nickel (Ni)-induced crystallization and the average grain area of ULG silicon is 118 µm2. The field-effect mobility of p-channel ULG poly-Si TFTs was 111 cm2/(V·s), which can be sufficiently applied to high driving parts of display systems. The p-channel ULG poly-Si TFT has a low threshold voltage of -1.06 V, a high ON/OFF current ratio of 9.2×107, and a subthreshold swing of 0.27 V/decade. Moreover, the fabricated TFTs have stable characteristics under temperature and gate bias stress owing to the large grains and smooth surface. These results show that the ULG poly-Si TFTs are remarkably suitable for the application to a low power and high speed pixel-driving device in flat panel displays.