poly-Si Thin-film Transistors Research Articles

Threshold voltage uniformity improvement by introducing charge injection tuning for low-temperature poly-Si thin film transistors with metal/oxide/nitride/oxide/silicon structure

Low-temperature poly-Si thin film transistors (TFTs) with a metal/oxide/nitride/oxide/silicon structure were fabricated to investigate the feasibility of suppressing threshold voltage variations between TFTs. By applying relatively high positive and negative gate bias voltages, threshold voltage could be tuned positively and negatively, respectively, by injecting charges into the charge trap layer. Stability of threshold voltage against positive gate bias at a level close to the actual circuit operation was not degraded compared with the case of an as-fabricated TFT. A uniform threshold voltage distribution could be achieved in a preliminary test using 16 TFTs by converging threshold voltages with a target value by tuning the threshold voltage for each TFT.

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Indium Zinc Oxide Nanosheet Transistor With 2 nm Channel Thickness for Monolithic Three-Dimensional Integrated Circuit

We have successfully fabricated an amorphous indium zinc oxide (a-IZO) thin film transistor (TFT) with a 2 nm-thick nanosheet channel, which demonstrated an impressive mobility of 84 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V-s. By shrinking the channel length and width, the a-IZO TFT exhibited a high drain current density of 1.6 mA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 1V, a sharper subthreshold swing of 72 mV/dec, and better drain-induced barrier lowering (DIBL) of 94 mV/V. By integrating p-type low-temperature poly-Si (LTPS) TFT and n-type a-IZO TFT, we have designed a heterogeneous complementary inverter that can achieve a high voltage gain of 99 V/V, while consuming only a few picowatts of power at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1.5 V. All thermal budgets used in this study are compatible with the back-end-of-line (BEOL) process, making it a suitable approach for fabricating monolithic three-dimensional integrated circuits (M3D-ICs).

Fine-Tunable Emission Pulse Generation Circuit Based on p-Type Low-Temperature Poly-Si Thin-Film Transistors for Active Matrix Organic Light-Emitting Diode Displays

Active matrix organic light-emitting diode (AMOLED) displays have deployed the compensation techniques to cope with the luminance non-uniformity issues caused by variations on electrical characteristics of thin-film transistors (TFTs). While some compensation circuits require control signals of longer pulse widths than a line time, the luminance control as well as the higher bit depth representation have been also accomplished by adjusting the pulse widths. A proposed EM pulse generation circuit consists of 11 p-type low-temperature poly-Si (LTPS) TFTs and a one coupling capacitor. While previous tunable circuits could address pulse widths of either even or odd multiples of a line time, the proposed circuit can generate any multiples by changing phases of additional clock signals. In particular, the internal inverter is implemented with a load connected to the output of a previous stage’s inverter to reduce the power consumption over pulse widths. The coupling capacitor is also connected between two adjacent stages through one TFT, eliminating coupling noises on the output pulses. The proposed EM circuit is simulated at a line time of 3.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> s for a 120 Hz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{3840}$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{2160}$</tex-math> </inline-formula> display. The results ensure that pulse widths from three to 2160 lines are generated successfully without coupling noises and the small variation on power consumption from 1.23 to 0.33 mW is achieved at 30 stages for the whole range of pulse widths, compared to the large range from 1.26 to 76.91 mW with the inverter of a diode-connected load.

Heterogeneous Integration of Atomically-Thin Indium Tungsten Oxide Transistors for Low-Power 3D Monolithic Complementary Inverter.

In this work, the authors demonstrate a novel vertically-stacked thin film transistor (TFT) architecture for heterogeneously complementary inverter applications, composed of p-channel polycrystalline silicon (poly-Si) and n-channel amorphous indium tungsten oxide (a-IWO), with a low footprint than planar structure. The a-IWO TFT with channel thickness of approximately 3-4 atomic layers exhibits high mobility of 24 cm2 V-1 s-1 , near ideally subthreshold swing of 63mV dec-1 , low leakage current below 10-13 A, high on/off current ratio of larger than 109 , extremely small hysteresis of 0mV, low contact resistance of 0.44 kΩ-µm, and high stability after encapsulating a passivation layer. The electrical characteristics of n-channel a-IWO TFT are well-matched with p-channel poly-Si TFT for superior complementary metal-oxide-semiconductor technology applications. The inverter can exhibit a high voltage gain of 152V V-1 at low supply voltage of 1.5V. The noise margin can be up to 80% of supply voltage and perform the symmetrical window. The pico-watt static power consumption inverter is achieved by the wide energy bandgap of a-IWO channel and atomically-thin channel. The vertically-stacked complementary field-effect transistors (CFET) with high energy-efficiency can increase the circuit density in a chip to conform the development of next-generation semiconductor technology.

Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain

We report detailed fabrication and characterization of poly-Si thin-film transistors (TFTs) with T-shaped gate (T-gate) and lightly-doped drain (LDD) structures. The formation of the LDD underneath the wings of a T-gate primarily relies on the shadowing of implanted dopants during the implantation of source and drain. Therefore, the fabrication of LDD structures in our proposed T-gate poly-Si TFTs can save a number of process steps as compared to conventional poly-Si TFTs with LDD structures. Our fabricated T-gated poly-Si TFTs with LDD structures not only exhibit suppressed off-state leakage current but also show a significant improvement in on-state current as compared to that of conventional poly-Si TFTs with the same top-gate dimension.

(Invited, Digital Presentation) Evaluation of Polycrystalline-Si1-XGex Thin-Film Transistors Grown Laterally on a Glass Substrate Using a Continuous-Wave Laser

System-on-glass requires high-performance thin-film transistors (TFTs). In order to realize high-performance polycrystalline-Si (poly-Si) TFTs, we grew high-quality poly-Si thin films using a continuous-wave solid-state laser, in a method known as continuous-wave laser lateral crystallization (CLC). The grain boundary (G.B.) of CLC poly-Si is characterized by being parallel to the laser scan direction with shape of nearly straight line. Ge-based devices are attractive because of the superior carrier mobility of Ge in comparison to Si; however, as carriers in poly-Ge thin film are high concentration of hole generated from defects, it is difficult to control the level of doping. Moreover, fabrication of stable gate dielectric GeO2 is highly challenging. Addition of Ge to Si is expected to improve carrier mobility in Si, leading to poly-Si1-xGex TFTs with better performance than conventional poly-Si TFTs. Hence, our work here is a step in that direction. The purpose of this study is to understand the performance of poly-Si1-xGex TFTs, and to highlight the issues pertaining to poly-Si1-xGex thin films by comparing the performance of poly-Si1-xGex TFTs with that of poly-Si TFTs.A typical TFT fabrication process is as follows. An amorphous Si1-xGex thin film (~100 nm) with a Ge concentration of 10% is grown on a quartz substrate. After cleaning the substrate surface with hydrogen fluoride solution, CLC is carried out in air without substrate heating, followed by the preparation of transistor islands using reactive ion etching (RIE). A 50-nm-thick SiO₂ film is deposited by plasma enhanced chemical vapor deposition (PECVD), followed by heat treatment in nitrogen atmosphere at 550 °C for 4 h and deposition of Mo film as the top gate. Next, P or BF₂ is ion-implanted into poly-Si1-xGex for source-drain (SD) respectively, at 10 keV and 3×1015 cm-2. After ion implantation is completed, interlayer dielectric SiO2 film is deposited by PECVD and activated by heating in nitrogen atmosphere at 550 °C for 6 h. Subsequently, contact holes and Mo electrodes are formed. Finally, hydrogenation using step-cooling is performed to complete the TFT. N-channel (n-ch) and P-channel (p-ch) poly-Si TFTs are also fabricated using identical processes. Two types of TFTs were fabricated for both poly-Si1-xGex TFTs and poly-Si TFTs: one with the G.B. lying parallel to the SD direction (parallel type) and the other with the G.B. perpendicular to the SD direction (perpendicular type).The transfer characteristics of n-ch TFTs showed that the threshold voltages (Vth) of poly-Si1-xGex shifted in the positive direction in comparison with those of poly-Si TFTs. The mobility and sub-threshold swing (s.s.) values of poly-Si1-xGex were inferior to those of poly-Si TFTs, for both the parallel and perpendicular types.Considering the p-ch TFTs, the transfer characteristics of parallel poly-Si1-xGex TFTs showed higher OFF current and lower ON current than the corresponding poly-Si TFTs. In case of perpendicular types, OFF currents of poly-Si1-xGex TFTs were comparable with that of poly-Si TFTs and ON currents of poly-Si1-xGex TFTs were lower than those of poly-Si TFTs. Moreover, Vth values of poly-Si1-xGex TFTs were shifted in the positive direction in comparison to those of poly-Si TFTs, for both parallel and perpendicular types.The segregation coefficient of Ge in Si is less than 1.0, and it has been shown that Ge segregates to G.B.s in poly-Si1-xGex thin films during solidification. As acceptors are generated in regions with high Ge concentration along G.B.s, p-type quasi-one-dimensional conduction regions were formed in Si1-xGex along G.B.s. Therefore, when SD regions are parallel to a G.B., a current path connecting those regions is formed along G.B.s in p-type poly-Si1-xGex TFTs, leading to enhancement of OFF current. However, when G.B.s lie perpendicular to SD regions, the latter remain unconnected, leading to normal OFF current values.The positive shift in Vth of poly-Si1-xGex TFTs can be explained by the formation of acceptors. It can also be concluded that the decrease of ON current in poly-Si1-xGex TFTs is due to ionized impurity scattering by the acceptors. In addition, the difference in the magnitude of ON current depending on the G.B. direction can be explained as follows: when G.B.s are parallel to the SD direction, ON current is higher than that of the perpendicular type, because G.B.s do not act as strong scattering centers.In summary, the characteristics of CLC poly-Si1-xGex TFTs can be explained by the formation of acceptors. In particular, the large OFF current in parallel p-ch poly-Si1-xGex TFTs is explained by Ge segregation along G.B.s, resulting in formation of quasi-one-dimensional p-type conduction channels and electrical connection between SD region.

(Invited) Oxide TFT Applications: Principles and Challenges

The main advantage of the thin film transistor (TFT) is that it can be fabricated on non-wafer substrate independent of the size, flexibility, and morphology. All composing films of the TFT are deposited at the low temperature. Therefore, TFTs can be applied to a broad range of consumer, biological, chemical, and optical products that are difficult to fabricate with the wafer based MOSFETs.There are many reports on a-Si:H and poly-Si TFT applications in displays, imagers, sensors, drivers, flexible electronics, and circuits (1,2). In principle, oxide TFTs can be applied to similar products. However, since the device characteristics and compositing materials of the oxide TFT are different from those of the a-Si:H and poly- Si TFTs, as shown in Figure 1 and Table 1, there are advantages and disadvantages in former’s applications. In this presentation, oxide TFT applications in the following three areas will be discussed. Control of the attached device, such as pixel-driving in displays,Integrated circuits, such as drivers or inverters, andChanging of characteristics with environment, such as pH, optical, and temperature sensors. L. Antonuk, Chapt. 10, and Y. Kuo, Chapt. 11, Amorphous Silicon Thin Film Transistors, pp. 395-505, Kluwer Academic Publishers, 2004.B.-D. Choi, et al., Chapt. 11-13, Polycrystalline Silicon Thin Film Transistors, Y. Kuo Editor, pp. 360-495, Kluwer Academic Publishers, 2004.Kuo and G. W. Chang, ECS Trans, 64(10), 145-153 (2014). Figure 1

(Digital Presentation) Degradation and Recovery of Low Temperature Poly-Si Thin Film Transistors Under DC and AC Bias Stresses

The low temperature poly-Si thin-film transistors (LTPS TFTs) have been extensively applied in the AMLCD and AMOLED due to their high carrier’s mobility and driving currents, and the ability to integrate the driving circuits onto the same substrate. The main mechanisms causing the degradation of the LTPS TFTs under bias stress are: hot carrier effect and self-heating effect. In this study, the degradation and recovery phenomena of the LTPS TFTs stressed by the hot carrier effect conditions would be systematically investigated. The device structures used in this study are n-channel LTPS TFTs with different lengths of lightly doped drain (LDD).First, we simultaneously apply a small positive DC voltage, approximately the threshold voltage plus 1V (Vth+1= +3 V), to the gate terminal and a large positive DC voltage (+12 V) to the drain terminal of the LTPS TFTs with three different LDD’s lengths. These stressing conditions would cause the TFTs operated in the saturation region, so that the channel is pinched off. And the electrons would be accelerated by a large transverse electric field when they drift from the source terminal to the drain one. The energetic electrons would impact the lattices of the channel and the interface between the gate dielectric and the channel near the drain terminal, causing the defect states and electron-hole pair generation. Few of the carriers with enough energy to overcome the energy barrier of gate dielectric would be trapped by the defects in it. The hot carrier effect causes the degradation of the TFTs devices, including the decrease of ON current and carrier mobility and the increase of OFF current, but less degradation of the threshold voltage and subthreshold swing. After the bias stressing, the resting time is added to investigate the recovery phenomena. The difference in the amount of degradation and the location of defects would cause the different recovery ratio. After the end of bias stressing, all of the terminals are not applied with any voltages in the resting periods. The electrons and holes generated in the channel near the drain terminal would recombine, and the defect states generated by the hot carrier impact slightly reduce, which causes the recovery phenomena of the degraded transistors.Then, we apply a small AC voltage (0 ~ +3 V) to the gate terminal and a large positive DC voltage (+12 V) to the drain one at the same time. This mode of bias stressing conditions is closer to the real operating mode of the TFTs in the driving circuits. From the experimental data, it could be found that there is no significant difference in the degradation of the TFTs under different frequency of AC signals applied on the gate. But the recovery ratio tends to gradually increase as the frequency increasing.Finally, a small positive DC voltage (+3 V) is applied to the gate terminal, and a large AC voltage (0 ~ +12 V) to the drain one at the same time. From the experimental data, it could be found that with the increase of AC signal frequency, the degradation of the TFTs decreases, but the recovery ratio of the TFTs increases due to the reduction of the effective stressing time in one period. As compared to the results of all stressing conditions, the TFTs, both of the gate and drain terminals applied with DC voltages, exhibit the largest degradation ratio but the least recovery one. However, the TFTs, as the gate terminal applied with DC voltages and drain one with AC voltage, exhibit the less degradation ratio but the largest recovery one.

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V ds of 5.0 V is suppressed, whereas the drain leakage current at V ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.

(Digital Presentation) Degradation and Recovery of Low Temperature Poly-Si Thin Film Transistors Under DC and AC Bias Stresses

The degradation and recovery phenomena of n-type LTPS TFTs stressed at hot carrier effect region under various bias conditions are investigated. The devices with longer LDD’s length demonstrate less degradation ratio but more recovery ratio, because of the lower transverse electric field. As the AC signals are applied to the gate terminal, the degradation of devices shows no significant dependence of AC signal frequency, but the recovery ratio displays the similar trends as AC signal frequency changing. However, as the AC signals are applied to the drain terminal, the degradation of devices shows very significant dependence of AC signal frequency. The higher the AC signal frequency is, the less degradation the devices show, but the recovery ratio displays the similar trends as AC signal frequency changing. From the results of all stressing conditions, the LTPS TFTs stressed with DC voltages exhibit the largest degradation ratio but almost the least recovery one.

Blue laser diode annealing-enhanced bottom-gate low-temperature Poly-Si thin-film transistors

The low-temperature poly-Si (LTPS) thin-film transistor (TFT) with bottom-gate architecture was successfully developed using the blue laser diode annealing (BLDA) technology. The amorphous silicon (a-Si) was successfully recrystallized by BLDA into LTPS with grain sizes ranging from 0.1 μm to 0.3 μm. With the proper pre-dehydration treatment of a-Si and optimized BLDA conditions, the bottom-gate LTPS TFTs achieved superior performance than a-Si TFTs, including a mobility up to 15.87 cm2/Vs. Moreover, such BLDA-enabled bottom-gate LTPS TFT is fully compatible with the incumbent a-Si production line, thus providing a new cost-efficient technology for large-area electronics.

Binary-Synaptic Plasticity in Ambipolar Ni-Silicide Schottky Barrier Poly-Si Thin Film Transistors Using Chitosan Electric Double Layer.

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH3COO− and OH−) and cations (H+) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems.

Study on Residual Image in Low-Temperature Poly-Si Oxide TFT-Based OLED Display on Polyimide Substrate

We study the reduction in residual image in low-temperature poly-Si oxide (LTPO) thin-film transistor (TFT)-based flexible organic light-emitting diode (OLED) displays on polyimide (PI) substrate. Conventional voltage compensation circuit (seven TFTs plus one capacitor) is used with modification of driving and some switching TFTs. The measurement results on the threshold-voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{TH}}$ </tex-math></inline-formula> ) shift and SPICE simulation data on the pixel circuits indicate that the residual image is due to the PI charging effect when a single-gate coplanar poly-Si TFT is used as driving one. It is shown here that adding a bottom electrode to the coplanar poly-Si driving TFT (D-TFT) eliminates the residual image by shielding the poly-Si active layer from the PI charging effect.

Synergy effect of microwave annealing and high-pressure hydrogen annealing on Poly-Si thin-film transistor

Grain boundary (GB) is a significant factor that deteriorates the transfer characteristics of poly-Si thin-film transistors (TFTs). In this study, we utilized the synergistic effect of microwave annealing (MWA) and high-pressure hydrogen annealing (HPHA) to effectively reduce grain boundary trap (GBT) density, resulting in improved field-effect mobility (μ) and subthreshold swing (SS). To investigate the synergistic effect of MWA and HPHA, the transfer characteristics of rapid thermal annealing and forming gas annealing devices were compared and analyzed as control devices. Furthermore, the mechanism of SS and mobility enhancement can be quantitatively understood by lowering the GB barrier height. In addition, Raman spectroscopy proved that poly-Si crystallinity was improved during MWA. Our results showed that MWA and HPHA play a vital role in reducing GBT density and improving poly-Si TFT characteristics.

A high-gain two-stage amplifier using low-temperature poly-si oxide thin-film transistors with a Corbino structure

This paper proposes a complementary metal–oxide–semiconductor (CMOS) amplifier using low-temperature poly-Si oxide (LTPO) thin-film transistors (TFTs). The Corbino structure used in the proposed amplifier has a higher output resistance than conventional amplifiers. The proposed circuit is composed of two CMOS inverters, one CMOS switch, and one input capacitor. It was possible to determine the operating point where the voltage gain could be kept high, regardless of the device variation, by shorting the gate input and output of the first amplifier. The alternating current component of the input signal was increased because the input signal was transferred to the first amplifier via the capacitor. The function of the second amplifier was to increase the total voltage gain. When a peak-to-peak voltage sine wave of 2 mV was applied at a frequency lower than 500 Hz, the proposed circuit showed an average voltage gain of 60.6 dB, which is the highest among the previously published TFT amplifiers.

Compact Integration of Hydrogen–Resistant a–InGaZnO and Poly–Si Thin–Film Transistors

The low–temperature poly–Si oxide (LTPO) backplane is realized by monolithically integrating low–temperature poly–Si (LTPS) and amorphous oxide semiconductor (AOS) thin–film transistors (TFTs) in the same display backplane. The LTPO–enabled dynamic refreshing rate can significantly reduce the display’s power consumption. However, the essential hydrogenation of LTPS would seriously deteriorate AOS TFTs by increasing the population of channel defects and carriers. Hydrogen (H) diffusion barriers were comparatively investigated to reduce the H content in amorphous indium–gallium–zinc oxide (a–IGZO). Moreover, the intrinsic H–resistance of a–IGZO was impressively enhanced by plasma treatments, such as fluorine and nitrous oxide. Enabled by the suppressed H conflict, a novel AOS/LTPS integration structure was tested by directly stacking the H–resistant a–IGZO on poly–Si TFT, dubbed metal–oxide–on–Si (MOOS). The noticeably shrunken layout footprint could support much higher resolution and pixel density for next–generation displays, especially AR and VR displays. Compared to the conventional LTPO circuits, the more compact MOOS circuits exhibited similar characteristics.

Statistical Study of Degradation of Flexible Poly-Si TFTs Under Dynamic Bending Stress

Degradation of flexible low-temperature poly-Si thin film transistors (TFTs) under dynamic bending cycles is investigated with statistical method. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ ON}}$ </tex-math></inline-formula> degradation data of different bending cycles and bending conditions are compared to five different statistical distribution models, and it is determined that the Gamma distribution best fits degradation data. Based on the model, the reliability of TFTs under a given stress condition can be evaluated under two typical application scenarios: (1) reliability prediction for large bending cycles; (2) reliability evaluation based on stress test with limited sample size.

A polylogarithmic model for thin-film transistors used in a CMOS inverter amplifier

This article presents a generalization of a transregional polylogarithmic model, previously proposed for continuously describing the transfer characteristics of polycrystalline and amorphous Thin Film Transistors (TFTs) at all levels of inversion. The present generalization entails including the necessary drain voltage dependencies to be able to describe also the output characteristics. The model is tested by using it in the design and analysis of a CMOS inverter amplifier consisting of poly-Si n- and p-channel TFTs fabricated at low temperature and pressure. The transistors are biased below threshold so that the CMOS amplifier circuit operates in weak conduction, having in mind energy saving considerations. The validity of the proposed model has been ascertained by comparing model simulations to actual measured data from individual poly-Si TFTs and from the CMOS amplifier circuit. The simulations of the CMOS inverter amplifier are compared to the results obtained using look-up table-type simulations.

New Low-Frame-Rate Compensating Pixel Circuit Based on Low-Temperature Poly-Si and Oxide TFTs for High-Pixel-Density Portable AMOLED Displays.

A new low-frame-rate active-matrix organic light-emitting diode (AMOLED) pixel circuit with low-temperature poly-Si and oxide (LTPO) thin-film transistors (TFTs) for portable displays with high pixel density is reported. The proposed pixel circuit has the excellent ability to compensate for the threshold voltage variation of the driving TFT (ΔVTH_DTFT). By the results of simulation based on a fabricated LTPS TFT and a-IZTO TFT, we found that the error rates of the OLED current were all lower than 2.71% over the range of input data voltages when ΔVTH_DTFT = ±0.33 V, and a low frame rate of 1 Hz could be achieved with no flicker phenomenon. Moreover, with only one capacitor and two signal lines in the pixel circuit, a high pixel density and narrow bezel are expected to be realized. We revealed that the proposed 7T1C pixel circuit with low driving voltage and low frame rate is suitable for portable displays.