poly-Si Nanowire Channels Research Articles

Enhanced Synaptic Behaviors in Chitosan Electrolyte-Based Electric-Double-Layer Transistors with Poly-Si Nanowire Channel Structures.

In this study, we enhance the synaptic behavior of artificial synaptic transistors by utilizing nanowire (NW)-type polysilicon channel structures. The high surface-to-volume ratio of the NW channels enables efficient modulation of the channel conductance, which is interpreted as the synaptic weight. As a result, NW-type synaptic transistors exhibit a larger hysteresis window compared to film-type synaptic transistors, even within the same gate voltage sweeping range. Moreover, NW-type synaptic transistors demonstrate superior short-term facilitation and long-term memory transition compared with film-type ones, as evidenced by the measured paired-pulse facilitation and excitatory post-synaptic current characteristics at varying frequencies and pulse numbers. Additionally, we observed gradual potentiation/depression characteristics, making these artificial synapses applicable to artificial neural networks. Furthermore, the NW-type synaptic transistors exhibit improved Modified National Institute of Standards and Technology pattern recognition rate of 91.2%. In conclusion, NW structure channels are expected to be a promising technology for next-generation artificial intelligence (AI) semiconductors, and the integration of NW structure channels has significant potential to advance AI semiconductor technology.

Reliability of p-Type Pi-Gate Poly-Si Nanowire Channel Junctionless Accumulation-Mode FETs

In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated and their reliability was investigated. The reliability of these PG JAM FETs was found to be dependent on the effective channel doping concentration (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> ). Through a negative gate bias stress (NGBS) test, we found that degradation in the average subthreshold swing (A.S.S.) and shift in the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) increases as the N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> of the PG JAM FETs decreases. Furthermore, the PG JAM FETs with a lower N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> show the more severe rate of deterioration in the transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) and ON current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ). By increasing N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> to reduce the electric field ( E-field) on the gate oxide and tune the carrier transport mechanism in the poly-Si nanowire channel, a better immunity against the NGBS test in the p-type PG JAM FETs can be achieved under a gate overdrive voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GOD</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH,initial</sub> = -3.5 V) to perform the NGBS test.

Enhanced Operation Characteristics in Poly-Si Nanowire Charge-Trapping Flash Memory Device With SiGe Buried Channel

Operation characteristics in a polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory device are studied with SiGe buried channel for the first time. Compared with the flash device with a general poly-Si NW channel, the device with SiGe buried channel shows improved programming and erasing speeds since the enhanced electric field in tunneling layer is enhanced by SiGe buried layer. The endurance characteristics are also improved by the SiGe buried channel while retention performances are retained. The SiGe buried channel is promising to CT flash device for 3D nonvolatile memory applications.

Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels

A novel gate-all-around (GAA) poly-Si floating-gate (FG) memory device with triangular nanowire (NW) channels was fabricated and characterized in this work. The enhanced electric field around the corners of the NW channels boosts more electrons tunneling through the tunnel oxide layer during programming and erasing (P/E) processes, and thus the operation voltage markedly decreases. Furthermore, the nonlocalized trapping feature characteristic of the FG makes the injection of electrons easier during the programming operation, which was demonstrated by technology computer-aided design (TCAD) simulations.

A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer

Hf-based charge-trapping (CT) layers, including HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and HfAlO, were employed in the fabrication of a CT-type memory with gate-all-around (GAA) poly-Si nanowire channels. It is shown that the GAA configuration can greatly enhance the programming/erasing efficiency as compared with the conventional planar scheme. It is also shown that the incorporation of Al into the dielectric can further improve the retention and endurance characteristics over the counterparts with a HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> trapping layer. Retardation of the recrystallization of the dielectric film with Al incorporation is postulated to be responsible for these observations.

A Novel Scheme for Fabricating CMOS Inverters With Poly-Si Nanowire Channels

A novel complementary metal-oxide-semiconductor inverter with poly-Si nanowire channels is proposed and demonstrated in this letter. The scheme employs a clever tilted-angle implant process in the fabrication; therefore, the formation of the source and drain of both p-channel and n-channel devices requires only one lithographic step. The fabricated n-channel and p-channel field-effect transistors in the inverters show a high ON/OFF current ratio, an acceptable subthreshold swing, and a symmetric driving current, thus enabling the realization of excellent characteristics of the inverters.

Performance Enhancement of Thin-Film Transistors With Suspended Poly-Si Nanowire Channels by Embedding Silicon Nanocrystals in Gate Nitride

In this letter, we fabricated and characterized thin-film transistors with a suspended poly-Si nanowire (NW) channel and gate nitride with embedded silicon nanocrystals (Si NCs). The embedded Si NCs increase the surface roughness, thus reducing the adhesive force as the nitride is in contact with the poly-Si NW channel during the operation. Such a feature results in a reduction in pull-in voltage and sharper pull-out behavior. Moreover, this approach also greatly improves the endurance characteristics of the devices.

High-Performance Poly-Si Nanowire Thin-Film Transistors Using the $\hbox{HfO}_{2}$ Gate Dielectric

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) using hafnium dioxide as gate dielectric is successfully fabricated for the first time. The excellent short-channel characteristics are attributed to the high- gate dielectric, ultrathin poly-Si NW channel thickness, and omega-shaped gate structure. The record high driving capability of 549 results from the ultrashort gate length , thin equivalent oxide thickness, and Ni silicide metal source/drain. This letter reveals the opportunity of high-performance poly-Si TFT circuits for system-on-panel and 3-D integrated circuit (3-D IC) applications.

Operation of a Novel Device With Suspended Nanowire Channels

We investigate the operation of a new device featuring a side-gate scheme and suspended poly-Si nanowire (NW) channels. The fabrication adopted a sidewall-spacer-etching technique to form the poly-Si NW channels. The NW channels were further suspended using a simple wet-etching step. An interesting hysteresis phenomenon is observed in the I-V characteristics. In addition, a steep subthreshold swing (< 60 mV/dec) is also observed in the transfer curves. A scenario is proposed to explain the operation of such a device.

A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of single- gate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at Vd = 2 V is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.

A Simple Spacer Technique to Fabricate Poly-Si TFTs With 50-nm Nanowire Channels

In this letter, polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 50-nm nanowire (NW) channels, which are fabricated without advanced photolithography by using a sidewall spacer-formation technique, are proposed for the first time. Because the polygate electrode is perpendicularly across poly-Si NW channels to form a trigatelike structure, the proposed poly-Si NW TFT owns outstanding gate controllability. In summary, a simple and low-cost scheme is proposed to fabricate high-performance poly-Si NW TFT suitable for future display manufacturing and practical applications.

Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels

The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared with conventional planar devices having self-aligned source/drain, the new devices show an improved on-current per unit width and better control over the short channel effects. The major conduction mechanism of the off-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure.

A simple and low-cost method to fabricate TFTs with poly-Si nanowire channel

A very simple and low-cost scheme is proposed for fabricating thin-film transistors with poly-Si nanowire (NW) channels. In this scheme, the poly-Si NW channel is formed by cleverly employing the poly-Si sidewall spacer technique. In addition, the poly-Si NW channel is genuinely exposed to the environment after the poly-Si sidewall spacer formation in the new scheme. This unique feature, together with its simplicity and low-cost, makes this approach very suitable for applications and manufacturing of bio-logic sensing devices. Good device performance is demonstrated in this letter.