poly-Si Interface Research Articles

Investigating the degradation behaviours of n+-doped Poly-Si passivation layers: An outlook on long-term stability and accelerated recovery

In this article, we study the kinetics of firing-activated degradation and recovery of industrially processed n + -doped poly-Si on thin oxide passivation layers subjected to illuminated annealing at elevated temperatures. The impact of a comprehensive range of fast-firing conditions on the subsequent degradation and recovery were assessed. The results indicate that the recovery process is dependent on the peak firing temperature, where higher temperatures led to an improvement in effective lifetime of up to 20% compared to the pre-fired state, and a very low surface dark saturation current density of 2.9 fA/cm 2 . By cycling through light soaking and dark anneal conditions, we show that unlike the commonly studied boron-oxygen light-induced degradation (BO-LID) and light- and elevated temperature-induced degradation (LeTID), this newly observed instability in n + -doped poly-Si passivation layers is not reversible, that is, once a degradation/recovery cycle is completed, the lifetime remains very stable under subsequent light soaking. This indicates that the surface related instability may be able to be completely resolved following the completion of the first degradation/recovery cycle. With this in mind, we investigate the potential for high intensity laser illumination (up to 150 kW/m 2 ) to rapidly increase the recovery rates, however, this does not seem sufficient to cycle through degradation and recovery on a timescale that is amenable with mass production. The mitigation of any potential instabilities at the poly-Si interface has significant implications for the reliability of n-type tunneling oxide passivated contact (TOPCon) solar cells. • Firing conditions have a significant impact in stability of polysilicon passivation. • The firing-induced surface instability is different to previous degradation modes. • Cycling between degraded and recovered states does not occur.

Abnormal threshold voltage shifts in p-channel low temperature polycrystalline silicon TFTs under deep UV irradiation

The electrical properties of p-channel low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) under deep ultraviolet (UV) irradiation were studied. Characteristics including threshold voltage (Vth), hole field effect mobility (μeff) subthreshold swing (SS), and leakage current (Ioff) were investigated as a function of UV irradiation doses from 4 to 20 J/cm2. With an increase in UV irradiation dosage, the Vth shift of the TFT showed a turnaround effect, which first shifted to the positive direction and then shifted back to the negative direction after a UV irradiation dose of 16 J/cm2. The continuous degradation of SS and μeff was discovered with the enhancement of UV irradiation dose. To better understand the physical mechanisms underlying these characteristic changes, UV induced traps at poly-Si grain boundaries, traps at the poly-Si and gate oxide insulator (poly-Si/SiO2) interface, and trapped charges in the gate oxide were studied with a function of UV irradiation doses.

Effect of ELA Energy Density on Self-Heating Stress in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The extent of the poly-silicon crystalline protrusion, a result of differences in excimer laser annealing (ELA), affects the performance and reliability of thin-film transistors (TFTs). This study investigates the degradation mechanism of the low-temperature polycrystalline silicon (LTPS) TFT devices with differences in crystalline protrusion under self-heating stress (SHS). Higher ELA energy will induce higher protrusion height in the interface between the poly-silicon and gate insulator (GI). This surface morphology leads to serious charge trapping into the GI layers; in contrast, the smallest degradation after SHS can be seen in the devices with the lowest protrusion height. This indicates that the degradation is caused by the surface morphology between the poly-Si and GI interface. In addition, the COMSOL simulation results confirm that the large electric field in the GI layer appears in the rough surface morphology devices; therefore, choosing the appropriate ELA energy of the poly-Si is beneficial for the applications of the driving TFT in organic light-emitting diode (OLED) display in the manufacturing industry.

Separating the two polarities of the POLO contacts of an 26.1%-efficient IBC solar cell

By applying an interdigitated back contacted solar cell concept with poly-Si on oxide passivating contacts an efficiency of 26.1% was achieved recently. In this paper the impact of the implemented initially intrinsic poly-Si region between p-type poly-Si and n-type poly-Si regions is investigated. Two recombination paths are identified: The recombination at the interface between the initially intrinsic poly-Si and the wafer as well as the recombination across the resulting p(i)n diode on the rear side which is aimed to be reduced by introducing an initially intrinsic region. By using test structures, it is demonstrated that the width of the initially intrinsic region ((i) poly-Si region) has a strong influence on the recombination current through the p(i)n diode and that this initially intrinsic region needs to be about 30 μm wide to sufficiently reduce the recombination across the p(i)n diode. Lateral and depth-resolved time of flight secondary ion mass spectrometry analysis shows that the high-temperature annealing step causes a strong lateral inter-diffusion of donor and acceptor atoms into the initially intrinsic region. This diffusion has a positive impact on the passivation quality at the c-Si/SiOx/i poly-Si interface and is thus essential for achieving an independently confirmed efficiency of 26.1% with 30 μm-wide initially intrinsic poly-Si regions.

Process Optimization of CoSi2 Formation on P-Doped Poly-Si by Hot Wall-Based Rapid Thermal Annealing

Low resistivity junctions and low resistivity contacts are essential for fabricating high performance devices with advanced device modes. Significant effort has been expended to develop low resistivity junctions, industry wide. However, low resistivity contact formation has not received significant attention, other than changing the silicide of choice, depending on required minimum line width or device node. Once the candidate silicide material is chosen for the device node, relatively small improvement in resistivity has been made in recent years, despite silicidation process optimization which include modifications of process steps and integration schemes. In this study, we have investigated the effect of annealing temperature and time on the resulting resistivity of Co2Si contacts with P-doped poly-Si using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. The hot wall RTA resulted in significantly (>20%) lower Rs, down to 19.6 ohm/sq. from equivalent RTA process using conventional tungsten halogen lamp-based (cold wall) RTA systems over a very wide process window (RTA temperature and time). Secondary ion mass spectroscopy (SIMS) dopant (P) depth profiling results revealed that the P atoms in the CoSi2 film and at the CoSi2/P-doped poly-Si interface, redistribute very differently under different RTA conditions. The same Rs value can be realized by different P profiles resulting from different RTA conditions. To enable contact resistance reduction, P pile-up near the CoSi2/P-doped poly-Si interface for and to suppress P depletion from P-doped poly-Si layer for resistivity reduction, lower temperature RTA for longer times in the hot wall RTA system was found to be beneficial. Wafers with almost identical P depth profiles after CoSi2 formation RTA in the cold wall RTA and the hot wall RTA systems, still showed an Rs difference of ~20%. The wafers annealed in the hot wall RTA system always showed lower Rs values indicating higher P dopant activation in the P-doped poly-Si layer. The difference in wafer heating mechanisms between the cold wall (lamp-based) RTA and the hot wall (furnace-based) RTA may have played an important role in the dopant activation and Rs differences. Hot wall RTA is very promising for realizing the low resistivity contacts required in advanced high performance devices. The simple change of annealing technique may extend the life cycle of CoSi2/P-doped poly-Si contacts. The Rs response surface (as a function of RTA temperature and time) and SIMS depth profiles of P atoms will be presented at the meeting. Figure 1

Process Optimization of CoSi2 Formation on P-Doped Poly-Si by Hot Wall-Based Rapid Thermal Annealing

To achieve low resistivity contacts, the effect of annealing temperature and time on the resulting resistivity of CoSi2 contacts with P-doped poly-Si was investigated using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. The hot wall RTA resulted in significantly (>20%) lower sheet resistance (Rs) from the equivalent RTA process using conventional tungsten halogen lamp-based (cold wall) RTA systems over a very wide process window. Dopant (P) depth profiling results by secondary ion mass spectroscopy (SIMS) revealed that the P atoms in the CoSi2 film and at the CoSi2/P-doped poly-Si interface, redistribute very differently under different RTA conditions. The CoSi2 formation process was optimized utilizing characteristics of P pile-up near the CoSi2/P-doped poly-Si interface to suppress P depletion from the P-doped poly-Si layer.

Towards Contact Resistance Minimization through CoSi2 Formation Process Optimization on P-Doped Poly-Si by Hot Wall-Based Rapid Thermal Annealing

The effect of annealing temperature and time on the resulting resistivity of CoSi2 contacts with P-doped poly-Si was investigated using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. To achieve low resistivity contacts, CoSi2 formation process optimization was done by detailed design of experiment (DOE). Sheet resistance (Rs) response surface plots as a function of annealing temperature and time for 1st step and 2nd step RTA processes showed a very wide process window. The hot wall RTA resulted in significantly (>20%) lower Rs, over a very wide process window, compared to the equivalent RTA process using conventional tungsten halogen lamp-based (cold wall) RTA systems. Dopant (P) depth profiling results by secondary ion mass spectroscopy (SIMS) revealed that the P atoms in the CoSi2 film and at the CoSi2/P-doped poly-Si interface, redistribute very differently under different RTA conditions. The CoSi2 formation process was optimized utilizing characteristics of P pile-up near the CoSi2/P-doped poly-Si interface to suppress P depletion from the P-doped poly-Si layer for contact resistance minimization.

Raman Characterization of Poly-Si Channel Materials for 3D Flash Memory Device Applications

Three dimensional (3D) vertical NAND (V-NAND) flash technology has been actively investigated. [1] 3D NAND architectures offer one of the best combinations of device performance, memory density, power consumption and manufacturing cost. All major memory device manufacturers are actively pursuing development of commercially viable devices. Development of bit cost scalable (BiCS) NAND technology is very important from both technology and commercialization points of view.Device scaling was achieved by vertical staking of thin film transistors (TFTs) in contrast to the conventional planar device scaling techniques relying on advances in lithography. Poly-Si is used as channel materials in 3D V-NAND flash memory devices. Control of both poly-Si grain size and grain size distribution is very important for tight control of device yield and performance variations.For poly-Si channel fabrication, amorphous Si (a-Si) film is deposited in the channel region and then converted to poly-Si by thermal annealing. To achieve desired properties of the poly-Si channel, grain size, resistivity, mobility and interface quality must be carefully monitored and controlled. One of the basic parameters of the poly-Si channel is grain size. Smaller grains lower in channel carrier mobility while larger grains increase device performance variations. The grain size and its distribution have to be optimized for the best device performance. Development of proper in-line characterization techniques for poly-Si grain size, after thermal annealing, is strongly desired.In this paper, Raman spectroscopy was used for characterizing poly-Si after thermal annealing of chemical vapor deposited (CVD) thin a-Si films on SiO2/Si wafers. The a-Si films on SiO2/Si wafers were annealed in a single wafer rapid thermal furnace (SRTF-300 system [4, 5]) in the temperature range of 600 ~ 1050oC under various ambient gases.Systematic change of Raman spectra, indicating crystallization of a-Si films and grain growth of poly-Si with annealing temperature increase was measured (Fig. 1.) using an MRS-300 system. [6] As deposited a-Si/SiO2/Si showed one sharp peak from the Si wafer at ~ 520.3cm-1 and one broad peak centered at ~ 480cm-1 corresponding to a-Si. After thermal annealing, the a-Si peak decreased in intensity and transformed into new peaks at ~ 495 and ~ 515 cm-1, corresponding to poly-Si. The poly-Si peaks increased and sharpened as the annealing temperature increased. The change of Raman spectra indicates the degree of polycrystallization and grain growth under different annealing conditions. Figures 2 and 3 showed the Raman spectra from the annealed samples and their deconvolution results. Detailed Raman characterization, as a function of annealing temperature and type of ambient gas, will be reported at the conference.

Current Understanding of the Transport Behavior of Hydrogen Species in MOS Stacks and Their Relation to Reliability Degradation

We review recent experiments that suggest a comprehensive model for the reversible hydrogen (H) transport between the poly-Si interface and the oxide/Si interface of MOS stacks. The H diffusion in intact model MOS structures is probed by H depth profiling via resonant 15N-H nuclear reaction analysis (NRA). It is demonstrated that MOS device degradation correlates with H accumulation in the oxide/Si interface region. A specific ultra-thin oxynitride is discovered in the poly-Si/oxynitride interface as well as in the near-surface region of N2-annealed nitride films and shown to function as a potential H-storage layer. The interfacial storage layer between the poly-Si gate and the oxynitride dielectric of MOS transistors is found to contain two kinds of H species, which are mobile and stable, respectively, versus irradiation-induced relocation. The mobile H, if stimulated by energetic carriers, migrates across the gate films and relocates to the SiO2/Si interface, causing device instabilities. Understanding this basic hydrogen transport behavior allows conceiving fabrication countermeasures to improve the device reliability.

Collapse behavior and forces of multistack nanolines

Two types of multistack nanolines (MNLs), Si-substrate (Si)/siliconoxynitride (SiON)/amorphous Si (a-Si)/SiO2 and Si/SiO2 /polycrystallineSi (poly-Si)/ SiO2 were used to measure the collapse force and to investigate their collapsebehavior by an atomic force microscope (AFM). The Si/SiON/a-Si/SiO2 MNL showed a larger length of fragment in the collapse patterns at a smaller collapse force. The Si/SiO2 /poly-Si/SiO2 MNL, however, demonstrated a smaller length of fragment at a higher applied collapseforce. The collapse forces increased by the square of the linewidth in both Si/SiON/a-Si/SiO2 andSi/SiO2 /poly-Si/SiO2 MNLs. Once an AFM tip touches an Si/SiON/a-Si/SiO2 line,which is a softer MNL, it was delaminated first at the Si/SiON interface. One end of the delaminatedline was first broken and then the other end was bent until it was broken. A harder MNL, Si/SiO2 /poly-Si/SiO2, however, was broken at two ends simultaneously after the delamination occurred at the Si/SiO2 /poly-Si interface. The different collapse behaviors were attributed to the magnitude ofadhesion forces at the stack material interfaces and the mechanical strength of MNLs.

Performance enhancement of excimer laser crystallized poly-Si thin film transistors with fluorine implantation technology

Polycrystalline silicon thin film transistors (poly-Si TFTs) with the ion implantation of fluorine elements were investigated in this study. The electrical performance and reliability were reported comprehensively. Experimental work has shown the electrical characteristics of excimer laser crystallized F-ions-implanted poly-Si TFTs are improved effectively, especially for field effect mobility. It is also found that the fluorine piled up at the poly-Si interface during thermal annealing, for the TFT fabricated without a prior deposition of pad oxide. The stronger Si–F bonds replace the Si–Si/Si–H, leading to the superior electrical reliability. However, the dose of F ions is critical in poly-Si, or the electrical characteristics of TFT devices will be degraded.

Improved Performance of F-Ions-Implanted Poly-Si Thin-Film Transistors Using Solid Phase Crystallization and Excimer Laser Crystallization

Polycrystalline silicon thin-film transistors (Poly-Si TFTs) with F-ions-implantation were investigated in this study. The electrical characteristics and reliability of the F-ions-implanted poly-Si TFTs were reported for solid phase crystallization (SPC) and excimer laser crystallization (ELC) methods respectively. The thermal annealing causes F-ions to pile up at the poly-Si interface, without the initial pad oxide deposition. With the introduction of fluorine in poly-Si film, the trap state density was effectively reduced. Also, the presence of strong Si-F bonds enhances electrical endurance against hot carrier impact by using F-ions-implantation. These improvements in electrical characteristics are even obvious for the ELC poly-Si TFTs compared to the SPC ones

Degradation Behaviors of Trigate Nanowires Poly-Si TFTs with NH[sub 3] Plasma Passivation under Hot-Carrier Stress

This work studies degradation behavior after hot-carrier stress of trigate polysilicon thin-film transistors (poly-Si TFTs) with nanowires. The NH 3 plasma passivation effect is also studied on the electrical characteristics after hot-carrier stress. The reliability of poly-Si TFTs with NH 3 plasma passivation outperforms that without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pileup of nitrogen at the SiO 2 /poly-Si interface. The reliability of poly-Si TFTs further improves by using nanowires structure. These findings originate from the fact that the nanowires poly-Si TFT has robust trigate control to reduce the hot-carrier effect due to declining lateral electrical field and its penetration from the drain, and its split nanowire structure has superior NH 3 plasma passivation effect. In degradation results under dc and ac stress, it reveals that the NH 3 plasma is mostly passivated on deep traps of grain boundaries rather than tail traps.

Electrical Enhancement of Solid Phase Crystallized Poly-Si Thin-Film Transistors with Fluorine Ion Implantation

Solid phase recrystallized polycrystalline silicon thin-film transistors (SPC poly-Si TFTs) with fluorine ion implantation were investigated in this study. Electrical characteristics and reliability of the proposed poly-Si TFTs were improved effectively, especially for field effect mobility and off current. The fluorine-ion-implanted poly-Si TFT can suppress the hot carrier multiplication near the drain side, leading to superior endurance to electrical stress compared with conventional poly-Si TFTs. It was found that fluorine ions will pile up at the poly-Si interface during thermal annealing, without the initial deposition of pad oxide. The proposed technology is manageable and compatible with conventional poly-Si TFT fabrication. As the ion dosages increase more than , however, the electrical characteristics of poly-Si TFTs were degraded due to the increase of trap state density caused by the fluorine segregation in the poly-Si film.

Valence-band electron-tunneling measurement of the gate work function: Application to the high-κ/polycrystalline-silicon interface

A technique is demonstrated to measure the band alignment between the silicon substrate and the gate electrode using the valence-band electron tunneling (VBET). When an n-channel metal-oxide-semiconductor field-effect transistor is biased in inversion the valence-band electron from the Si substrate can tunnel into the gate [A. Shanware, J. Shiely, H. Massoud, E. Vogel, K. Henson, A. Srivastava, C. Osburn, J. Hauser, and J. Wortman, Tech. Dig.-Int. Electron Devices Meet.1999, 815], depending on the overlapping of the density of states in the Si valence band and the gate. This technique is suitable to measure the band alignment between the silicon substrate and the gate electrode with any given gate dielectric, provided that both the gate and substrate leakages are dominated by direct tunneling. This technique has been applied to study the SiO2/polycrystalline-silicon (poly-Si) interface behavior in the presence of submonolayer traces of HfO2. The general applicability of VBET to arbitrary gate stacks is finally demonstrated with the HfSiON/poly-Si case.

A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs

A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF/sub 4/ plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO/sub 2//poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better on/off current ratio. Furthermore, the CF/sub 4/ plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.

Stress-Induced Voiding in Sputtered TiSi[sub x] Complementary Metal Oxide Silicon Gate Electrodes

We examined the effect of shallow trench isolation (STI) process for the Si ultralarge-scaled integrated circuit on the thermal stability of the bar resistance and the internal void formation of sputtered-/poly-Si gate electrodes. Among the examined process variables, the STI step height can strongly affect the density of voids formed between the poly-Si and the films after the silicidation annealing. Above a STI step height of 400 Å, many clear voids were observed at the STI boundaries by scanning electron microscopy. The thermal stability of the sheet resistance for the /poly-Si gate electrode was investigated at various STI step heights and Si/Ti molar ratios (x) of the composite target. With the decrease in STI step height from 400 to 200 Å, the average at a 0.16 μm linewidth was enhanced from ∼60 to 15 Ω/□ after postannealing at 800°C for 2 h. With the increase of x from 2.1 to 2.3, the thermal stability of was also greatly enhanced showing an average of ∼15 Ω/□ at a 400 Å STI step height. From this study, we suggest that the stress-induced voiding at /poly-Si interface plays one of key roles in thermal degradation of due to the highly developed triaxial stress state in the gate electrode film. © 2002 The Electrochemical Society. All rights reserved.

Benefits of microscopy with super resolution

Transmission electron microscopy developed from an imaging tool into a quantitative electron beam characterization tool that locally accesses structure, chemistry, and bonding in materials with sub-Angstrom resolution. Experiments utilize coherently and incoherently scattered electrons. In this contribution, the interface between gallium nitride and sapphire as well as thin silicon gate oxides are studied to understand underlying physical processes and the strength’ of the different microscopy techniques. An investigation of the GaN/sapphire interface benefits largely from the application of phase contrast microscopy that makes it possible to visualize dislocation core structures and single columns of oxygen and nitrogen at a closest spacing of 85 pm. In contrast, it is adequate to investigate Si/SiO x N y /poly-Si interfaces with incoherently scattered electrons and electron spectroscopy because amorphous and poly-crystalline materials are involved. Here, it is demonstrated that the SiO x N y /poly-Si interface is rougher than the Si/SiO x interface, that desirable nitrogen diffusion gradients can be introduced into the gate oxide, and that a nitridation coupled with annealing increases its physical width while reducing the equivalent electrical oxide thickness to values approaching 1.2 nm. Therefore, an amorphous SiN x O y gate dielectric seems to be a suitable substitute for traditional gate oxides to further increase device speed by reducing dimensions in Si technology.

Poly-Si TFT fabricated by laser-induced in-situ fluorine passivation and laser doping

A new poly-Si TFT has been fabricated by employing laser-induced in-situ fluorine passivation and a laser-doping method. With only one excimer laser annealing, we have successfully fabricated the device using one step to crystallize, passivate and dope simultaneously. Although no additional plasma post-passivation was performed, the on-state and the off-state leakage properties of TFTs with fluorine passivation were improved compared with those without fluorine passivation. The device with in-situ fluorine passivation has the maximum transconductance of 13.3 μA/V for a C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> F/sub 6/ flow rate of 100 sccm, whilst that for a device without fluorine passivation is 8.4 μA/V. The device reliability under electrical stress was remarkably improved in the in-situ fluorine-passivated devices due to the fluorine passivation of trap states in the poly-Si channel and at the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /poly-Si interface.

Endurance Characteristics and Degradation Mechanism of Polysilicon Thin Film Transistor EEPROMs with Electron Cyclotron Resonance N2O-Plasma Gate Oxide

Endurance characteristics and degradation mechanism of polysilicon thin film transistor (poly-Si TFT) EEPROMs with electron cyclotron resonance (ECR) N2O-plasma oxide have been investigated. The ECR N2O-plasma oxide has Qbd up to 10 C/cm2 due to the smooth interface and strong Si-N bonds. The poly-Si TFT EEPROMs have a larger threshold voltage shift of 2.5 V even after 105 program and erase (P/E) cycles. The threshold voltage of the programmed device decreases until 104 P/E cycles, but after then increases, while that of the erased device increases after 103 P/E cycles. The degradation is ascribed to electron trapping in the oxide and the generation of traps and interface states at the tunnel oxide/active poly-Si interface.