poly-Si Gate Electrode Research Articles

Numerical Study of SiC MOSFET With Integrated n-/n-Type Poly-Si/SiC Heterojunction Freewheeling Diode

It is highly desirable to monolithically integrate a high-performance freewheeling diode (FWD) in both Si and SiC power MOSFETs for power electronic applications. This is especially true for a SiC MOSFET since its inherent body diode has a very large turn-on knee voltage (~2.7 V). The purpose of this numerical study is to investigate a new 1200 V SiC MOSFET structure with an integrated heterojunction diode formed between n-type polysilicon and n-type SiC (termed HJD-MOSFET). The proposed HJD-MOSFET uses a mesa structure to accommodate the heterojunction FWD without sacrificing any active area while leaving the split-gate planar MOSFET cells in the trench. A p-shield region surrounding the heterojunction, along with the p-base of the MOS cells, shields high electric fields and maintains a high breakdown voltage. Three key HJD-MOSFET device parameters are identified and optimized in this article. The HJD-MOSFET offers a turn-on knee voltage of 0.5 V, roughly five times lower than the intrinsic SiC body diode or two times lower than a typical SiC Schottky barrier diode due to the low barrier height of the n/n heterojunction (~0.68 eV). Finally, the gate charge of HJD-MOSFET is reduced by 42% compared with conventional MOSFET since the poly-Si gate electrode is significantly reduced to accommodate the heterojunction FWD.

(Invited) Past, Present, and Future of High-k/Metal Gate Technologies

The SiO2 based gate insulator and poly Si gate electrode had been used almost 4o years for (C)MOS integrated circuits from 1970 to 2010 because of their extraordinary good properties of both the interfaces at the substrate and gate electrode. Thus, most of the people had not believed the replacement of SiO2/poly Si gate stack by that of high-k/metal in the products would be impossible, although the demand to introduce the high-k gate oxide became stronger due to the high tunneling gate leakage current when decreasing the gate oxide thickness with the scaling. However, the operation of high k/metal gate stack MOSFETs were demonstrated by several different organizations at the same time at IEDM 1999. Since then, many R & D organizations seriously participated to the research and development of high-k/metal gate stack for MOSFETs. It was in 2001, when Prof. Samares Kar proposed to create an ECS symposium on “Physics and Technology of High-k Gate Dielectrics”. Then, the 1st symposium was held in Salt Lake City, Utah, U.S.A. on October 20-14, 2002. At that time total number of the presentations at the symposium was 34. The, number increased to 56 in the 2nd symposium in Cancun, Mexico, 2003, and 75, in the 3rd symposium in Los Angeles, in 2006, and so on. In 2007, Intel introduces HfO2 based high-kmaterial for the 1st time into their product. Later, the symposium was renamed with Semiconductors, dielectrics and metals for Nanoelectronics and still continues and contributed to give opportunities to the researchers and engineers for the paper presentation and discussion. Prof. Samares Kar has been the leading organizer of the symposium, maintaining rigorous standards to make the symposium one of the most successful in ECS. However, it was very sad that Prof. Samares Kar passed away on January 13, 2017 at his home in Kolkata, India. We would like to express our sincere appreciation for the hard work and rigorous drive towards the advancement of the symposium by giving presentations for the past, present and future of high-k stack technologies.

Poly-Si gate electrodes for AlGaN/GaN HEMT with high reliability and low gate leakage current

AlGaN/GaN HEMT with a BF2-implanted polycrystalline Si gate has been characterized through comparison to TiN gate electrodes. Positive threshold voltage (Vth) shift was observed with the addition of F ions, which in turn degraded the effective electron mobility (μeff) by diffusion into the AlGaN/GaN interface and GaN layer. A large reduction in gate leakage current (Jg) was achieved and the property was maintained even after strong reverse-bias stressing. No additional degradation in μeff was observed, suggesting the formation of a stable poly-Si/AlGaN interface. Therefore, poly-Si gate electrodes have advantages in reducing the Jg and robustness against reverse-bias stressing.

Failure Analysis of a SiC MOS Capacitor with a Poly-Si Gate Electrode

The failure mechanism of a SiC metal-oxide-semiconductor capacitor with a poly-Si gate electrode was investigated by time-dependent dielectric breakdown testing under a 200-nA constant current stress. The capacitor exhibited both hard and soft breakdowns. After dielectric breakdown in both cases, adjacent concaves were observed on the capacitor with a field-emission scanning electron microscope. Additional optical beam-induced resistance changes and photo-emission analysis of a capacitor after hard-breakdown located a failure point on the periphery of a group of adjacent concaves. Cross-sectional scanning transmission electron microscope observation revealed that a narrow, vertical defect had formed at this point on the SiC substrate.

High sensitivity silicon single nanowire junctionless phototransistor

A high-gain photodetector based on junctionless MOSEFT has been presented in this work. Tri-gate junctionless nanowire phototransistors were fabricated on (100) silicon-on-insulator wafers with a buried oxide of thickness 145 nm and top silicon layer of thickness 10 nm. The gate stack consisted of a 10 nm SiO2 dielectric and a 50 nm poly-Si gate electrode. The channel length and doping concentration of junctionless n-MOSFETs was 1 μm and 3 × 1019 cm−3, respectively. The dark current of this device measured at room temperature was less than 1 pA. The measured internal gain of the device was about 35 for 860 nm light illumination. The photocurrent was 300 times larger than the dark current for only 30 nW incident power on the nanowire at 300 mV drain bias.

Ultra-Low Temperature Flattening Technique of Silicon Surface Using Xe/H2 Plasma

(1) Introduction The interface microroughness between the insulator film and the silicon substrate is one of the critical issues to the gate insulator film reliability and the performance of MOSFETs [1-2]. The atomically flat surface of Si(100) has been obtained by the ultra-pure Ar annealing at the temperature of 800 ºC or above [3-7]. The MOSFETs having atomically flat interface between the silicon substrate and the radical gate SiO2 film show higher performances than the MOSFETs having conventional interfaces [3,4,7]. The decreasing flattening temperature is effective to apply the flattening process to the patterned wafer just before the gate oxide formation. We have reported that the 800 oC annealing can be applied to the wafers having the shallow trench isolation (STI), and the breakdown field intensity (Ebd) improved and the random telegraph noise decreased [8]. In order to introduce the flattening process just before the gate oxide formation in the latest LSI manufacturing process such as Fin-FET, it is considered that lower flattening temperature is strongly required. Thus the flattening technique of silicon surface was developed by using Xe/H2 plasma at 400 oC. In this paper, MOS devices are fabricated by an introduction of Xe/H2plasma flattening technique and these electrical characteristics are evaluated. (2) Experimental details In this study, MOS capacitors were fabricated using Cz-n type Si(100) wafers (8-12 Ω·cm) as follows. For the device isolation, 300 nm-thick field oxide films were grown by a pyrogenic wet oxidation at 1000 oC followed by patterning the active region. These patterned wafers were cleaned by APM (29% NH4OH : 30% H2O2 : H2O = 0.05 : 1 : 5) solution with megasonic and the native oxides were removed by 0.5% dilute HF. Just before the gate oxides formation, Xe/H2 plasma flattening process was performed by a microwave-excited high-density Xe(90%)/H2(10%) plasma at a pressure of 266 Pa and temperature of 400 °C for 3 min. The 7 nm-thick gate oxides were fabricated by radical oxidation followed by forming n+ poly-Si gate electrode and Al buck side electrode. Finally the forming gas (10 %H2/90 %N2) annealing at 400 oC was carried out for 30 min. (3) Results and discussion Fig 1 shows the 3×3 μm2 AFM images (a) before and (b) after flattening Si(100) surface by using the Xe/H2 plasma. The average roughness (Ra) of Si(100) surface was decreased from 0.12 nm to 0.039 nm by the Xe/H2 plasma treatment. Fig. 2 shows the variations of the breakdown field intensity (Ebd). Here, Ebd was determined at breakdown field in the current density versus the electric field (J-E) characteristics of MOS capacitors whose area was 10-4 cm2. By an introduction of the Xe/H2 plasma flattening, Ebd was improved more than 1 MV/cm and obtained the much smaller fluctuation of Ebd than that of conventional. From these results, improving Si surface flatness before gate oxide formation can be effective to reduce the variations of Ebd. The reason is considered that the local spots, where the excess electric field is induced in the roughened SiO2/Si interface, are drastically decreased by the Xe/H2 plasma flattening at even 400 oC. Consequently the Xe/H2plasma flattening technique can be effective to the advanced integrated circuit with very shrunk transistors such as three dimensional MOFET (Fin-FET). Acknowledgments This work was partially supported by JSPS KAKENHI Grant Number 22000010. Reference T. Ohmi, et al., Electron. Device Lett., 12, p.652 (1991).T. Ohmi, et al., T-ED 39, p.537 (1992).R. Kuroda, et al., T-ED, 56, p.291 (2009).R. Kuroda, et al., Jpn. J. Appl. Phys., 48, p.04C048 (2009).X. Li, T et al., ECS Trans. 28 p.299 (2010).X. Li, et al., Microelec. Eng., 88, p.3133 (2011).X. Li, et al., Jpn. J. Appl. Phys., 50, p.10PB05 (2011).T. Goto, et al., Extended Abst. SSDM, F-1-3, p.670 (2014).T. Suwa, et al., ECS Trans., 61, p.401 (2013). Figure 1

On the Origin of the Gate Oxide Failure Evaluated by Raman Spectroscopy

1. Background and purpose In the miniaturization of the large-scale integrated-circuit (LSI), gate oxide thinning is one of the most important techniques for the performance improvement. However, the ultimately thinned gate oxide causes in the failure with high leakage current. Thus, the evaluation and control of the gate oxide integrity is indispensable in the present LSI technology. In this study, we evaluated the origin of the gate oxide failure by Raman spectroscopy in conjunction with optical beam induced resistance change (OBIRCH) analysis. 2. Experiments Metal-oxide-semiconductor (MOS) capacitors were used as the samples. The 2.8 nm thick gate oxinitrid insulator film and the poly-Si gate electrode layer were formed on a P type Si substrate. The poly-Si layer was deposited at 620 oC with the SiH4 flow rate of 150 or 350 sccm. The gate oxide integrity was evaluated by the test element group (TEG) measurements. The failure was observed only for the 150 sccm SiH4 flow. The current-voltage (I-V) characteristics were shown in Fig. 1. The positions with high leakage current were specified by OBIRCH, and evaluated by Raman spectroscopy. One-dimensional measurements were performed for the Raman spectroscopy by using a quasi-line excitation source at the same time. Excitation laser was Nd:YAG laser (wavelength: 532 nm), and the focal length of the spectrometer was 2,000 mm. The length of the quasi-line laser was approximately 100 μm. We investigated the origin of the gate oxide failure by Raman Spectroscopy obtained at the leakage position determined by OBIRCH. 3. Result s and Discussion Figure 2 shows the light emission image obtained by OBIRCH at the MOS capacitor with gate oxide failure fabricated with 150 sccm SiH4 flow. We confirmed that there are two defect points in the MOS capacitor. Figure 3 shows the Raman intensity distribution across the leakage position in the sample. The higher Raman intensity than the surroundings was confirmed at the failure position. Figure 4 shows the distribution of the Raman shift and the full width at half maximum (FWHM) across the failure position. As shown in Fig. 4, we verified that the Raman peaks at the defect positions shifted toward the lower wave number compared with the other positions. It can be considered that the gate oxide failure was induced by the high tensile strain in the poly-Si layer, probably due to the lack of the SiH4 supply during the deposition. Furthermore, FWHM of Raman spectra were not different comparing with the other position. Thus, there is no difference in the crystallinity and the grain size of the poly-Si. In conclusion, we have evaluated the gate oxide failure with leakage current by Raman spectroscopy and found that the origin was high tensile strain in the gate poly-Si.

On the Origin of the Gate Oxide Failure Evaluated by Raman Spectroscopy

The metal-oxide-semiconductor-field-effect-transistor (MOSFET) has been miniaturized for the high performance large-scale integrated-circuit (LSI). However, in the ultimately miniaturized MOSFET, the gate oxide failure with high leakage current is inevitable. In this study, we evaluated the origin of the gate oxide failure by Raman spectroscopy in conjunction with optical beam induced resistance change (OBIRCH) analysis. MOS capacitors were used as the samples. The 2.8 nm thick gate oxinitrid insulator film and the poly-Si gate electrode layer were formed on a P type Si substrate. The cobalt (Co) silicide film was formed on the poly-Si electrode. The SiH4 flow rate was 150 sccm or 350 sccm. The gate oxide integrity was evaluated by the test element group (TEG) measurements. As a result, Raman intensity increased at the failure position compared with the other positions in the sample deposited with 150 sccm of SiH4 flow rate. We consider that higher Raman intensity at the gate oxide failure positions reflects the irregular structure of poly-Si. Furthermore, the Raman peaks at failure positions shifted toward the lower wavenumber while the FWHMs are approximately constant with other positions. Thus, we found that there is no difference in the crystallinity of the poly-Si. The origin of the gate oxide failure was high tensile strain in the gate poly-Si electrode. In conclusion, we have successfully evaluated the gate oxide failure by Raman spectroscopy with a quasi-line excitation source.

Pattern transfer of directed self-assembly patterns for CMOS device applications

A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.

Defects responsible for the Fermi level pinning in n+ poly-Si/HfO2 gate stacks

Based on density functional calculations, we propose a defect model that can explain flat band voltage shifts, especially in n+ poly-Si/HfO2 gate stacks. For two interface structures, with Si electrodes on top of crystalline and amorphous HfO2, we find the formation of O-vacancies at the interface, which exhibit weak Si–Si dimer bonds and low formation energies, very different from those in the oxide. Due to weak dimer bonds, charge trap levels lie near the Si conduction band edge, leading to the Fermi level pinning and flat band voltage shifts in n+ poly-Si gate electrodes.

Possible Origins of Extra Threshold Voltage Variability in N-Type Field-Effect Transistors by Intentionally Changing Process Conditions and Using Takeuchi Plot

The origins of the threshold voltage (VT) variability of n-type field-effect transistors (NFETs), which have larger VT variability than p-type field-effect transistors (PFETs), are investigated using the Takeuchi plot and by intentionally changing process conditions. The process conditions investigated in this study are the polarity of polycrystalline silicon (poly-Si) gate electrodes, fluctuations of gate oxide thickness and gate oxide/substrate interface, and channel stress. It is confirmed by experiments that these process conditions negligibly affect VT variability in NFETs. This result does not contradict our previous result that channel profile nonuniformity is the major origin of the larger VT variability in NFETs than that in PFETs.

Evaluation of Si etching yields by Cl+ Br+ and HBr+ ion irradiation

Cl2 and HBr plasmas are widely used for poly-Si gate electrode etching processes in the semiconductor industry. In this study, sputtering yields of poly Si by Br+ and HBr+ion injections, simultaneous injections of thermal H atoms and energetic Br+ ions, and successive injections of an energetic H+ and Br+ ion beams, have been evaluated with the use of a multi-beam system equipped with a mass-selected ion beam injector and a H radical source. It has been shown that there is little difference in sputtering yields among all these processes, which indicates that such hydrogen has little effect on the Si sputtering yield by Br+ ion injections. The result contrasts with an earlier speculation that hydrogen in HBr plasmas significantly enhances the Si sputtering yield by Br+ ion injections. In addition sputtering yields of poly Si by Cl+ ion bombardment obtained from similar beam experiments have been presented for comparison.

A carrier-mobility model for high- k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high- k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high- k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high- k gate dielectric and the charge carriers in the conduction channel.

Advanced high-k/metal gate stack progress and challenges – a materials and process integration perspective

Abstract Scaling of complementary metal oxide semiconductor devices is critical to enhancing performance and reducing the production cost of transistors. Conventional gate stack film systems consisting of a SiO2 dielectric layer between the Si substrate channel and a doped polycrystalline silicon (poly-Si) gate electrode exhibited excessively high gate current leakage when the physical thickness of this traditional dielectric was scaled to Tphys = ∼2 nm. The rate of scaling was initially preserved by incorporating nitrogen to form an SiOxNy insulator layer; however, this material soon experienced unacceptable levels of direct tunneling leakage current, which launched an industry-wide investigation of potential high dielectric constant (high-k) metal oxides as replacement materials for the SiO2 based gate dielectric layer. Thermal stability requirements for the introduction of high-k dielectric materials necessitated the simultaneous replacement of poly-Si with a metal gate electrode due to several performance factors including unscalable threshold voltage. Although high-k/metal gate thermal stability has been demonstrated, significant challenges remain to be resolved for future technology nodes. This paper reviews the progress and challenges associated with the introduction of high-k/metal gate transistors, including threshold voltage tuning and gate dielectric thickness scaling, from a materials and process integration perspective.

Evaluation of Drive Current of Hf-based High-k n-type MOSFET with p+ poly-Si or Metal Gate Electrode

Evaluation of Drive Current of Hf-based High-k n-type MOSFET with p+ poly-Si or Metal Gate Electrode

Impact on 1/f Noise due to Gate Electrodes in High-k. Based MOSFETs - A Comparison Study Between Poly-Si Vs Metal Vs FUSI

This work summarizes the effects of using three different gate electrodes - poly-Si, fully silicided (FUSI) and metal (TiN-TaN) on drain current low-frequency (1/f) noise in devices with HfO2 as gate dielectric oxide. While 1/f^b type spectra were observed, the frequency exponent b was found to vary. Number fluctuations were found to be the dominant mechanism for 1/f noise. 1/f noise in poly-Si based oxides show the highest noise while FUSI based devices show the lowest noise. A specific behavior was observed in SiO2 and HfO2 regions of oxide, when the trap profiles are assessed using f x SVg spectra. Constant, decreasing and increasing trap distribution profiles were observed in the HfO2 region for poly-Si, FUSI and metal gate electrodes respectively. Investigations reveal that the oxygen transport during the gate electrode processing were mainly responsible for the observed differences in 1/f noise.

Impact of Gate-Induced Strain on MuGFET Reliability

Hot carrier injection (HCI) reliability and negative bias temperature instability (NBTI) of multiple-gate field-effect transistors (MuGFETs) with highly tensile metal gate electrodes were investigated. The results were compared with those from control devices with poly-Si gate electrodes. It was found that gate strain boosts performance without any detrimental effect on HCI or NBTI reliability, indicating MuGFET compatibility with strained silicon technology. The impact of fin width (W fin) scaling was also investigated. HCI reliability improves with W fin scaling, whereas NBTI reliability degrades with W fin scaling. The same W fin scaling trends were observed in both strained and unstrained devices.

Enhancement of the Flatband Modulation of Ni-Silicided Gates on Hf-Based Dielectrics

For the first time, the effect of the poly-Si gate electrode deposition process on the electrical characteristics of Ni-based fully silicided/HfO2 gate stacks is investigated. The flat- band voltage Vfb of Ni2Si/HfO2 (or Ni3Si/HfO2) with a physical vapor deposited (PVD) Si electrode was found to significantly shift to the positive direction by 0.27 V (or 0.15 V), compared to the case with a chemical vapor deposited (CVD) Si electrode. On the contrary, the Vfb of NiSi/HfO2 with a PVD Si electrode slightly shifts to the negative direction from that with a CVD Si electrode (~0.05 V). Further, La is incorporated into HfO2 to enhance the Vfb modulation of NiXSi gates with a PVD Si gate to near the conduction band edge of Si (~4.0 eV). We believe that the Vfb shift of NiXSi/HfO2 is attributed to the release of Fermi-level pinning at the interface between the Si gate electrode and HfO2, arising from the different Si electrode formation process.

Performance Comparison of Ultrathin Fully Depleted Silicon-on-Insulator Inversion-, Intrinsic-, and Accumulation-Mode Metal–Oxide–Semiconductor Field-Effect Transistors

This work demonstrates the performance comparison of ultrathin fully depleted (FD) silicon on insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) with various structures. The current drivability and immunity to the short channel effect are analyzed for FD-SOI n-channel MOSFETs (nMOSFETs) with various SOI layer thickness and SOI layer dopant concentrations based on the device simulation study. The SOI layer dopant concentrations are widely varied from conventional inversion-mode MOSFET, undoped-mode (intrinsic-mode) to the accumulation-mode MOSFET, where the accumulation-mode MOSFETs has the same dopant type in SOI layer as those of the source and the drain regions. The results suggest that the short channel effect immunity becomes comparable among various SOI layer dopant concentrations when SOI layer thickness is less than 10 nm. The current drivability is higher in the order of accumulation-, intrinsic-, and inversion-mode MOSFETs, and the mechanism of the current drivability increase is explained. In addition, accumulation-mode MOSFETs with polycrystalline silicon (poly-Si) gate electrode can maintain their high current drivability even for short channel generation because the gate capacitance decrease due to the poly-Si depletion effect does not arise. Thus, accumulation-mode MOSFETs can maximize the performance of the ultrathin FD-SOI MOSFETs.

Highly Manufacturable and Reliable HfSiON N-FET With Poly-Si/a-Si Stacked Gate for LSTP Applications

We have proposed a novel poly-Si/a-Si/HfSiON transistor to enhance reliabilities without performance degradation for a 65-nm-node low standby power (LSTP) application. By insertion of a thin amorphous-Si layer between the Poly-Si gate electrode and HfSiON, both phosphorus penetration from gate electrode and a reaction at gate electrode/HfSiON interface are successfully suppressed, so that positive bias temperature instability, one of the biggest issues for high-k gate dielectric, is drastically improved by two orders of magnitude. By carefully optimizing the gate stack structure of HfSiON, the HfSiON device can satisfy both lower gate leakage and gate-induced drain leakage at the same time. As a result, an excellent Ion- Istandby (= Ig + loff) characteristic can be achieved, compared to the conventional SiON device. The a-Si insertion technique can realize the combination between the high-k gate dielectric and Poly-Si for future LSTP applications.