poly-Si Gate Electrode Research Articles

Process Characterization and Control of Polycrystalline SiGe as the Gate Electrode in CMOS Fabrication

Polycrystalline (poly-SiGe) films have been proposed as a promising alternative to the currently employed polycrystalline silicon (poly-Si) gate electrode for complementary metal-oxide-semiconductor (CMOS) field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion than that of poly-Si gate. The use of Poly-SiGe as the gate electrode, however, has serious implications on transistor fabrication processes such as plasma dry etching, resist ashing, wafer cleaning, and oxidation. In this work, we investigate the impact of these processes on the polycrystalline profile and the critical dimension (CD) of the gate electrode. The process improvements and an integration scheme using an oxide liner are presented to minimize the profile and CD variations introduced by the fabrication processes. © 2004 The Electrochemical Society. All rights reserved.

Origin of Flatband Voltage Shift in Poly-Si/Hf-Based High-k Gate Dielectrics and Flatband Voltage Dependence on Gate Stack Structure

Hafnium silicate films (HfSiO) were studied to assess the origin of the flatband voltage (Vfb) shift relative to SiO2. We systematically investigated its dependence on the structure of the film stack and the gate electrodes. Our experimental results indicate that the surface composition of Hf is the most critical factor in controlling the Vfb shift. We also found that the poly-Si deposition process or impurity boron in the poly-Si gate electrode did not give rise to an additional fixed charge that can account for the huge Vfb shift. In addition, we found that the shift occurred even before activation annealing of the ion-implanted poly-Si gate electrode. The results clearly demonstrate that the Vfb shift results from the Hf-originated defects at the poly-Si/HfSiO interface. We also discuss the suitable structure for reducing the huge Vfb shift by decreasing the number of Hf atoms near the interface of the poly-Si, for example, by reducing the Hf content and/or by adding a thin cap layer. These are both effective methods of reducing the Vfb shift.

Backside-SIMS profiling of dopants in thin Hf silicate film

Boron diffusion from B-doped polycrystalline silicon through Hf silicate gate dielectric films into Si substrate was investigated. The dopant penetrated into the Si substrate as a result of high-temperature processing. This dopant penetration is a significant problem because it induces a gate threshold voltage shift. Therefore, backside-SIMS was applied to investigate the dopant diffusion profile in thin Hf silicate films. Backside-SIMS makes it possible to measure the dopant profile in Hf silicate films accurately without remnant surface species and atomic mixing effects from the high-doped poly-Si gate electrode. Using backside-SIMS analysis, it was confirmed experimentally that the introduction of N into Hf silicate films is effective for suppressing dopant diffusion.

Highly Selective Removal of Residual Deposited Films and Oxide Hard Masks on Polysilicon Gate Electrodes in Anhydrous HF Gases

This paper presents new vapor-phase HF processes, developed for highly selective removal of residual deposited films of etch by-products and oxide hard masks, following polysilicon gate etching. Etching of thin gate oxides in anhydrous HF gases, after exposure to an HBr/O2 plasma in the gate etch process, was investigated by X-ray photoelectron spectroscopy and transmission electron microscopy. During exposure to an HBr/O2 plasma, a SiBrxOy layer was formed at the near-surface region of the gate oxide. The delay or incubation time to start etching in HF gases was different between the SiBrxOy and underlying undamaged SiO2 layers. Moreover, the etch rates of SiBrxOy and chemical-vapor-deposition oxides used as a mask material were much higher than that of SiO2. By utilizing these differences in incubation time and etch rate, sidewall deposition films and oxide masks on poly-Si gate electrodes were completely removed without side etching or notching of thin gate oxides.

Reliability Characteristics of poly Si-gated High Quality Chemical Vapor Deposition Hafnium Oxide Gate Dielectric

In this paper, reliability characteristics of chemical vapor deposition (CVD) HfO2 gate stacks with n+-poly-Si gate electrode are investigated systematically, along with long-term lifetime projection. The area dependence and critical defect density of CVD HfO2 gate stacks have been investigated and compared to that of SiO2. Results show that in addition to the significant reduction of tunneling leakage current by a factor of 103–104, a comparable Weibull slope factor and critical defect density are obtained from a high quality CVD HfO2 mainly due to the thicker physical thickness, compare to SiO2. Considering the cumulative impact of temperature acceleration at 150°C, scaling of an effective gate oxide area of 0.1 cm2 and a maximum allowed fraction of failures of 0.01%, the maximum allowed operating voltage is projected to be ∼0.85 V for HfO2/poly-Si gate stack with equivalent oxide thickness (EOT) = 14.5 Å.

Effect of Post-metallization Annealing for Alternative Gate Stack Devices

The effect of the post-metallization annealing of devices having or dielectrics and poly-Si or TaN gate electrodes was studied. Forming gas (10% annealing at 400°C enhanced drive current and channel mobility of devices having 1.2 nm gate dielectrics, by eliminating interface states. Post-metal annealing in 10% for 1.2 nm gate dielectrics resulted in larger enhancements in drive current and device channel mobility than forming gas annealing. Similar enhancements of the device characteristics were observed in (300 mV shift in both flatband and threshold voltage) and (200 mV shift only in threshold voltage) materials. Annealing in pure nitrogen was found to degrade the dielectric quality of including a decrease in device current and 50% lower capacitance. © 2004 The Electrochemical Society. All rights reserved.

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

Thermally stable, high-quality ultrathin (EOT=13 A) CVD HfAlO gate dielectrics with poly-Si gate electrode have been investigated for the first time. Results demonstrate that while in situ doping with Al significantly increases the crystallization temperature of HfO/sub 2/ up to 900/spl deg/C and improves its thermal stability, it also introduces negative fixed oxide charges due to Al accumulation at the HfAlO-Si interface, resulting in mobility degradation. The effects of Al concentration on crystallization temperature, fixed oxide charge density, and mobility degradation in HfAlO have been characterized and correlated.

Suppression of Stress-Induced Leakage Current of Wet and Dry SiO2 by SiD4 Poly-Si Gate Electrode

In this paper, we report on the effect of deuterated poly-Si deposition on stress-induced leakage current (SILC) under Fowler–Nordheim (F–N) electron injection. A deuterated poly-Si gate electrode was deposited on wet and dry thin gate oxide films by utilizing deuterated monosilane (SiD4) gas, as a substitute for hydrogenated monosilane (SiH4) gas. As a result, it was found that SILC values of both wet and dry oxides were clearly suppressed by the deuterated poly-Si gate electrode. Experimental results for the depth profiles of the introduced-deuterium atoms indicated that a large amount of deuterium is introduced into the gate oxide films after the deuterated poly-Si deposition. Furthermore, it was found that hydrogen concentration in a wet oxide film decreases by high-temperature deuterium annealing, while deuterium concentration increases. It is inferred that both high concentration of deuterium and high-temperature annealing for gate doping after poly-Si deposition bring about the suppression of SILC due to the efficient replacement of hydrogen with deuterium in gate oxide films.

Electrical properties and thermal stability of CVD HfOxNy gate dielectric with poly-Si gate electrode

High-quality, ultrathin chemical vapor deposition (CVD) hafnium oxynitride (HfOxNy) gate dielectric with poly-silicon (Si) gate electrode has been investigated for the first time. This CVD HfOxNy gate dielectric film remains amorphous after 950 /spl deg/C N/sub 2/ annealing. Compared with HfO/sub 2/ films with poly-Si gate electrode and similar equivalent oxide thickness (EOT), CVD HfOxNy shows significantly reduction in leakage-current density and boron penetration and superior thermal and electrical stability.

Properties of Polycrystalline Si1 − xGex Films Grown by Ultrahigh Vacuum CVD Using Si2 H 6 and GeH4

Polycrystalline films have been suggested as a promising alternative to the currently employed polycrystalline silicon (poly-Si) gate electrode for complementary metal oxide semiconductor field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion effect than that of poly-Si gates. We investigated the formation of poly- films by using ultrahigh vacuum chemical vapor deposition CVD with and gases, and studied their physical properties as well as electrical characteristics. The deposition rate and Ge content of poly- films increased linearly with the flux of up to a critical flux, while, above this critical flux, it is slightly changed. The resistivity of poly- films decreased as the Ge content increased, and was about one-half of that of poly-Si films at a Ge content of 45%. The capacitance-voltage measurements of metal oxide semiconductor capacitor structures with gates demonstrated that the flatband voltage of the films was lower than that of poly Si films by 0.2 V. In addition, the changes of flatband voltage with the dosage of boron and the sudden decrease of accumulation capacitance in the gate structure were investigated. Leakage current levels increased slightly due to the difference in with the increase of Ge content in poly films. © 2003 The Electrochemical Society. All rights reserved.

Scalability of MOCVD-deposited Hafnium Oxide

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

Ellipsometry Measurement Accuracy of Gate Oxides under Polysilicon

ABSTRACTPrecisely controlling the thickness of ultrathin silicon dioxide (SiO2) gate dielectric films is critical for high yield advanced generation semiconductor manufacturing. Advanced methods for producing ultrathin gates deposit both the gate dielectric and the polysilicon (poly-Si) gate electrode in a single cluster tool. This avoids the opportunity for adsorption of molecular airborne contamination (MAC) between deposition of the two layers, but necessitates measuring gate oxide thickness through a thick poly-Si layer.Variations in poly-Si grain size, amorphous silicon content, and roughness, make it very difficult to model the optical feedback in the visible spectral range to resolve ultrathin (10–20 Å) gate oxides with sufficient accuracy and repeatability for process control.This paper studies the optical behavior of the poly-Si/dielectric filmstack from 190 nm to 900 nm and the physical properties of the poly-Si layer. A more accurate modeling method is proposed to characterize the poly-Si and its top roughness layer using effective medium approximation (EMA) models. Using the new model, both a spectroscopic ellipsometer (SE) and a multi-angle multi-wavelength laser ellipsometer (MWLE) were employed to measure wafers with different poly-Si and gate oxide thicknesses. TEM was used to characterize the film thickness while roughness was determined using AFM. Good correlation was obtained between the TEM, AFM, and ellipsometry results. Excellent repeatability (0.04 Å 1σ on a 15 Å gate oxide for 10 days) and across the wafer uniformity (0.2 Å 1σ for a 49-point map) were also achieved when measuring gate dielectric films under the poly-Si with the MWLE.

Suppression of stress-induced leakage current after Fowler-Nordheim stressing by deuterium pyrogenic oxidation and deuterated poly-Si deposition

Reports on the effect of deuterium incorporation into gate oxide on stress-induced leakage current (SILC) under Fowler-Nordheim (F-N) electron injection. Deuterium atoms were introduced during the growth of the gate oxide by deuterium pyrogenic oxidation. A deuterated poly-Si film was also utilized as a gate electrode. The deuterated poly-Si gate electrode was deposited by deuterated monosilane (SiD/sub 4/) gas, as a substitute for hydrogenated monosilane (SiH/sub 4/) gas. The properties of the deuterated oxide were compared with those of deuterium-annealed oxide, i.e., the conventional method for deuterium incorporation into gate oxide. As a result, it was found that SILC after both polarities of F-N stressing was clearly suppressed by the use of both the deuterium pyrogenic oxide and the deuterated poly-Si gate. Experimental results for the depth profiles and thermal desorption characteristics of introduced-deuterium atoms, compared with the case of the deuterium annealing, indicated that both the deuterium incorporation not only into the Si/SiO/sub 2/ interface but also into bulk-SiO/sub 2/ and the more stable chemical bonding of deuterium atoms are realized by deuterium pyrogenic oxidation.

Si – SiO 2 barrier height and its temperature dependence in metal-oxide-semiconductor structures with ultrathin gate oxide

The potential distribution across n+ polycristalline silicon (poly-Si)/SiO2/Si(p) structures, with an oxide layer thinner than 4 nm, was determined using a full quantum self-consistent model. When applied to capacitance–voltage measurements, it allows an accurate determination of the oxide thickness tox to be made. When applied to current–voltage measurements, in the Fowler–Nordheim regime, it leads to an accurate determination of the barrier height Φ at the interface between the emitting poly-Si gate electrode and the oxide, over a temperature range 20–250 °C. The results show a constant Φ(0 K) for 3 nm<tox⩽9 nm. However, the temperature sensitivity |dΦ/dT| increases from 0.35 to 0.7 meV/K with tox reduction.

A W-spacer GOLD TFT with high performance and high reliability

In this paper, we successfully fabricated Gate-Overlapped Lightly-doped Drain (GOLD) polycrystalline silicon thin-film transistors (poly-Si TFTs) with selectively deposited spacers. Under appropriate deposition conditions, tungsten (W) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared to the conventional poly-Si TFTs without LDD structures, our devices effectively suppress the kink effect and the punch-through phenomenon in short-channel devices. The hot-carrier reliability of our devices is also improved due to the reduced electric field on the drain side. In addition, the transconductance of our devices is compatible to that of conventional devices. This is because the W-spacer acts as a part of gate electrode to induce channel when the device is operated under ON state.

Stress-Induced Voiding in Sputtered TiSi[sub x] Complementary Metal Oxide Silicon Gate Electrodes

We examined the effect of shallow trench isolation (STI) process for the Si ultralarge-scaled integrated circuit on the thermal stability of the bar resistance and the internal void formation of sputtered-/poly-Si gate electrodes. Among the examined process variables, the STI step height can strongly affect the density of voids formed between the poly-Si and the films after the silicidation annealing. Above a STI step height of 400 Å, many clear voids were observed at the STI boundaries by scanning electron microscopy. The thermal stability of the sheet resistance for the /poly-Si gate electrode was investigated at various STI step heights and Si/Ti molar ratios (x) of the composite target. With the decrease in STI step height from 400 to 200 Å, the average at a 0.16 μm linewidth was enhanced from ∼60 to 15 Ω/□ after postannealing at 800°C for 2 h. With the increase of x from 2.1 to 2.3, the thermal stability of was also greatly enhanced showing an average of ∼15 Ω/□ at a 400 Å STI step height. From this study, we suggest that the stress-induced voiding at /poly-Si interface plays one of key roles in thermal degradation of due to the highly developed triaxial stress state in the gate electrode film. © 2002 The Electrochemical Society. All rights reserved.

Compact quantum model for a silicon MOS tunnel diode

A simple model for the simulation of the potential distribution and tunnel currents in MOS structures with metal or poly-Si gate electrodes is proposed. Only the ground quantum state of particles near the Si/SiO 2 interfaces is considered. The model is applicable for all bias conditions and any doping density within Si and poly-Si. Good agreement with experimental data and more refined theories is demonstrated.

The investigation of key technologies for sub-0.1-μm CMOS device fabrication

The fabrication of sub-0.1-/spl mu/m CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p/sup +//n/sup +/ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-/spl mu/m poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-/spl mu/m CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-/spl mu/m CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved.

The Physical and Electrical Properties of Polycrystalline Si1−xGex as a Gate Electrode Material for ULSI CMOS Structures

ABSTRACTPoly Si1−xGex films have been suggested as a promising alternative to the currently employed poly-Si gate electrode for CMOS technology due to lower resistivity, less boron penetration, and less gate depletion effect than those of poly Si gates. We investigated the formation of poly Si1−xGex films grown by UHV CVD using Si2H6 and GeH4 gases, and studied their microstructures as well as their electrical characteristics. The Ge content of the Si1−xGex films increased linearly with the flux of the GeH4 gas up to x=0.3, and saturated above x=0.45. The deposition rate of the poly Si1−xGex films increased linearly with the flux of the GeH4 gas up to x=0.1, above which it is slightly changed. The resistivity of the Si1−xGex films decreased as the Ge content increased, and was about one half of that of poly-Si films at the Ge content of 45%. The C-V measurements of the MOSCAP structures with poly Si1−xGex gates demonstrated that the flat band voltage of the poly Si1−xGex films was lower than that of poly-Si films by 0.2V.

Monolayer-level controlled incorporation of nitrogen in ultrathin gate dielectrics using remote plasma processing: Formation of stacked “N–O–N” gate dielectrics

A low thermal budget approach to monolayer-level controlled incorporation of nitrogen in ultrathin gate dielectrics using 300 °C, remote plasma processing is discussed. Incorporation of approximately 1 ML of nitrogen at the Si–SiO2 interface in an “N–O” structure has been achieved by remote plasma-assisted oxidation of the Si surface followed by N2/He remote plasma nitridation, each at a process pressure of 0.3 Torr. The interface nitridation reduces direct and Fowler–Nordheim tunneling by at least one order of magnitude, independent of film thickness. Incorporation of nitrogen at the top surface of the oxide in a concentration equivalent to about 1–2 molecular layers of silicon nitride in an “O–N” structure has been accomplished by N2/He remote plasma nitridation at 300 °C, but at a reduced process pressure of 0.1 Torr. Top surface nitridation has been shown to prevent boron diffusion out of p+ poly-Si gate electrodes during high-temperature activation anneals, e.g., at 1000 °C. Combining interfacial and top surface nitridation processes resulted in a “N–O–N” structure that was effective in reducing tunneling leakage currents and suppressing boron out-diffusion from p+ poly-Si gate electrodes.