poly-Si Contact Research Articles

Carrier transport through the ultrathin silicon-oxide layer in tunnel oxide passivated contact (TOPCon) c-Si solar cells

The carrier transport through the silicon-oxide (SiOx) layer in tunnel oxide passivated contact (TOPCon) c-Si solar cells has been studied experimentally and by simulation. The current intensity versus voltage (J-V) characteristics of GaIn/n-c-Si/SiOx/n+-poly-Si/Al structures shows a linear Ohmic characteristic, while a non-Ohmic behavior is observed in the samples without the n+-poly-Si contact layer. Conductive Atomic Force Microscopy (c-AFM) images reveal some current spikes on the surface of the samples, which could be related to the transport through pinholes. The simulation results show that 1) a rectification characteristic is obtained when only the tunneling mechanism is included, 2) both the reverse saturation current and the forward current increase when a small amount of transport through pinholes is introduced, and 3) finally a linear Ohmic behavior is observed when the pinhole transport component reaches a certain level. Furthermore, the simulation for whole TOPCon solar cells provides some useful results. For very thin SiOx (< 1.2 nm), the tunneling provides sufficient high tunneling probability and high efficiency TOPCon solar cells can be obtained without transport through pinholes if the passivation is ensured; while for a relatively thick SiOx (> 1.2 nm) without the transport through pinholes, the TOPCon solar cell shows a poor fill factor (FF) with a high series resistance (Rs) because the tunneling does not provide a sufficient high transport channel for carrier transport, and the introduction of a small number of transports through pinholes improves the FF and reduces the Rs, hence improves the PCE. However, a high possibility for carrier going through pinholes reduces all of the performance parameters and degrades PCE for all the cases simulated. Therefore, an optimized pinhole density and size distribution is critical engineering for solar cell performance optimization. However, the establishment of an optimized method to precisely control the pinhole formation and characterization is still on the way.

Optical and electrical characterization of poly-Si/SiOx contacts and their implications on solar cell design

The scope of this paper lies on the phenomenon of free-carrier absorption (FCA) in heavily phosphorus-doped poly-Si layers, applied at solar cells featuring poly-Si/SiOx passivating contacts at the rear. Firstly, FCA is investigated on test structures featuring poly-Si contacts of different thickness and doping level. Secondly, these passivating contacts are integrated into the rear of solar cells featuring a boron-diffused emitter at the front. The infrared (IR) response of the solar cells is analyzed and FCA losses are quantified. In agreement with theory, it is shown that Jsc losses due to FCA increase with poly-Si doping level and thickness. For instance, a total Jsc loss of ~0.5 mA/cm² is obtained for a 145 nm thick poly-Si layer with a doping concentration of 1.9x1020 cm-3.

Effect of the SiO2 interlayer properties with solid-source hydrogenation on passivated contact performance and surface passivation

We investigate how SiOx oxide interlayers prepared by different techniques (chemical, thermal) in combination with hydrogen released from an ALD Al2O3 source layer govern passivation in 1) passivated contacts based on doped poly-Si layers and tunneling SiO2, and 2) wafer surface passivation by Al2O3. Profiles of O and H in these structures with engineered, buried SiOx interlayers were measured by Time-of-Flight SIMS (TOF-SIMS) at nanometer resolution. Passivated contacts perform best with thermally oxidized SiOx, while chemical SiOx causes poly-Si film blistering and performance degradation. ALD Al2O3 acts as passivating H source, significantly improving B-doped and intrinsic poly-Si contacts for IBC cells. Fast-diffusing hydrogen from the Al2O3 source layer appears to penetrate Si wafer thickness, improving the passivation of structures at the opposite side. In contrast to the passivated contacts, chemical SiOx interlayer promotes wafer surface passivation by ALD Al2O3, while similarly thin thermal SiO2 suppresses passivation and built-in charge.

The application of poly-Si/SiOx contacts as passivated top/rear contacts in Si solar cells

Passivated contacts based on low-pressure chemical vapor deposited (LPCVD) heavily-doped poly-Si and a thin SiOx layer are explored for the application in an interdigitated back contact (IBC) solar cell. The poly-Si/SiOx contacts are realized by applying wet-chemically grown SiOx tunnel layers and amorphous Si (a-Si) layers doped via ion implantation that are subsequently transformed into poly-Si/SiOx contacts by a high temperature step. The impact of doping species, ion dose, and poly-Si thickness on the surface passivation of such contacts is studied. Excellent J0 values down to 4.5fA/cm2 were measured for n+-poly-Si contacts, while J0 values as low as 22fA/cm2 were obtained for p+-poly-Si contacts. Solar cells with top/rear poly-Si contacts were processed and Voc values up to 709mV and FF values above 81% were measured. Furthermore, the upper bound for the parasitic absorption losses in 10–40nm thick poly-Si films was quantified to be about 0.5mA/cm2 per 10nm poly-Si layer thickness.

Interfacial Layer Control by Dry Cleaning Technology for Polycrystalline and Single Crystalline Silicon Growth.

Native oxide removal prior to poly-Si contact and epitaxial growth of Si is the most critical technology to ensure process and device performances of poly-Si plugs and selective epitaxial growth (SEG) layers for DRAM, flash memory, and logic device. Recently, dry cleaning process for interfacial oxide removal has attracted a world-wide attention due to its superior passivation properties to conventional wet cleaning processes. In this study, we investigated the surface states of Si substrate during and after dry cleaning process, and the role of atomic elements including fluorine and hydrogen on the properties of subsequent deposited silicon layer using SIMS, XPS, and TEM analysis. The controlling of residual fluorine on the Si surface after dry cleaning is a key factor for clean interface. The mechanism of native oxide re-growth caused by residual fluorine after dry cleaning is proposed based on analytical results.

Process Optimization of CoSi2 Formation on P-Doped Poly-Si by Hot Wall-Based Rapid Thermal Annealing

Low resistivity junctions and low resistivity contacts are essential for fabricating high performance devices with advanced device modes. Significant effort has been expended to develop low resistivity junctions, industry wide. However, low resistivity contact formation has not received significant attention, other than changing the silicide of choice, depending on required minimum line width or device node. Once the candidate silicide material is chosen for the device node, relatively small improvement in resistivity has been made in recent years, despite silicidation process optimization which include modifications of process steps and integration schemes. In this study, we have investigated the effect of annealing temperature and time on the resulting resistivity of Co2Si contacts with P-doped poly-Si using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. The hot wall RTA resulted in significantly (>20%) lower Rs, down to 19.6 ohm/sq. from equivalent RTA process using conventional tungsten halogen lamp-based (cold wall) RTA systems over a very wide process window (RTA temperature and time). Secondary ion mass spectroscopy (SIMS) dopant (P) depth profiling results revealed that the P atoms in the CoSi2 film and at the CoSi2/P-doped poly-Si interface, redistribute very differently under different RTA conditions. The same Rs value can be realized by different P profiles resulting from different RTA conditions. To enable contact resistance reduction, P pile-up near the CoSi2/P-doped poly-Si interface for and to suppress P depletion from P-doped poly-Si layer for resistivity reduction, lower temperature RTA for longer times in the hot wall RTA system was found to be beneficial. Wafers with almost identical P depth profiles after CoSi2 formation RTA in the cold wall RTA and the hot wall RTA systems, still showed an Rs difference of ~20%. The wafers annealed in the hot wall RTA system always showed lower Rs values indicating higher P dopant activation in the P-doped poly-Si layer. The difference in wafer heating mechanisms between the cold wall (lamp-based) RTA and the hot wall (furnace-based) RTA may have played an important role in the dopant activation and Rs differences. Hot wall RTA is very promising for realizing the low resistivity contacts required in advanced high performance devices. The simple change of annealing technique may extend the life cycle of CoSi2/P-doped poly-Si contacts. The Rs response surface (as a function of RTA temperature and time) and SIMS depth profiles of P atoms will be presented at the meeting. Figure 1

Oxygen migration in TiO2-based higher-k gate stacks

We report on the stability of high-permittivity (high-k) TiO2 films incorporated in metal-oxide-silicon capacitor structures with a TiN metal gate electrode, focusing on oxygen migration. Titanium oxide films are deposited by either Ti sputtering [physical vapor deposition (PVD)] followed by radical shower oxidation or by plasma-enhanced atomic layer deposition (PEALD) from titanium isopropoxide (Ti{OCH(CH3)2}4) and O2 plasma. Both PVD and PEALD films result in near-stoichiometric TiO2 prior to high-temperature annealing. We find that dopant activation anneals of TiO2-containing gate stacks at 1000 °C cause 5 Å or more of additional SiO2 to be formed at the gate-dielectric/Si-channel interface. Furthermore, we demonstrate for the first time that oxygen released from TiO2 diffuses through the TiN gate electrode and oxidizes the poly-Si contact. The thickness of this upper SiO2 layer continues to increase with increasing TiO2 thickness, while the thickness of the regrown SiO2 at the gate-dielectric/Si interface saturates. The upper SiO2 layer degrades gate stack capacitance, and simultaneously the oxygen-deficient TiOx becomes a poor insulator. In an attempt to mitigate O loss from the TiO2, top and bottom Al2O3 layers are added to the TiO2 gate dielectric as oxygen barriers. However, they are found to be ineffective, due to Al2O3-TiO2 interdiffusion during activation annealing. Bottom HfO2/Si3N4 interlayers are found to serve as more effective oxygen barriers, reducing, though not preventing, oxygen downdiffusion.

Scaling the MOSFET gate dielectric: From high- k to higher- k? (Invited Paper)

We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high- k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO 2 can be scaled to capacitance equivalent thickness in inversion ( T inv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high- k/channel interfacial layer. This is based on the higher dielectric constant of Si 3N 4 and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher- k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO 2 as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO 2 at the poly-Si contact. We further address the performance of Si 3N 4 and HfO 2 as oxygen barrier layers.

Fabrication of poly-Si TFT with silicided Schottky barrier source/drain, high-κ gate dielectric and metal gate

In this paper, a polycrystalline Si thin film transistor (TFT) with self-aligned silicide Schottky barrier source/drain (SSD), high-κ gate dielectric and metal gate electrode is demonstrated using a simplified low temperature process. After crystallization of α-Si, the thermal budget for device fabrication is reduced to ∼420 °C due to elimination of the implant doping and subsequent activation annealing procedures. P-channel SSD-TFT with PtSi S/D shows an acceptable electrical performance with I on of 1.5 μA/μm for the L g = 2.5 μm device at V gs = V ds = −5 V and I on/ I off ratio of ∼10 4. However, I on of the n-channel SSD-TFT with DySi 2− x S/D is about two orders of magnitude smaller due to the relatively high Schottky barrier height and poor silicide quality of the DySi 2− x /poly-Si contact.

Effect of interfacial resistance and contact size on current crowding at Ni/poly-Si junctions

Self-heating induced by vias and metal/Si contacts in VLSI circuits is undoubtedly one of the most important reliability issues for microelectronic integrated circuits. In this study the thermal characteristics of Ni/poly-Si contacts subject to an electrical current stressing were investigated. The self-heating induced contact temperature rises were measured for the Ni/poly-Si contacts having different contact resistivity, poly-Si sheet resistance and contact geometry. A current crowding phenomenon inside the contact window was analysed numerically based on a two-dimensional computation model. The temperature rise at the Ni/poly-Si contacts was found to increase proportionally with the heating power density of the contact. The extent of current crowding inside the contact window shows a strong dependence on Rs/ρc ratio and contact size. The effect of contact misalignment on the thermal properties of the contact is also discussed.

RuO2/TiN-Based Storage Electrodes for (Ba, Sr)TiO3 Dynamic Random Access Memory Capacitors

Sputtered (Ba, Sr)TiO3 (BST) thin film capacitors have been fabricated with thick RuO2/TiN-based storage electrodes and poly-Si contact plugs, and the electrical properties of the storage electrodes have been studied. The electrode height was higher than 450 nm and the contact size was 0.8×0.8 µ m2. Resistance of the storage electrodes including contact plugs can be evaluated from the dispersion observed in capacitance-frequency measurements. TiN oxidation at the RuO2/TiN interface and native oxide at the TiN/Si contact contribute to the electrode resistance of RuO2/TiN electrodes. With increasing BST deposition temperature, the thickness of oxidized TiN in RuO2/TiN electrodes increases and the electrode resistance increases correspondingly. A Ru layer inserted at the RuO2/TiN interface, a TiN/TiSi2/Si junction and rapid thermal annealing in N2 ambient of the TiN layer are effective ways to reduce the resistance of RuO2/TiN-based electrodes.

Contact barrier application of selective CVD-tungsten in a bipolar device

Abstract A selective CVD-tungsten (SCVD-W) contact barrier of 200 nm thickness, deposited via hydrogen reduction of WF 6 , has been integrated in a bipolar polysilicon self-aligned transistor instead of the proven PtSi/TiW barrier. In order to restrict the silicon consumption at the highly doped polysilicon electrodes as much as possible, a temperature-ramped deposition process has been evaluated which uses a thin tungsten layer, created at 25°C via silicon reduction, as in situ barrier for the further deposition. The integrity of the tungsten diffusion barrier in the poly Si/SCVD-W/AlSiCu metallization has been tested after different postannealing cycles at 450°C. SEM and TEM investigations reveal a relatively smooth tungsten/silicon interface with ≤ 30 nm vertical Si consumption. No clear evidence of wormhole formation could be detected. The input and transfer characteristics of the transistor employing the SCVD-W barrier show an almost ideal performance, evidencing the absence of any degradation effect. The forward current gain is found to be constant over nearly six decades of collector current variation. The emitter-base diode breakdown occurs at a reverse voltage of 6.5 V, which is in close agreement with the best values for the reference metallization. In addition, low contact resistances ( R c ( n + )=0.78 Ω ; R c ( p + )=3.85 Ω) to the highly doped 8 × 2 Ωm 2 poly-Si contacts are reported which are stable even after a 60 min post-annealing treatment.

N-Channel Si-gate process for MNOS EEPROM transistors

An n-channel Si-gate process has been developed to fabricate MNOS EEPROM transistors and fast logic circuits on one chip. The technology proposed involves low thermal oxidation temperatures ≤900° C after nitride deposition, two LOCOS process steps and application of self-aligned overlapped poly-Si contacts. The MNOS memory transistors obtained have been programmed by ±25 V pulses with a write time of t w = 10 ms and an erase time of t e = 100 ms. The retention data have been found to be dependent on nitride thickness and threshold voltage shift, but independent of channel length and channel doping. For devices with a nitride thickness of 30.5 nm the short-term decay rate of 0.6 V/(decade of time) has been determined. Endurance testing using up to 10 7 pulses of ±25 V, 100 μs corresponding to approx. 10 4 write/erase cycles showed no time dependence for the decay rate over the time of 10 5 min in which retention measurements were made.

Transmission electron microscopy of cross sections of large scale integrated circuits

Accurate cross-sectional views of large scale integrated circuits are useful for failure analysis and process evaluation. We have successfully prepared thin sections of finished devices cut perpendicular to the plane of the chip and examined them using transmission electron microscopy. We describe the sectioning procedure and show some cross-sectional views from memory cells of a CMOS RAM with poly-Si gates and tungsten second metal. Examples include micrographs of sections through 1) an IGFET showing the gate edges and the poly-Si grain size distribution, 2) metal to Si, and metal to poly-Si contacts, and 3) poly-Si runners. Each circuit element examined was uniquely identified by mapping the cross section through adjacent memory cells and noting the sequence of elements intersected. This demonstrated ability to examine cross sections of finished devices, consisting of multilayers of materials with different densities, hardness, etc., should prove useful whenever detailed device geometries, crystalline structures, etc., need to be examined in a manner which is relatively free of experimental artifacts.