Pole-zero Doublet Research Articles

In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers

In this paper we explore the effects of pole-zero compensation in the settling performance of operational transconductance amplifiers (OTAs). We carry out the analysis by exploiting a proficient technique that provides an in-depth comprehension of the time domain behavior from the contour plots of the Normalized Settling Time. Starting from the case of a single-pole amplifier, we show the conditions upon which the settling time is degraded by the slow time constant set by the pole-zero doublet. Then, we extend these results to two-pole amplifiers and provide a useful design equation. Design examples of a two-stage and a single-Miller three-stage OTAs confirm the validity of the proposed theoretical models.

An optimization-based methodology for efficient design of fully differential amplifiers

This paper presents an optimization-based design methodology for fully differential amplifiers (FDAs) including the effects of real common-mode feedback (CMFB) circuits as constraints in the design flow. The sizing procedure is performed separately for the main amplifier and for the CMFB circuit, reducing the number of free variables and exploring the design space in a more efficient way. Also, this methodology can be employed to design single and two-stages FDAs whereas a second pole compensation scheme is necessary. In order to validate the proposed methodology, a two-stage fully differential amplifier with a no capacitor feed-forward (NCFF) compensation technique was designed in 0.13 μm CMOS technology with a 1.2 V power supply. The presented results also include a pole-zero pair mismatch analysis and proposes a solution in order to compensate the generated pole-zero doublet that might affect the performance of the amplifier. We can show that this approach reduces the overall static power consumption while satisfying the design specifications.

Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers

Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain greater than 90 dB DC gain, GBW of 325 MHz and better than phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18 m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.

Analysis and compensation of two-pole amplifiers with a pole-zero doublet

A simple representation of a two-pole amplifier with a pole-zero doublet is proposed which can be used in the compensation of transconductance amplifiers. The model is based on the consideration that a pole-zero doublet does not greatly modify the behavior of the closed-loop amplifier. Indeed, assuming an underdamped behavior we have found that the pole-zero doublet only affects the phase margin and, hence, it can accurately be accounted for by properly modifying the second pole of the original two-pole amplifier. Simulations on a two-stage transconductance amplifier show that such a model closely agrees with the time response of the real amplifier.

A high-linearity 50- Omega CMOS differential driver for ISDN applications

A CMOS differential line-driver amplifier that uses positive feedback in the input stage to give transconductance multiplication and pole-zero doublet insertion is reported. The gain-bandwidth product at 60 kHz is 30 MHz and the unity-gain frequency is 2.7 MHz. The circuit operates from a single 5-V power supply and can achieve a total harmonic distortion (THD) of -78 dB for a 6-V/sub pp/ differential output signal at 40 kHz and for a load of 100 Omega and/or 150 pF. For the same measuring condition but with a load of 50 Omega and/or 150 pF, the THD is -73 dB. A power supply rejection of more than 76 dB up to 150 kHz was obtained. The chip occupies an area of 1200 mil/sup 2/ in a 1.5- mu m CMOS technology and dissipates 20 mW. >