Pole-zero Cancellation Circuit Research Articles

Application of pole-zero cancellation circuit in nuclear signal filtering and shaping algorithm

Application of pole-zero cancellation circuit in nuclear signal filtering and shaping algorithm

Analog CMOS Readout Channel for Time and Amplitude Measurements With Radiation Sensitivity Analysis for Gain-Boosting Amplifiers

The front-end readout channel consists of a charge sensitive amplifier (CSA) and two different unipolar-shaping circuits to generate pulses suitable for time and energy measurement. The signal processing chain of the single channel is built of two different parallel processing paths: a fast path with a peaking time of 30 ns to obtain the time of arrival for each particle impinging the detector; and a slow path with a peaking time of 400 ns dedicated for low noise amplitude measurements, which is formed by a pole-zero cancellation circuit and a 4th order complex shaper based on a bridged-T architecture. The tunability of the system is accomplished by the discharge time constant of the CSA in order to accommodate various event rates. The readout system has been implemented in a 180 nm CMOS technology with the size of 525 μm x 290 μm. The building blocks use compact gain-boosting techniques based on quasi-floating gate (QFG) transistors achieving accurate energy measurement with good resolution. The high impedance nodes of QFG transistors require a detailed study of sensitivity to single-effect transients (SET). After carrying out this study, this paper proposes a method to select the value of the QFG capacitors, minimizing the area occupancy while maintaining robustness to radiation. The nonlinearity of the CSA-slow-shaper has been found to be less than 1% over a 10-70 fC input charge. The power dissipation of the readout channel is 4.1 mW with a supply voltage of 1.8 V.

Development of a dedicated front-end electronics for straw tube trackers in the P̄ANDA experiment

The design and tests of front-end electronics for straw tube trackers in the P̄ANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25–67 ns), gain, noise (ENC 800–2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

Design and Analysis of a Low-Power Readout Circuit for CdZnTe Detectors in 0.13-$\mu \text{m}$ CMOS

In this paper, the design of a low-power low-noise readout circuit for cadmium zinc telluride (CdZnTe or CZT) detectors is presented. Such sensors are used in a variety of applications, including medical imaging, security, and astrophysics. The readout circuit includes a charge-sensitive amplifier (CSA), a reset network to accommodate the leakage current of the detector, and a first-order pulse shaper with a pole-zero cancellation circuit. The CSA has two gain settings for 0–5- and 5–45-fC injected charge, and the pulse shaper is designed to provide four different shaping times. The discharge time constant of the CSA can also be adjusted to accommodate various event rates. Furthermore, a comprehensive noise analysis of the readout system is presented. To facilitate the noise analysis, the equivalent noise charge (ENC) equations are derived analytically. The optimization of the noise performance of the front-end circuit is also discussed. The application-specific integrated circuit is fabricated in a 0.13- $\mu \text{m}$ CMOS process. For a detector capacitance of 250 fF, the measured ENC varies from 66 to 101 $\bar {e}$ -rms depending on the peaking time. The measured power consumption of the readout circuit is just under 1 mW from a 1.2 V supply.

Linear Tunable Analog Front-End Electronics for Silicon Charged-Particle Detectors

A linear front-end electronic system based on a high-speed charge sensitive amplifier and a tunable shaping amplifier suitable for silicon detectors has been presented. The designed charge sensitive amplifier features simplicity and compactness. It is based on the combination of a low-noise field-effect transistor input device and a current feedback opamp ensuring high frequency and small rise time. The circuit provides both an energy signal and a timing signal. The shaping amplifier is a fifth-order complex filter based on an opamp- RC topology providing a nearly Gaussian response. The shaper also includes a pole-zero cancellation circuit and a base line restorer to preclude the pileup of subsequent input signals. A control system has been developed to adjust the main parameters of the channel. The designed readout channel has been optimized for a medium energy range up to 50 MeV coupled to silicon detectors up to 100 pF. Its feasibility for nuclear physics applications has been experimentally validated.

Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

The design and the preliminary measurements results of a multichannel, variable gain front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e - at 10 pF input capacitance.

Development of an ASIC for Si/CdTe detectors in a radioactive substance visualizing system

We report on the recent development of a 64-channel analog front-end ASIC for a new gamma-ray imaging system designed to visualize radioactive substances. The imaging system employs a novel Compton camera which consists of silicon (Si) and cadmium telluride (CdTe) detectors. The ASIC is intended for the readout of pixel/pad detectors utilizing Si/CdTe as detector materials, and covers a dynamic range up to 1.4MeV. The readout chip consists of 64 identical signal channels and was implemented with X-FAB 0.35μm CMOS technology. Each channel contains a charge-sensitive amplifier, a pole-zero cancellation circuit, a low-pass filter, a comparator, and a sample-hold circuit, along with a Wilkinson-type A-to-D converter. We observed an equivalent noise charge of ~500 e− and a noise slope of ~5 e−/pF (r.m.s.) with a power consumption of 2.1mW per channel. The chip works well when connected to Schottky CdTe diodes, and delivers spectra with good energy resolution, such as ~12keV (FWHM) at 662keV and ~24keV (FWHM) at 1.33MeV.

Low power low noise high speed tunable CMOS radiation detection system

This paper presents a design of low power and low noise, high speed readout front-end system for semiconductor detectors. The architecture comprises a folded cascode charge sensitive amplifier with gain enhancement, a pole-zero cancellation circuit and a complex shaper circuit with Gm-C topology. A local feedback amplifier based on a wide swing gain boosting scheme with dc level shifting has been used. The system has been fabricated in a 0.13-µm CMOS technology with a single 1.2-V supply voltage. Experimental results show the flexibility of the system where the key parameters, such as decay time, charge gain and peaking time can be tuned. For a nominal peaking time of 150ns the power consumption of the entire channel is less than 5mW. A power consumption-low noise tradeoff will be considered to match a detector capacitance of 5pF. The output pulse has a peak amplitude of 200mV for a charge of 10fC from the detector and achieves a linearity better than 1% up to an input charge range of 12fC.

FSDR16—Fast and Low Noise Multichannel ASIC With 5th Order Complex Shaping Amplifier

We report on the design and measurements of a multichannel ASIC FSDR16 prototype implemented in UMC 180 nm CMOS technology and dedicated for the readout of silicon strip detectors. The FSDR16 chip contains 16 channels with the size of 60 μm × 880 μm each, which are built with: charge sensitive amplifier, pole-zero cancellation circuit, 5th order complex shaper based on the follow-the-leader architecture and 7-bit trim DAC. To achieve low noise performance and high speed analog signal processing, the proper signal shaping has to be involved in order to obtain voltage pulse which is as symmetrical and short as possible at the shaper output. The functionality of the chip allows to make a comparison between a typical CR-(RC)5 shaper based on real poles and a complex semi-Gaussian shaper based on complex poles. We present both, the design procedure of such filters and the measurements results with the emphasis on the spread of analog front-end parameters of these architectures in the multichannel system. The FSDR16 chip characterizes low power dissipation Pdiss = 3.5 mW per single channel. The peaking time tp measured from 1% to the peak of complex semi-Gaussian shaper is set to 75 ns (fast mode) or 180 ns (slow mode). Its architecture allows to obtain a shorter pulse width tw (t w/tp = 2.85) measured form 1% to 1% of the curve than in case of a typical CR-(RC) 5 shaper (tw/t p = 3.54). The front-end electronics has been optimized for detector capacitance of CDET = 30 pF and for fast mode of complex semi-Gaussian shaper an equivalent noise charge ENC = 172 e- +26.2 e- /pF, while for slow mode ENC = 139 e-+18.9 e-/pF.

High speed low power FEE for silicon detectors in nuclear physics applications

A high speed, low power and programmable readout front-end system is presented for silicon detectors to be used in nuclear physics applications. The architecture consists of a folded cascode charge sensitive amplifier, a pole-zero cancellation circuit to eliminate undershoots and a shaper circuit with Gm-C topology. All building blocks include a regulated cascode technique based gain enhancement. Experimental results show that the whole front-end system can be programmed for peaking times of 100ns, 200ns and 400ns maintaining the amplitude of the output voltage. Programmability is achieved by switching different resistors for all poles and zeros. The system has been designed in a 130nm CMOS technology and powered from a 1.2V supply. The output pulse has peak amplitude of 200mV for an input energy of 5MeV from the detector. A power consumption low noise tradeoff will be considered.

An alternative pulse height correction method for pole zero cancellation circuitry

CdTe diode radiation detectors have a problem called the “polarization effect”, which causes CdTe performance to degrade with time. The pulsed bias voltage shutdown technique, in which a bias voltage is turned off and on quickly to recombine the accumulated charges, is used to suppress the effect. When this technique is used with a charge sensitive amplifier equipped with a pole zero cancellation (PZC) circuit, an extra dead time is observed. After a 40ms shutdown, we have to wait for 130ms (net 170ms dead time) due to the saturation of the amplifier when equipped with a PZC stage while only 10ms (net 50ms dead time) is necessary without a PZC. However, PZC is essential to reduce the degradation of the energy resolution in high count rate conditions. Therefore, an alternative technique to avoid degrading the energy resolution in high count rate conditions without a PZC circuit was investigated. A present pulse height was corrected by using both the pulse heights and the elapsed times from the previous events. As a result, in a readout circuit having no PZC circuitry, an energy resolution of 4.7% for a 122keV photo peak at a count rate of 20kcps was obtained when using the correction, and a 9.1% one was obtained without the correction. In addition, an energy resolution of 2.7% for a 662keV photo peak at a count rate of 21kcps was obtained when using the correction, and a 5.3% one was obtained without the correction. It is shown that this new correction method has almost the same effect as PZC circuitry.

Low Noise 64-Channel ASIC for AC and DC Coupled Strip Detectors

A 64-channel ASIC (SXDR64) aimed to work with both AC and DC coupled detectors (Si, CdTe, GaAs), in a single photon counting mode with an energy window has been developed. Every channel of the ASIC consists of a charge sensitive amplifier, a pole-zero cancellation circuit, a 4th order shaper with programmable gain from 14 μV/e- to 50 μV/e- and peaking time from 115 ns to 380 ns, a base-line restorer, two independent discriminators, and two 20-bit counters. Control and readout of the chip are done using on-chip LVDS drivers/receivers. The ASIC can work with input leakage currents in the range from -10 nA up to 7 nA. The ENC obtained with an AC-coupled Si detector is 120 e- for a peaking time Tp=115 ns and Cdet=1.2 pF. With a DC-coupled CdTe detector, the ENC is 210 e- rms for a peaking time Tp=380 ns and Cdet=2 pF and the leakage current Idleak=0.15 nA. The implemented trim DACs at the discriminator inputs allows to minimize the effective threshold spread to 8 e- rms (at one sigma level). The ASIC is designed in a CMOS 0.35 μm technology and its total area is 4800×5000 μm2.

Measurements of low noise 64 channel counting ASIC for Si and CdTe strip detectors

We present the design and performance of a 64-channel ASIC called SXDR64. The circuit is intended to work with DC coupled CdTe detectors as well as with standard AC coupled Si detectors. A single channel of the ASIC consists of a charge sensitive amplifier with a pole-zero cancellation circuit, a 4th order programmable shaper, a base-line restorer and two independent discriminators with 20-bit counters equipped with RAM. The circuit is able to operate correctly with both polarities of the input signal and the detectors leakage current in a few nA range, with the average rate of input pulses up to 1 Mcps.

Development of front-end electronics for the luminosity detector at ILC

The design and measurements of the prototype front-end electronics for the luminosity detector (LumiCal) at the International Linear Collider (ILC) are presented. The challenges of the LumiCal front-end electronics are discussed and the proposed architecture comprising switched-gain preamplifier, pole-zero cancellation circuit (PZC) and switched-gain shaper is described. The preamplifier works for a wide range of input capacitance of up to 100 pF. The input charge dynamic range extends from < 0.4 fC to > 10 pC and covers more than four orders of magnitude. To conform with the timing requirements a peaking time ( T peak ) of about 70 ns was chosen. The prototype ASIC comprising eight channels was designed and fabricated in 0.35 μ m CMOS technology. The results of measurements on gain, noise, high count rate performance and crosstalk are presented.

Development of a low-noise, two-dimensional amplifier array

This paper describes the recent development of a low-noise, two-dimensional analog front-end ASIC for hybrid pixel imaging detectors. Based on the Open-IP LSI project, the ASIC is designed to meet a low-noise requirement of better than 100 e - (rms) with self-triggering capability. The ASIC is intended for the readout of pixel sensors utilizing silicon (Si) and cadmium telluride (CdTe) as detector materials for spectroscopic imaging observations in the X-ray and gamma-ray regions. The readout chip consists of a 4 × 4 matrix of identical 270 μ m × 270 μ m pixel cells and was implemented with TSMC 0.35 - μ m CMOS technology. Each pixel cell contains a charge-sensitive amplifier, pole-zero cancellation circuit, shaper, comparator, and peak hold circuit. Preliminary testing of the ASIC achieved an 88 e - (rms) equivalent noise charge and a 25 e - / pF noise slope with power consumption of 150 μ W per pixel.

Pole-Zero Cancellation Circuit With Pulse Pile-Up Tracking System for Low Noise Charge-Sensitive Amplifiers

Modern X-ray imaging systems require low noise high-count-rate multichannel front-end electronics. Such systems widely use charge-sensitive amplifiers (CSA) with pole-zero cancellation (PZC) circuits for sensor readout. CSAs in multichannel ASICs often include continuous reset systems based on MOS transistors discharging the integrating capacitance. Noise requirements for such front-end electronics put the effective CSA feedback resistance in the range of hundreds of MOmega. On the other hand, the high input pulse rate generates a dc voltage shift at the CSA output that modifies the CSA feedback resistance and degrades the PZC circuit performance. In the paper we analyze these problems and propose a novel circuit solution to bias transistors in the CSA feedback and in the PZC circuit. This bias circuit tracks the above mentioned voltage shift at the CSA output and ensures proper cancellation of the CSA feedback pole even in the case of high rates of input pulses. We present measurements of a test structure for the continuous CSA feedback discharge and implementation of this circuit in a fast multichannel ASIC manufactured in the 0.35 mum CMOS technology. The circuit performance for the high input pulse rate is described in detail.

Measurements of Matching and High Count Rate Performance of Multichannel ASIC for Digital X-Ray Imaging Systems

We present the measurements of matching and high count rate performance of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 mum CMOS process and its total area is 3900 times 5000 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking time of 160 ns. Internal correction DAC implemented in each channel independently ensures a low spread of discriminator effective threshold, namely 0.4 mV at one sigma level. The mean gain in the multichannel ASIC is 54 muV/el, with a good uniformity from channel-to-channel (sd/mean ap 0.8%). Low noise performance and high rate capability have been demonstrated by the measurement up to and above 1 MHz average rate of input signals.

8-channel CMOS preamplifier and shaper with adjustable peaking time and automatic pole-zero cancellation

An 8-channel preamplifier-shaper circuit for use with detectors having a capacitance in the range 20–50pF has been designed in 1.2μ CMOS AMS technology. The shaper is designed so that the peaking time can be adjusted, by steps, in the range 200ns–2μs by simple digital control. The pole-zero cancellation circuit uses an original method of sensing the preamplifier feedback capacitor discharging current and producing an identical current to discharge the capacitance of the pole-zero cancellation circuit. The series noise resistance rs=415Ω has been measured (270Ω of which is the protection resistor). The input capacitance of the preamplifier is 10pF + the strays of the test box 10pF for a total of 20pF. The input PMOS transistor has a gm of 5mA/V (from simulation) at 210μA drain current. The cross-talk between channels is less than 1%.

A multi-channel integrated circuit for the readout of a microstrip gas chamber

The design and test of an 8 channel integrated circuit for the readout of the microstrip gas chamber and other multielectrode detectors are described. The circuit is composed of 8 identical channels, each providing the amplification and the shaping of the signal delivered by the detector. The peaking time of the shaper is 25 ns and the overall amplifier gain is 8mV1000 e−. In addition to the analog output, each channel provides a TTL compatible digital output. The equivalent input noise is less than 700 e− rms and the total dc power consumption is about 5 mW/channel. To avoid a baseline shift due to the tail of the current issued from the detector, an adjustable pole-zero cancellation circuit has been included.