Polar Decoder Research Articles

Low-Latency Segmented List-Pruning Software Polar List Decoder

As the first provably capacity-achieving codes, polar codes have been selected as the coding scheme for 5G enhanced mobile broadband (eMBB) control channels. Furthermore, if the bottleneck in decoding complexity is addressed, polar codes are still promising for long code length scenarios in the future with superior error-correcting performance. Considering the demand of cloud radio access network (C-RAN) in 5G system, the low-latency software polar decoder is studied in this paper. Two novel algorithms are proposed to reduce the latency of the successive cancellation list (SCL) decoding, including the segmented list-pruning (SLP) algorithm and the modified distributed sorting (MDS) algorithm. Moreover, the proposed SLP algorithm improves the decoding performance compared to existing segmentation schemes. In terms of the software implementation, our decoder is nearly $20\%$ faster than the state-of-the-art flexible software polar list decoder.

A Linear-Complexity Channel-Independent Code Construction Method for List Sphere Polar Decoder

Besides the main decoding methods for polar codes such as successive cancellation (SC) decoding, SC list decoding (SCL), and belief propagation (BP) decoding, list sphere decoding (LSD) is an alternative for short codes regarding its lower complexity. Though the improved LSD (ILSD) can achieve better performance than LSD by a synchronous determination scheme, its performance is still not satisfactory with an inappropriate code construction. Good polar code construction is to pick the K most reliable bits from N bits. However, existing polar construction methods are designed for SC or BP decoders. These construction methods might not be suitable for ILSD, which searches based on the Euclidean distance. In this paper, a linear-complexity channel-independent polar code construction method for ILSD is proposed to improve the performance. Considering the Hamming distance as the reliability for ILSD, the proposed method arranges more frozen bits in the early synchro sets and improves the evaluation of the paths at each decoding level. With linear complexity, this method is channel-independent, which is efficient for offline constructions. Numerical results show the proposed construction with low code rates outperforms the state-of-the-art by 2 dB with ILSD.

An Unfolded Pipelined Polar Decoder With Hybrid Number Representations for Multi-User MIMO Systems

Next generation wireless communication introduces ultra high speed and low latency requirements to baseband processors, especially for multi-user multiple-input-multiple-output (MU-MIMO) systems. Polar codes, as the channel coding scheme in the control plane of 5G eMBB scenario, still cannot satisfy the hardware implementation requirements of polar decoders for MU-MIMO systems. In this brief, a high throughput and low latency polar decoder is proposed for MU-MIMO systems. The decoding architecture is fully unfolded to maximize hardware parallelism, and is fully pipelined by decoupling the round-trip scheduling datapath to enable simultaneous processing of multiple codewords. Besides, a hybrid decoding datapath is introduced by proposing complementary decoding units with mixed data representations to reduce hardware complexity. For (1024, 512) polar codes, a decoding throughput of 100.6 Gbps is achieved, and the latency is 0.43 us when 36 users are processed simultaneously.

Hardware Architectures of Visible Light Communication Transmitter and Receiver for Beacon-based Indoor Positioning Systems

High-speed applications of Visible Light Communications have been presented recently in which response times of photodiode-based VLC receivers are critical points. Typical VLC receiver routines, such as soft-decoding of run-length limited (RLL) codes and FEC codes was purely processed on embedded firmware, and potentially cause bottleneck at the receiver. To speed up the performance of receivers, ASIC-based VLC receiver could be the solution. Unfortunately, recent works on soft-decoding of RLL and FEC have shown that they are bulky and time-consuming computations. This causes hardware implementation of VLC receivers becomes heavy and unrealistic. In this paper, we introduce a compact Polar-code-based VLC receivers. in which flicker mitigation of the system can be guaranteed even without RLL codes. In particular, we utilized the centralized bit-probability distribution of a pre-scrambler and a Polar encoder to create a non-RLL flicker mitigation solution. At the receiver, a 3-bit soft-decision filter was implemented to analyze signals received from the VLC channel to extract log-likelihood ratio (LLR) values and feed them to the Polar decoder. Therefore, the proposed receiver could exploit the soft-decoding of the Polar decoder to improve the error-correction performance of the system. Due to the non-RLL characteristic, the receiver has a preeminent code-rate and a reduced complexity compared with RLL-based receivers. We present the proposed VLC receiver along with a novel very-large-scale integration (VLSI) architecture, and a synthesis of our design using FPGA/ASIC synthesis tools.

An Efficient Software List Sphere Decoder for Polar Codes

Polar codes, first achieving the capacity of symmetric binary-input discrete memoryless channels (B-DMCs), have been standardized for eMBB control channels. Since 5G cellular requires flexible architecture which is realized by the software defined networking paradigm, efficient polar decoder is anticipated. Though successive cancellation list (SCL) decoder achieves satisfactory performance, it requires a large amount of memory. For short control channel codes, sphere decoder (SD) is an alternative, but costs unbearable time complexity at low signal-to-noise ratio. List sphere decoder (LSD) abandons the radius and keeps a list of best paths to gain a fixed complexity. However, LSD needs a large list size L for satisfactory performance. In this paper, an efficient software LSD with path pruning and efficient sorting is proposed. We recall the radius as the bound to delete the paths out of the sphere at very early levels. Since L is dynamic, efficient sorting is proposed to reduce the copy operations. Implemented with C++, the proposed decoder can reduce up to 65.3% latency compared with the original LSD, with the same performance and lower complexity.

A Node-Reliability Based CRC-Aided Successive Cancellation List Polar Decoder Architecture Combined With Post-Processing

This paper presents a node-reliability based cyclic redundancy check (CRC)-aided successive cancellation list (NRB CA-SCL) polar decoder architecture, where node reliability is used to determine the number of expanding paths, and a priority-based sorter is devised so as to reduce the number of sorting cycles. In order to reduce the effort required for sorting by the node processor, the expanding segments are generated using off-line flipping patterns. We also propose a post-processing scheme that improves the error-rate performance for the NRB CA-SCL decoders. The proposed techniques are demonstrated by implementing (1024, 512) polar decoders. Compared to other state-of-the-art CA-SCL decoders, the proposed decoder, when the post-processing technique is not included, achieves a better area efficiency. When the post-processing technique is included, the proposed list-16 decoder achieves an area efficiency that is almost 2.5 times greater compared to the latest list-32 CA-SCL decoder, as well as a similar error-rate performance.

Improved Polar Decoder Utilizing Neural Network in Fast Simplified Successive-Cancellation Decoding

This article has been retracted to straighten the academic record. In making this decision the Editorial Board follows COPE's Retraction Guidelines. The aim is to promote the circulation of scientific research by offering an ideal research publication platform with due consideration of internationally accepted standards on publication ethics. The Editorial Board would like to extend its sincere apologies for any inconvenience this retraction may have caused. Please see the article page for more details. The full retraction notice in PDF is preceding the original paper which is marked RETRACTED.

Transformation of Binary Linear Block Codes to Polar Codes With Dynamic Frozen

In this paper, a general transformation of binary linear block codes (BLBCs) to (possibly, multi-kernel) polar codes with dynamic frozen bits is proposed. Through a simple matrix permutation operation, a one-to-one connection between the codewords of a BLBC and its transformed polar code can be established. This transformation allows the usage of any decoding algorithm of polar codes for efficient soft decoding of BLBCs, including the powerful successive cancellation list (SCL) decoding algorithm. Simulations show that the soft SCL polar decoding of BLBCs can achieve a comparative performance to the order statistic decoding (OSD), as well as the maximum-likelihood decoding (MLD) in certain cases, with a much lower computational complexity.

Improved Polar Decoder Utilizing Neural Network in Fast Simplified Successive-Cancellation Decoding

Polar codes using successive-cancellation decoding always suffer from high latency for its serial nature. Fast simplified successive-cancellation decoding algorithm improves the situation in theoretically but not performs well as expected in practical for the workload of nodes identification and the existence of many short blocks. Meanwhile, Neural network (NN) based decoders have appeared as potential candidates to replace conventional decoders for polar codes. But the exponentially increasing training complexity with information bits is unacceptable which means it is only suitable for short codes. In this paper, we present an improvement that increases decoding efficiency without degrading the error-correction performance. The long polar codes are divided into several sub-blocks, some of which can be decoded adopting fast maximum likelihood decoding method and the remained parts are replaced by several short codes NN decoders. The result shows that time steps the proposed algorithm need only equal to 79.8% of fast simplified successive-cancellation decoders require. Moreover, it has up to 21.2 times faster than successive-cancellation decoding algorithm. More importantly, the proposed algorithm decreases the hardness when applying in some degree.

An Efficient Polar Coding Scheme for Uplink Data Transmission in Narrowband Internet of Things Systems

Narrowband Internet of Things (NB-IoT) is an emerging IoT cellular-based wireless technology that builds based on the existing LTE standard to extend its network coverage suited for Low Power Wide Area Network (LPWAN) connectivity. In the NB-IoT system, LTE turbo codes and Cyclic Redundancy Check (CRC) codes are adopted as the main channel coding technique for Narrowband Physical Uplink Shared Channel (NPUSCH). However, turbo codes require iterative decoding algorithm at the expense of high computation complexity of decoding hence is crucial to achieving the LPWAN requirement of NB-IoT systems. Polar codes are best suited in this regard due to its capacity approaching and complexity reduction in short block length code. In this paper, we proposed an efficient polar coding technique using the Belief Propagation (BP) decoding algorithm for uplink data transmission on the NPUSCH channel. Furthermore, the BP algorithm is incorporated with the CRC stoppage criterion to decrease the number of decoding iteration and reduce computational complexity. In this scheme, single-tone numerology of NPUSCH using 3.75 kHz and 15 kHz subcarrier spacing is adopted. Then, the encoded data is generated with different NPUSCH resources. The theoretical formulation and simulation demonstrate that the proposed scheme provides better error rate performance over the adopted LTE turbo codes and other polar decoding algorithms while reducing the computational complexity.

Practical Dynamic SC-Flip Polar Decoders: Algorithm and Implementation

SC-Flip (SCF) is a low-complexity polar code decoding algorithm with improved performance, and is an alternative to high-complexity (CRC)-aided SC-List (CA-SCL) decoding. However, the performance improvement of SCF is limited since it can correct up to only one channel error ($\omega=1$). Dynamic SCF (DSCF) algorithm tackles this problem by tackling multiple errors ($\omega \geq 1$), but it requires logarithmic and exponential computations, which make it infeasible for practical applications. In this work, we propose simplifications and approximations to make DSCF practically feasible. First, we reduce the transcendental computations of DSCF decoding to a constant approximation. Then, we show how to incorporate special node decoding techniques into DSCF algorithm, creating the Fast-DSCF decoding. Next, we reduce the search span within the special nodes to further reduce the computational complexity. Following, we describe a hardware architecture for the Fast-DSCF decoder, in which we introduce additional simplifications such as metric normalization and sorter length reduction. All the simplifications and approximations are shown to have minimal impact on the error-correction performance, and the reported Fast-DSCF decoder is the only SCF-based architecture that can correct multiple errors. The Fast-DSCF decoders synthesized using TSMC $65$nm CMOS technology can achieve a $1.25$, $1.06$ and $0.93$ Gbps throughput for $\omega \in \{1,2,3\}$, respectively. Compared to the state-of-the-art fast CA-SCL decoders with equivalent FER performance, the proposed decoders are up to $5.8\times$ more area-efficient. Finally, observations at energy dissipation indicate that the Fast-DSCF is more energy-efficient than its CA-SCL-based counterparts.

Design of Approximate Polar Maximum-Likelihood Decoder

Polar codes, presented by Arikan, accomplish the ability to acquire nearly error-less communication for any given noisy channel of symmetry with "low encoding and decoding complexities" on a huge set of fundamental channels. As of late, polar code turned into the best ideal error-correcting code from the perspective of information theory because of its quality of channel achieving capacity. Though the successive cancellation decoder with approximate computing is efficient, the proposed ML-based decoder is more efficient than the former. As it is equipped with the Modified Processing Element which shows the better performance with the properties of Median Filter. The proposed ML-based decoder diminishes the area and power consumed and logic utilization. In the present paper, effective polar decoder architecture is structured and executed on FPGA utilizing Vertex 5. Here we examine the proposed unique construction that is appropriate for decoding lengthy polar codes with less equipment multifaceted nature.

Efficient Successive Cancellation Stack Decoder for Polar Codes

As an improved version of successive cancellation (SC) polar decoder, an SC stack (SCS) decoder has been proposed for performance improvement. However, the existing SCS polar decoder suffers a lot from high time complexity at low signal-to-noise ratio (SNR) region and space complexity compared with the SC decoder. To this end, two improved decoders are proposed to reduce time and space complexity in both low and high SNR regions. The first one is the segmented cyclic redundancy check (CRC)-aided SCS (SCA-SCS) decoder, which is based on segmented parity checkers. The second one is the adaptive SCS (ASCS) decoder, which has the flexibility of stack depth and searching width. Furthermore, a channel condition estimator is proposed to select appropriate decision criteria for different SNR scenarios. Results have shown that for the polar code of length 1024 and rate 1/2, two improved SCS decoders can perform better than the traditional SCS decoder. The proposed SCA-SCS decoder and the ASCS decoder can achieve 10.8% and 11.42% time complexity reduction and 31.68% and 60.85% space complexity reduction on average over binary-input additive white Gaussian noise channels (BI-AWGNCs), respectively. Efficient parallel hardware architecture of the SCS polar decoder is first proposed and implemented with 90- and 65-nm technologies. Results have verified its advantages over the state of the art (SOA).

High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder

This brief presents an algorithm for the processing element (PE) of polar decoder based on 2’s complement representation of logarithmic likelihood ratios. It simplifies computation and alleviates critical path delay of PE. In addition, we propose a low complexity algorithm and ${p}$ -node architecture for 2-bits successive-cancellation (SC) polar-decoding scheme. Furthermore, overall SC polar decoder-architecture has been design by incorporating suggested PE architectures as well as ${p}$ -nodes to support code-length and code-rate ( ${r}$ ) of 1024 bits and 1/2, respectively. We have synthesized and post-layout simulated our design in UMC 180-nm CMOS process and it occupies an area of 6.1 mm $^{\boldsymbol 2}$ and operates at a maximum clock frequency of 446 MHz. Our decoder delivers a throughput of $298{r}$ Mb/s which is 16% better than the state-of-the-art implementation. It has achieved better throughput efficiency of $1.01{r}$ compared to recently reported works.

Seamless Optimized LTE Based Mobile Polar Decoder Configuration for Efficient System Integration, Higher Capacity, and Extended Signal Coverage

Mobile communications have seminal importance in telecommunication systems. Thrust challenges in optimization area like capacity to scale up in channels, coverage area and integration of newer techniques with minimum design efforts are targeted in this work. This article proposes a novel technique of configuring the present decoder with Euclidian distance polar-code decoding method at low hardware efforts. The Taguchi optimization technique based on orthogonal array method for polar-code is employed to carry out an experimental design to achieve parameter optimization. This method helps to cram interaction between process parameters. Taguchi optimization analysis of polarization effect of polar code and 8 PSK higher modulations resulted into an increase in channel utilization and bandwidth. The experimentation results proved a low SNR of 9.8 dB and efficient channel utilization of 2.9956 bits/Hz for desired BER of 10- 4, reducing network congestion by 1.5 times. At the same time, yield in bandwidth has sunk from 25 KHz to 16.66 KHz by paying minimum penalty of 1.496 dB in required SNR.

An Improved Software List Sphere Polar Decoder With Synchronous Determination

Being the first codes achieving the capacity of symmetric binary-input discrete memoryless channels, polar codes have been favorable and standardized for enhanced mobile broadband (eMBB) control channels. In future mobile communications, the entire system is required to be flexible and adaptive to varying scenarios. Therefore, efficient software implementation of polar decoder is expected. Existing software successive cancellation list polar decoder can achieve good performance but with a good memory consumption. For short control channel codes, a more memory-efficient alternative is sphere decoder, but its latency gives rise to another issue. Equipped with a breadth-first search to keep a fixed complexity, list sphere decoder (LSD) is also considered. To improve the performance of LSD, a software LSD with synchronous determination is proposed in this paper. We precalculate the synchro sets to improve the decoding, which leads to a performance gain. Meanwhile, the decoding process is simplified due to the precalculation, which attains even lower complexity. Implemented with C++ , the proposed decoder can achieve up to 2 dB performance gain compared with the existing LSD.

An Uplink Non-Orthogonal Multiple Access Method Based on Frozen Bit Patterns of Polar Codes

In this letter, we propose a low-complexity uplink non-orthogonal multiple access (NOMA) scheme based on polar codes. The proposed scheme, called polar coding-based NOMA (PC-NOMA), relies on the separation of user signals transmitted in the same physical resources using binary-valued patterns embedded in the frozen bit locations of polar codes. By means of frozen bit patterns unique to each user, the superimposed user signals are separated at the receiver by an interference-cancelation algorithm and a polar decoder. We demonstrate that the proposed scheme performs well even when the received powers of the multiplexed users are not significantly distinct.

Sphere decoder for polar codes concatenated with cyclic redundancy check

The existing cyclic redundancy check (CRC)-aided successive cancellation list (CA-SCL) decoder partitions the decoding process into two steps,where an SCL is followed by a CRC check. An SCL decoder can approach the maximum-likelihood (ML) decoding performance of the inner polar codes using a sufficiently large list; however, in this case, CRC is only used for performing error detection. Therefore, the decoding performance of the outer CRC is different from that of ML because the errors are not rectified, which degrades the performance of the entire concatenated codes. In this study, we propose a sphere decoder (SD)that can achieve the ML performance of polar codes concatenated with CRC to address the suboptimality of CA-SCL decoding. The proposed SD performs joint decoding of the CRC-polar codes in a single step, thereby avoiding the polar decoding and CRC detection decoding scheme. Because the proposed SD guarantees the ML decoding performance of the CRC-polar concatenated codes, the simulation results demonstrate that the block error rate (BLER) of the proposed SD acts as the lower bound of the CA-SCL decoding performance. Further, a new initial radius selection method is proposed for the SD to reduce the average decoding complexity. The simulations demonstrate that the proposed initial radius selection method reduces more amount of decoding complexity when compared with that reduced using sequential step size methods.

An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems

For a coded massive multi-user multiple-input multiple-output (MIMO) system, a soft-output MIMO detector is essential since it can provide a significant coding gain, e.g., 3 dB, compared with a hard-output detector. However, the computational complexity of the soft-output MIMO detector is usually much greater than that of the hard-output detector. This paper presents the first soft-output message-passing detector (MPD), which is also integrated with a high-throughput polar decoder. The algorithm and architecture are designed concurrently to improve the hardware performance. The proposed techniques, including the adaptive variance estimation and reliable symbol detection, reduce the complexity of the MPD by 98.3%, and enable soft output for the outer polar decoder. Compared to the state-of-the-art hard-output design, the proposed MPD achieves a $5.86\times $ higher throughput-to-area ratio (TAR) with 54.3% lower energy dissipation, despite the soft output. The proposed bidirectional-propagation belief propagation decoder is devised to reduce the critical path and to increase the throughput. The proposed polar decoder can improve the TAR by 35% with a comparable area and energy compared with the state-of-the-art polar decoder. A polar-coded massive MIMO receiver that supports a length-1024 rate-1/2 polar code, 128 receive antennas, and eight users is designed and implemented, and delivers a throughput of 7.61 Gb/s.

Low-complex processing element architecture for successive cancellation decoder

A low-complexity design architecture for implementing the Successive Cancellation (SC) decoding algorithm for polar codes is presented. Hardware design of polar decoders is accomplished using SC decoding due to the reduced intricacy of the algorithm. Merged processing element (MPE) block is the primary area occupying factor of the SC decoder as it incorporates numerous sign and magnitude conversions. Two’s complement method is typically used in the MPE block of SC decoder. In this paper, a low-complex MPE architecture with minimal two’s complement conversion is proposed. A reformulation is also applied to the merged processing elements at the final stage of SC decoder to generate two output bits at a time. The proposed merged processing element thereby reduces the hardware complexity of the SC decoder and also reduces latency by an average of 64%. An SC decoder with code length 1024 and code rate 1/2 was designed and synthesized using 45-nm CMOS technology. The implementation results of the proposed decoder display significant improvement in the Technology Scaled Normalized Throughput (TSNT) value and an average 48% reduction in hardware complexity compared to the prevalent SC decoder architectures. Compared to the conventional SC decoder, the presented method displayed a 23% reduction in area.