Point Multiplication Algorithm Research Articles

An Optimized Point Multiplication Strategy in Elliptic Curve Cryptography for Resource-Constrained Devices

Elliptic curve cryptography (ECC) is widely acknowledged as a method for implementing public key cryptography on devices with limited resources thanks to its use of small keys. A crucial and complex operation in ECC calculations is scalar point multiplication. To improve its execution time and computational complexity in low-power devices, such as embedded systems, several algorithms have been suggested for scalar point multiplication, with each featuring different techniques and mathematical formulas. In this research, we focused on combining some techniques to produce a scalar point multiplication algorithm for elliptic curves over finite fields. The employed methodology involved mathematical analysis to investigate commonly used point multiplication methods. The aim was to propose an efficient algorithm that combined the best computational techniques, resulting in lower computational requirements. The findings show that the proposed method can overcome certain implementation issues found in other multiplication algorithms. In certain scenarios, the proposed method offers a more efficient approach by reducing the number of point doubling and point addition operations on elliptic curves using the inverse of the targeted point.

Power/Area-Efficient ECC Processor Implementation for Resource-Constrained Devices

The use of resource-constrained devices is rising nowadays, and these devices mostly operate with sensitive data. Consequently, security is a key issue for these devices. In this paper, we propose a compact ECC (elliptic curve cryptography) architecture for resource-constrained devices based on López–Dahab (LD) projective point arithmetic operations on GF(2m). To achieve an efficient area-power hardware ECC implementation, an efficient digit-serial multiplier is developed. The proposed multiplier is built on a Bivariate Polynomial Basis representation and a modified Radix-n Interleaved Multiplication (mRnIM) method (for area and power complexities reduction). Furthermore, the LD-Montgomery point multiplication algorithm is adjusted for accurate scheduling in the compact ECC architecture to eliminate data reliance and improve signal management. Meanwhile, the area complexity is reduced by reuse of resources, and clock gating and asynchronous counter are exploited to reduce the power consumption. Finally, the proposed compact ECC architecture is implemented over GF(2m) (m = 163, 233, 283, 409, and 571) on Xilinx FPGAs’ (Field-Programmable Gate Array) Virtex 5, Virtex 6, and Virtex 7, showing that the efficiency of this design outperforms to date when compared to reported works individually. It utilizes less area and consumes low power. The FPGA results clearly demonstrate that the proposed ECC architecture is appropriate for constraint-resources devices.

A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA

This article presents an area-aware unified hardware accelerator of Weierstrass, Edward, and Huff curves over GF(2233) for the point multiplication step in elliptic curve cryptography (ECC). The target implementation platform is a field-programmable gate array (FPGA). In order to explore the design space between processing time and various protection levels, this work employs two different point multiplication algorithms. The first is the Montgomery point multiplication algorithm for the Weierstrass and Edward curves. The second is the Double and Add algorithm for the Binary Huff curve. The area complexity is reduced by efficiently replacing storage elements that result in a 1.93 times decrease in the size of the memory needed. An efficient Karatsuba modular multiplier hardware accelerator is implemented to compute polynomial multiplications. We utilized the square arithmetic unit after the Karatsuba multiplier to execute the quad-block variant of a modular inversion, which preserves lower hardware resources and also reduces clock cycles. Finally, to support three different curves, an efficient controller is implemented. Our unified architecture can operate at a maximum of 294 MHz and utilizes 7423 slices on Virtex-7 FPGA. It takes less computation time than most recent state-of-the-art implementations. Thus, combining different security curves (Weierstrass, Edward, and Huff) in a single design is practical for applications that demand different reliability/security levels.

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor

Due to rapid development in secured technological devices, the efficient implementation of a large field-size elliptic curve cryptosystem (ECC) is becoming demanding in many critical applications. Therefore, this paper presents a new Montgomery point multiplication (PM) algorithm to optimize and balance the signal flow and resource utilization efficiency. Thereafter, we have presented an efficient ECC processor architecture over <inline-formula> <tex-math notation="LaTeX">$GF(2^{m})$ </tex-math></inline-formula> with m &#x003D; 409 and 571 for the proposed Montgomery PM algorithm. Finally, we have given a detailed comparison and performance analysis (in terms of area-delay product) to show that the proposed cryptographic processor has superior performance as compared to the competing designs. The implementation results after place &#x0026; route on Xilinx Virtex 7 and Kintex Ultrascale&#x002B; are provided. The achieved results reveal that the proposed large field-size ECC processor (and the proposed design strategy) can be extended and applied in many security-demanding applications.

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

Cybersecurity is a critical issue for Real-Time IoT applications since high performance and low latencies are required, along with security requirements to protect the large number of attack surfaces to which IoT devices are exposed. Elliptic Curve Cryptography (ECC) is largely adopted in an IoT context to provide security services such as key-exchange and digital signature. For Real-Time IoT applications, hardware acceleration for ECC-based algorithms can be mandatory to meet low-latency and low-power/energy requirements. In this paper, we propose a fast and configurable hardware accelerator for NIST P-256/-521 elliptic curves, developed in the context of the European Processor Initiative. The proposed architecture supports the most used cryptography schemes based on ECC such as Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Elliptic Curve Diffie-Hellman (ECDH) and Elliptic Curve Menezes-Qu-Vanstone (ECMQV). A modified version of Double-And-Add-Always algorithm for Point Multiplication has been proposed, which allows the execution of Point Addition and Doubling operations concurrently and implements countermeasures against power and timing attacks. A simulated approach to extract power traces has been used to assess the effectiveness of the proposed algorithm compared to classical algorithms for Point Multiplication. A constant-time version of the Shamir’s Trick has been adopted to speed-up the Double-Point Multiplication and modular inversion is executed using Fermat’s Little Theorem, reusing the internal modular multipliers. The accelerator has been verified on a Xilinx ZCU106 development board and synthesized on both 45 nm and 7 nm Standard-Cell technologies.

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA.

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over , which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module

In today's technology, a sheer number of Internet of Things applications use hardware security modules for secure communications. The widely used algorithms in security modules, for example, digital signatures and key agreement, are based upon elliptic curve cryptography (ECC). A core operation used in ECC is the point multiplication, which is computationally expensive for many Internet of things applications. In many IoT applications, such as intelligent transportation systems and distributed control systems, thousands of safety messages need to be signed and verified within a very short time-frame. Considerable research has been conducted in the design of a fast elliptic curve arithmetic on finite fields using residue number systems (RNS). In this article, we propose an RNS-based ECC core hardware for the two families of elliptic curves that are short Weierstras and twisted Edwards curves. Specifically, we present RNS implementations for SECP256K1 and ED25519 standard curves. We propose an RNS hardware architecture supporting fast elliptic curve point-addition (ECPA), point-doubling (ECPD), and point-tripling (ECPT). We implemented different ECC point multiplication algorithms on the Xilinx FPGA platform. The test results confirm that the performance of our fully RNS ECC point multiplication is better than the fastest ECC point multiplication cores in the literature.

An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications

This brief presents an energy-efficient elliptic curve cryptography (ECC) processor for Internet of Things (IoT) security applications. The proposed processor supports dual-field computations, and employs various design techniques across the algorithm, architecture, and arithmetic circuit levels to minimize power and energy consumption. The proposed elliptic curve point multiplication (ECPM) algorithm employs signed binary representation (SBR) with the m-ary method to reduce both area and energy consumption, while avoiding attack from simple power analysis (SPA). In addition, the proposed hybrid modular arithmetic architecture effectively increases the hardware utilization to reduce both area and energy cost. Finally, the proposed processor uses an energy-efficient data flow to further minimize memory overhead for group operations. The proposed ECC processor achieves 51.6% and 50.5% lower energy consumption for each GF(p) and GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) ECPM operation, respectively, when compared to state-of-the-art ECC designs.

An area-efficient ECC architecture over GF([formula omitted]) for resource-constrained applications

Elliptic Curve Cryptography (ECC), an asymmetric-key cryptographic system, received extensive research and industry recognition owing to its reliable security with relatively smaller key sizes. It is most effective with resource-constrained applications. The very intensive function in ECC is point-multiplication. In this article, we propose a novel architecture for elliptic curve point-multiplication based on modified Lopez–Dahab–Montgomery(LDM) point-multiplication algorithm to achieve a reduction in hardware complexity and time complexity. The proposed architectural data-path is pipelined and organized to realize finite-field operations i.e., FF-multiplication and FF-square operations, in parallel to reduce the critical-path delay. The FF-operations are scheduled to perform each iteration of point-addition(PA) and point-doubling(PD) operations in eight clock-cycles without data-dependency. The elliptic curve-point-multiplication(ECPM) implementation over the National Institute of Standards and Technology(NIST) recommended binary curve GF(2163) shows that the proposed design achieves point-multiplication in 3.71μs utilizing 8529 LUTs on Xilinx Virtex-7 FPGA. In addition the design achieves an improvement of 36%, 32%, and 39% area-time efficiency when compared to the best existing designs in the literature when implemented over GF(2163), GF(2233) and GF(2283) respectively.

Comparison of scalar point multiplication algorithms in a low resource device

Since it was invented, Elliptic Curve Cryptography (ECC) is considered an ideal choice for implementing public key cryptography in resource constrained devices, thanks to its small keys. Scalar point multiplication is the central and the complex operation in the cryptographic computations of ECC that requires a lot of optimizations on execution time and energy consumption especially in low computing power devices such as embedded systems. Thus, many scalar point multiplication algorithms are proposed, each using their own computational techniques and mathematical formulas. In this paper, we have combined the computational techniques with some optimized mathematical formulas and we have implemented them on some Elliptic Curves scalar point multiplication algorithms over finite field. The aim of this work is to identify the most efficient algorithm that combine the best computational technique and the mathematical formulas, and consequently offer less-memory requirements and faster field arithmetic operations. The results show that Montgomery ladder algorithm in co-Z addition with update formula gives better results compared to the other algorithms implemented in this paper.

IMAGING: In-Memory AlGorithms for Image processiNG

Data-intensive applications such as image processing suffer from massive data movement between memory and processing units. The severe limitations on system performance and energy efficiency imposed by this data movement are further exacerbated with any increase in the distance the data must travel. This data transfer and its associated obstacles could be eliminated by the use of emerging non-volatile resistive memory technologies (memristors) that make it possible to both store and process data within the same memory cells. In this paper, we propose four in-memory algorithms for efficient execution of fixed point multiplication using MAGIC gates. These algorithms achieve much better latency and throughput than a previous work and significantly reduce the area cost. They can thus be feasibly implemented inside the size-limited memory arrays. We use these fixed point multiplication algorithms to efficiently perform more complex in-memory operations such as image convolution and further show how to partition large images to multiple memory arrays so as to maximize the parallelism. All the proposed algorithms are evaluated and verified using a cycle-accurate and functional simulator. Our algorithms provide on average $200\times $ better performance over state-of-the-art APIM, a processing in-memory architecture for data intensive applications.

High-Performance Pipelined Architecture of Point Multiplication on Koblitz Curves

Point multiplication is the key operation that dominates the speed and area of each elliptic curve cryptosystem. In this brief, we propose a highly efficient architecture for point multiplication on Koblitz curves. The right-to-left point multiplication algorithm is adopted to allow parallel computation of Frobenius maps and point additions. In order to achieve short latency as well as high frequency, we explore operation rescheduling in consecutive point additions with a pipelined bit-parallel finite field multiplier accumulator. Furthermore, the pipelined mixed-form double-digit scalar converter with compact recoding is employed to reduce the wait time and consumed logic resources by scalar conversion. Fast inversion based on optimal addition chains is used to further reduce the latency. Implementation results on Xilinx Virtex V show that the proposed architecture can perform a point multiplication in as few as 2.50, 4.09, 5.81, 9.50, $18.51~ {\mu }\text{s}$ over the five NIST Koblitz curves K-163, K-233, K-283, K-409, and K-571, respectively. To the best of our knowledge, the proposed architecture of point multiplication has the fastest speed in comparison to the reported results.

ACryp-Proc: Flexible Asymmetric Crypto Processor for Point Multiplication

Flexibility is one of the driving agents for 5G architecture development to incorporate enhanced mobile broad band, machine type communication (MTC), and ultra-reliable MTC. While considering flexibility in the domain of security/reliability, we present a unified and flexible hardware architecture, implementing point multiplication algorithm for both elliptic curve cryptography (ECC) and Binary Huff Curves (BHC). The proposed architecture can be used in the scenarios where the users can tradeoff between the algorithmic execution time and different reliability/security levels. To establish an area overhead for the unified design, dedicated architectures for ECC and BHC over the $GF(2^{m})$ field are implemented in the first step and compared with state-of-the-art. Then, a unified architecture for ECC and BHC is implemented. The performance results of proposed unified architecture illustrate the trade-off between execution time and security level.

Constructing multidimensional differential addition chains and their applications

We propose new algorithms for constructing multidimensional differential addition chains and for performing multidimensional scalar point multiplication based on these chains. Our algorithms work in any dimension and offer some key efficiency and security features. In particular, our scalar point multiplication algorithm is uniform, it can be parallelized, and differential addition formulas can be deployed. It also allows trading speed for precomputation cost and storage requirements. These key features and our theoretical estimates indicate that this new algorithm may offer some performance advantages over the existing point multiplication algorithms in practice. We also report some experimental results and verify some of our theoretical findings, and a simplistic Magma implementation is provided.

An Efficient and Flexible Hardware Implementation of the Dual-Field Elliptic Curve Cryptographic Processor

Elliptic curve cryptography (ECC) has been widely used for the digital signature to ensure the security in communication. It is important for the ECC processor to support a variety of ECC standards to be compatible with different security applications. Thus, a flexible processor which can support different standards and algorithms is desired. In this paper, an efficient and flexible dual-field ECC processor using the hardware–software approach is presented. The proposed processor can support arbitrary elliptic curve. An elaborate modular arithmetic logic unit is designed. It can perform basic modular arithmetic operations and achieve high efficiency. Based on our designed instruction set, the processor can be programmed to perform various point operations based on different algorithms. To demonstrate the flexibility of our processor, a point multiplication algorithm with power analysis resistance is adopted. Our design is implemented in the field-programmable gate array platform and also in the application-specified integrated circuit. After implemented in the 55 nm CMOS process, the processor takes between 0.60 ms (163 bits ECC) and 6.75 ms (571 bits ECC) to finish one-point multiplication. Compared to other related works, the merits of our ECC processor are the high hardware efficiency and flexibility.

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7).

Design of Double Precision Floating Point Multiplication Algorithm with Vector Support

Design of Double Precision Floating Point Multiplication Algorithm with Vector Support

Parallelization of scalable elliptic curve cryptosystem processors in GF(2m)

The parallelization of scalable elliptic curve cryptography (ECC) processors (ECPs) is investigated in this paper. The proposed scalable ECPs support all 5 pseudo-random curves or all 5 Koblitz curves recommended by the National Institute of Standards and Technology (NIST) without the need to reconfigure the hardware. The proposed ECPs parallelize the finite field arithmetic unit and the elliptic curve point multiplication (ECPM) algorithm to gain performance improvement. The finite field multiplication is separated such that the reduction step is executed in parallel with the next polynomial multiplication. Subsequently, the finite field arithmetic of the ECPs are further parallelized and the performance can be further improved by over 50%. Since the multiplier blocks consume a low number of hardware resources, the latency reduction outweighs the cost of the extra multiplier resulting in more efficient ECP designs. The technique is applied for both pseudo-random curve and Koblitz curve algorithms. A novel ECPM algorithm is also proposed for Koblitz curves that take advantage of the proposed finite field arithmetic architecture. The implementation results show that the proposed parallelized scalable ECPs have better performance compared to state-of-the-art scalable ECPs that support the same set of elliptic curves.

Comparing design approaches for elliptic curve point multiplication over [formula omitted] with polynomial basis representation

Point Multiplication (PM) is considered the most computationally complex and resource hungry Elliptic Curve Cryptography (ECC) mathematical operation. PM hardware accelerator design can follow several approaches that lead to a fast, small or flexible implementation, meeting related application specifications. However, each PM design decision has certain outcomes in utilized hardware resources and computation speed. Such a key design decision is related to the structure of the GF(2k) multipliers to be employed in the PM accelerator. In this paper, we highlight the GF(2k) multiplication role in the overall PM performance and investigate what are the trade-offs on a PM accelerator when using bit serial or bit parallel multiplication approach in terms of speed, chip covered area and flexibility. To achieve this goal, we estimate these tradeoffs for a single point operation and specify realistic design cases for bit serial and bit parallel multiplier based PM design approaches. To evaluate the theoretical modeling, a point operation design methodology based on the parallelism and rescheduling of GF(2k) operations is proposed. This design approach is adapted to two characteristic PM algorithm realizations, the traditional double & add algorithm and the side channel attack resistant Montgomery power ladder algorithm. Our goal is to assess the resulting PM accelerator overall performance so as to achieve high speed with an acceptable cost on chip covered area (hardware resources). Using this methodology, PM is performed in series of GF(2k) parallelism stages. To test the proposed methodology, 8 PM accelerator use cases are identified that can offer high speed, flexibility, side channel attack resistance or small chip covered area. To provide fair comparisons and results, a common PM architecture is devised and the use case PM accelerators are implemented in FPGA technology. Depending on the designers goal, the proposed architectures and 8 implementations can offer the benefit of either high speed (the proposed work is currently one of the fastest known GF(2k) bit parallel multiplier based PM realization) or flexibility with reasonable compromises in chip covered area.

Area Efficient Implementation of Elliptic Curve Point Multiplication Algorithm

Elliptic Curve Cryptography (ECC) has established itself as the most preferred and secured cryptography algorithm for the secure data transfer and secure data storage in embedded system environment. Efficient implementation of point multiplication algorithm is crucial activity for designing area efficient, low footprint ECC cryptoprocessors. In this paper, an area efficient implementation of double point multiplication algorithm over binary elliptic curve is presented. Area analysis of double point multiplication algorithm based on differential addition chains method is carried out and area report is generated. Area optimization is achieved by using pipelined structure and by reutilizing idle resources from previous stages in processing unit. The proposed architecture for double point multiplication is implemented on Xilinx Virtex-4 FPGA device. Architecture is modeled in verilog-HDL and synthesized using Xilinx ISE 14.1 design software and is found to be more efficient in terms of area than the existing such architectures.