PMOS Varactors Research Articles

A high‐linearity LC‐VCO with combined MOS varactors and bulk‐biased PMOS varactors for gain variation compensation

AbstractA high‐linearity LC‐voltage‐controlled oscillator (LC‐VCO) with combined metal‐oxide semiconductor varactors and bulk‐biased P‐channel metal‐oxide semiconductor varactors in parallel is proposed to reduce the VCO‐gain (KVCO) variation and extend the linear range of the control voltage. Fabricated in a 180‐nm complementary metal‐oxide semiconductor process, the proposed topology achieves a low gain variation of less than 6.3% and a tuning range of ~28% operating from 2.31 to 3.06 GHz, corresponding to a linear control voltage range from 0.6 to 1.4 V. The phase noise is measured to be −115.3 dBc/Hz at 1 MHz offset at 3.06 GHz and the figure of merit (FoM) is −181.2 dBc/Hz. The oscillator occupies an area of 0.93 × 0.54 mm and consumes 1.8 mW from mixed 1.2/1.8 V supply voltage.

180 nm NMOS voltage-controlled oscillator for phase-locked loop applications

<p>The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset and a total harmonic distortion (THD) of 3.9%. The proposed design is verified by PSpice simulations. A new criterion is proposed for optimizing NMOS LC oscillators.</p>

A 6.7 GHz, 89.33 μW Power and 81.26% Tuning Range Dual Input Ring VCO with PMOS Varactor

This paper proposes an improved two-stage and four-stage CMOS ring-Voltage Controlled Oscillator (VCO) design with large frequency at output, improved phase noise, and reduced consumption of power. A PMOS varactor is used in conventional circuit to obtain high tuning-range and very low consumption of power. Cadence Virtuoso 90 nm technology was used to simulate this differential ring-VCO with the proposed dual input differential delay cell. This two-stage and four-stage design gives wider range of tuning from 1.254 to 6.694 GHz (81.26%) and 1.821 to 5.259 GHz (65.37%), respectively, with the change in [Formula: see text] from 0.1 to 1 V. The power-consumption of two-stage ring VCO and four-stage ring VCO varies from 48.02 to 89.33 [Formula: see text] and 66.81 to 157.02 [Formula: see text] respectively. The proposed two-stage and four-stage VCO exhibits −114.46 and −111.06 dBc/Hz at 1 MHz offset from 6.694 and 5.259 GHz carrier frequency, respectively. The proposed two-stage and four-stage differential ring-VCO results in wider tuning range and very low consumption of power and an improved figure of merit and phase-noise.

Improving linearity in MOS varactor based VCOs by means of the output quiescent bias point

This paper presents a CMOS based LC tank VCO topology improving the tuning range linearity. The VCO tuning range is linearized with PMOS varactors which remain in the inversion region for an extended range of the control voltage. This is achieved with the design of the quiescent operating point in the VCO's output nodes with a value close to the voltage rails, letting the varactors to behave quasi linearly in the achievable VCO tuning range. The experimental results of a VCO in a CMOS 0.35µm process show a linear tuning range improvement of 75% of the control voltage in the (1.43–1.55)GHz range, with a minimum VCO gain variation compared to similar architectures. The results show a phase noise improvement from −94dBc/Hz to −124dBc/Hz @600kHz offset from the carrier with an overall reduced amplitude noise for the VCO.

Design of low power CMOS LC VCO for direct conversion transceiver

A low power 1.2 GHz LC differential voltage-controll ed oscillator (VCO) is designed for a direct conversion transceiver in 130 nm CMOS processes. It consists of a complementary current reuse structure and LC tank circuit. To produce a good tuning range and reduce losses in the tank circuit, modied inversion mode PMOS varactors and an on-chip inductor are designed with a better quality factor. The icker noise is reduced by the PMOS tail current source connected in parallel with the capacitance. The 1.2 GHz LC VCO achieves a phase noise value of {132 dBc/Hz at 1 MHz offset and the tuning range of the oscillator is from 1.128 to 1.27 GHz for the control voltage, tuning from 0 to 1.5 V. It dissipates 245 W power at 0.8 V supply voltage and thegure of merit is calculated as {199.7 dBc/Hz.

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- $$\upmu \hbox {m}$$ μ m CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of $$-$$ - 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only $$594~\upmu \hbox {W}$$ 594 μ W in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is $$-$$ - 192.1 dB at 3 GHz.

Quadrature Sine Wave Signals Generated by Selection Topology and its Components

This paper presents how to generate high frequency quadrature sinewave signals by selection topology and its active and passive components. Also, presents how to choose the value of inductor by different ways followed by performance comparison of various VCO topologies. The overall performance is displayed by all-pMOS VCO in terms of supply voltage and tuning range. The performance comparison of all-pMOS LC-VCO using various capacitive loads is discussed. All-pMOS LC-VCO with MOS capacitor switched capacitor array (SCA) followed by divider using CML latch without fixed tail current source is used for generation of high linearity quadrature signals. A three 2.4/4.8 GHz CMOS Quadrature Voltage Controlled Oscillators (QVCO's) tuned by a diode varactor, inversion- mode pMOS varactor and an accumulation-mode nMOS varactor, respectively. The performance comparison of different varactors QVCO is simulated in terms of frequency range, tuning range, harmonic distortion and power consumption. The overall performance is displayed by inversion mode pMOS varactor QVCO. However, all the performances of varactor QVCO's are significantly closer with all-pMOS LC VCO compared with other VCO topologies like all-nMOS LC-VCO and complementary cross coupled LC- VCO, due to low dc impedance path between the varactor to ground terminal. It displayed the power consumption of all varactor QVCO's are equal. The QVCO's were implemented in a 0.18 µm standard CMOS technology as the supply voltage is 1 V. The pre and post layout simulation results are compared in terms of tuning range, phase noise, power dissipation, and harmonic distortion, self oscillation frequency of divider and reference voltage of inversion mode pMOS varctor QVCO.

A 2.4GHz to 3.86GHz digitally controlled oscillator with 18.5kHz frequency resolution using single PMOS varactor

A 2.4GHz to 3.86GHz digitally controlled oscillator with 18.5kHz frequency resolution using single PMOS varactor

DAC를 이용한 고해상도 DCO 설계

기존에 ADPLL(All Digital Phase Locked Loop)에서는 DCO(Digitally Controlled Oscillator)의 해상도를 향상시키기 위해 주로 디더링(dithering) 기법이 사용되었다. 본 논문에서는 디더링 방식에서 발생하는 문제점을 보안하고자 DAC(Digital-to-Analog Converter)를 이용한 DCO의 해상도 확보 방법을 제안하였다. 주파수 컨트롤은 coarse와 fine 바랙터(varactor) bank 그리고 DAC 바랙터에 의해서 이루어지며, coarse와 fine bank는 PMOS 바랙터로, DAC 바랙터는 NMOS 바랙터로 구현하였다. 각 바랙터 bank는 8비트의 디지털 입력으로 컨트롤된다. <TEX>$0.13{\mu}m$</TEX> CMOS 공정을 이용하여 설계된 DCO는 약 2.8GHz~3.5GHz의 주파수 범위에서 발진하며 660MHz의 대역폭을 갖는다. DCO의 출력 주파수를 측정한 결과 해상도는 2.8GHz대역에서 73Hz이다. 설계된 DCO는 1M 옵셋(offset)에서 -119dBc/Hz의 위상 잡음 특성을 보이며, 1.2V 전원에서 4.2mA의 전류를 소모한다. 칩 면적은 PAD를 포함하여 <TEX>$1.3mm{\times}1.3mm$</TEX>이다. Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a <TEX>$0.13{\mu}m$</TEX> CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is <TEX>$1.3mm{\times}1.3mm$</TEX> including pads.

A 5.8-GHz High-Frequency Resolution Digitally Controlled Oscillator Using the Difference Between Inversion and Accumulation Mode Capacitance of pMOS Varactors

This paper proposes an oppositely coupled varactor pair and reports the measured results for applying to a test digitally controlled oscillator (DCO). The pair exploits the differences between the accumulation region capacitance and inversion region capacitance of pMOS varactors. The novel varactor pairs provide much smaller switchable capacitances than those of other approaches, and hence, the test DCO for verifying the property of the pair achieves the high-frequency resolution. The pairs and test DCO are implemented in a 0.18-μm CMOS process. The switchable discrete capacitance of 32 aF is obtained by using the novel varactor pairs, and the test DCO has a frequency resolution of about 110 kHz at 5.8 GHz. Furthermore, ΔC of 4-aF and 14-kHz frequency resolution can be obtained through the dithering processes. The test DCO achieves a low phase noise of -117.6 dBc/Hz at 1-MHz offset from 5.8 GHz.

A high performance 1 GHz voltage controlled oscillator using neural system architecture

In this paper, an improved voltage controlled oscillator scheme with temperature compensated frequency, a wide linear range, low phase noise and low power dissipation is presented for application in transmitting signals of gas sensors from mines using RF communication. The basic unit of the oscillator is a ring based differential amplifier incorporating temperature compensated voltage dependent PMOS capacitors and standard PMOS triode connected load with temperature compensated biasing scheme. The increased nonlinearity in the presence of PMOS capaciors is reduced to 0.001% using a digitally programmable neural architecture which is simulated in the mixed signal domain of SYNOPSYS. Additionally, the temperature compensated PMOS capacitor improves the sensitivity of the VCO and the standard temperature compensated biasing scheme of the PMOS triode connected load reduces the drift in amplitude with temperature variation. The PMOS varactor lowers the phase noise of the VCO compared to parasitic capacitors without increasing the power dissipation. The entire VCO is designed using 0.18 μm typical technology of TSMC with 1.8 V power supply. The tuning range of the VCO is 0.3---1.7 V, maximum frequency is 1 GHz with a linear change of around 750 MHz, temperature sensitivity and power consumption are around 50 ppm/°C and 2 mW respectively. The phase noise is obtained to be around ?123dBc/Hz at 1 MHz offset frequency.

Digitally controlled oscillator with high frequency resolution using novel varactor bank

An LC tank based digitally controlled oscillator (DCO) with high frequency resolution by using a novel varactor bank is presented. The proposed varactor exploits the opposite C-V characteristics of the PMOS and NMOS and achieves unit capacitance that is an order of magnitude less than a simple PMOS or NMOS varactor. A prototype DCO is designed in 65 nm CMOS process, and simulation results show that the DCO achieves a frequency range of 4.5- 5.5 GHz while having 1.4 kHz of minimum frequency step, which corresponds to 0.8 aF of unit capacitance.

A 5-GHz low-voltage and low-power CMOS LC voltage controlled oscillator for 802.11a wireless LAN applications

In this paper, a low phase noise and low power 5.15 GHz LC-tank VCO is presented and analysed. The phase noise achieved is −91, −116 and −126 dBc/Hz at 100 KHz, 1 MHz and 3 MHz offsets respectively from the carrier frequency of 5.15 GHz, with 1.8 V power supply voltage and giving a very low power consumption of about 2.5 mW by considering the proposed oscillator topology, which consumes less power than the classical oscillator using the traditional differential transconductor pair. A broad tuning range has been achieved by means of standard mode PMOS varactors. The tunability of the designed VCO covers 530 MHz, from 4.78 GHz up to 5.31 GHz. Predicted performance has been verified by analyses and simulations using ELDO-RF tool with 0.35 µm CMOS TSMC parameters.

Fully integrated 10 GHz CMOS VCO

A differential voltage-controlled oscillator has been designed to operate in the 10 GHz band using a 0.25 µm CMOS process and low Q integrated inductors. The low gain and low Q problems of the components are overcome by the deployment of the cascode configuration with negative conductance generation to enhance the loop gain and Q value. PMOS varactors are used for varying the oscillating frequency from 9.7 to 11.4 GHz. The phase noise at 400 kHz offset is from –101 dB/Hz at the low frequency end to –87 dB/Hz at the high frequency end.

A low-phase-noise reference oscillator with integrated pMOS varactors for digital satellite receivers

A low-phase-noise LC reference oscillator (RO) for use in digital satellite receivers is described. This RO is an essential building block of a double-loop wide-band tuning system that reduces the phase noise of integrated quadrature voltage-controlled oscillators (VCOs) required for zero-IF receivers. In order to achieve a high degree of integration the RO is implemented using integrated varactors. Three varactor options which are available in a standard 11-GHz f/sub t/ bipolar technology are investigated: the p-n junction of an NPN, an active varactor circuit, and a pMOS varactor. Experimental results show that the integrated pMOS varactor combined with external inductors is the preferred choice to implement the resonator of the low-phase-noise RO. The achieved tuning range is 225-310 MHz. Carrier-to-noise levels of more than 87 dBc/Hz at 10-kHz offset are measured. The performance is realized with a RO dissipation of 14 mW at a supply voltage of 3.5 V.