PMOS Access Transistor Research Articles

A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations

To efficiently implement searching and logic functions with the SRAM-based in-memory computing (IMC), we need to perform computations on bitlines (BLs) (called compute access) via multiple wordline (WL) activations. However, this may cause prominent read disturbance when the IMC is implemented with the standard 6 T SRAM. To address this reliability issue, existing solutions adopt either auxiliary assistance circuits or alternative bitcell topologies, but they lead to substantial overheads of the access speed or array density. In this article, we propose a novel 8T compute SRAM (CSRAM) for reliable and high-speed in-memory searching and compound logic-in-memory computations. Our 8T CSRAM features a pair of pMOS access transistors and split-WLs dedicated to the compute access. A thorough circuit-level analysis reveals that the pMOS-based compute access port is essential for significantly mitigating the read disturbance. Moreover, we propose an elevated precharge voltage scheme and a low-skewed inverter-based sensing amplifier to improve the sensing speed. We have validated the proposed 8T CSRAM design in a 16 Kb array with a 28-nm CMOS technology. Compared to the state-of-the-art 8 T CSRAM, results show that our design is not only reliable but also 3.1 times faster, with a maximum operating frequency upping to 2.44 GHz.

Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing

In this paper, we propose two independent gate (IG) FinFET SRAM cells that use PMOS access transistors and back-gate (BG) biasing to achieve a high-stability performance. In the first cell, the back-gate of the access transistors is connected to the adjacent storage nodes, and the back-gate of the pull-down transistors is dynamically biased. Simulations indicate that the first proposed cell offers higher read static noise-margin (SNM), higher write-ability, least static/dynamic power, and a comparable read current compared to the previous IG-6TSRAMs. The second cell is a novel independently-controlled-gate FinFET SRAM cell, which provides a high read stability, the highest write-ability, low static power dissipation and high read current compared to the previously reported independently-controlled-gate FinFET SchmitTrigger based SRAM cells. This cell supportsbit-interleaving property at VDD = 0.4 V with high read/write yields.

Low power FinFET content addressable memory design for 5G communication networks

Content Addressable Memories (CAMs) are used in diverse applications, such as network protocols used in Wireless Sensor Networks (WSN), text analytics, reconfigurable computing and signal processing applications that require ultra-high speed and very low power consumption. In this work, a novel FinFET CAM using PMOS access transistors, based on PTM–MG transistor models in 22 nm and 14 nm technology is analyzed. Simulation results show that the Independent Gate (IG) FinFET CAM using PMOS access transistor exhibits a 38% improvement in the speed and 48% power consumption reduction compared to the shorted gate (SG) CAM based on 22 nm technology. Similarly, the proposed IG cell achieves a 5% improvement in speed and 50% reduction in power consumption when 14 nm technology is adopted. Hence the proposed IG cell in 14 nm has 6% improvement in speed and 59% less power consumption over 22 nm technology which is suitable for modern 5th generation communication networks.

A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology

This paper presents a six-transistor bitcell SRAM with pMOS access transistor. Utilizing pMOS access transistor results in lower zero-level degradation (ZLD) and, hence, higher read stability. In addition, the access transistor connected to the internal node holding $V_{\text {DD}}$ acts as a stabilizer and counter balances the effect of ZLD. In order to improve the writability, wordline (WL) boosting is exploited. WL boosting also helps to compensate the lower speed of the pMOS access transistor compared with nMOS transistor. To verify our design, a 2-kb SRAM is fabricated in the TSMC 65-nm CMOS technology. Measurement results show that the maximum operational frequency of the test chip is at 3.34 MHz at 290 mV. The minimum energy consumption is measured as 1.1 fJ/bit at 400 mV.

RNM Calculation of 6T SRAM Cell in 32nm Process Node based on Current and Voltage Information

Objectives: This work aims to analyze the the dependency of VDD, T and CR (Cell Ratio) on cell stability in terms of Read Noise Margin (RNM) in 32nm technology by the N- curve and butterfly graphical methods. The advantages of considering both voltage and current information for SRAM cell stability measurement have been reported. Methods/Statistical Analysis: The cell stability calculation of SRAM is a central concern in submicron CMOS process nodes, as they reason for increase in dies variability and voltage scaling. The cell Stability of the SRAM is typically calculated by Static Noise Margin (SNM). As it varies with different operating modes of a cell, a detailed analysis is required. In this article, the RNM of SRAM cell is computed by N curve, which compares with the SNM by bufferfly method. SRAM with PMOS access transistor for improved read stability and low voltage application is also presented. Findings: Results show that proposed SRAM gives 50% cell stability in read mode of operation over conventional SRAM cell for CR=3. Application/Improvements: The typical SRAM bit cell with PMOS access transistor shows improved read stability at low voltage application than standard SRAM cell.

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

SummaryIn this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1 V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1 V down to 0.5 V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. Copyright © 2015 John Wiley & Sons, Ltd.

A highly reliable NBTI Resilient 6T SRAM cell

In this work, a highly reliable six-transistor (6T) Static Random Access Memory (SRAM) cell is proposed. The proposed SRAM cell is resilient to Negative Bias Temperature Instability (NBTI), since, PMOS pull-up transistors are replaced by their counterpart NMOS pull-up transistors. We compared the different parameters and performance indices (static noise margin and energy per operation) of the proposed SRAM cell with the standard 6T and loadless 4T SRAM cells. In order to achieve full logic level in the proposed SRAM cell, we studied the effect of PMOS as access transistors and compared with the loadless 4T SRAM cells with and without NBTI effect. It is observed that the proposed PMOS access transistors based SRAM cell yield better reliability (120% improvement in read SNM) with marginal increase in energy per operation as compared to NMOS access transistors. The leakage current of the proposed SRAM cell is 57× less than the 4T SRAM cell. The proposed SRAM cell design has positive impact of NBTI stress and yields significant improvement in the SRAM cell reliability as compared to its counterpart standard 6T SRAM cell.

Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density and Reduced Leakage Power

A new six transistor (6T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stabilityand the integration densityof FinFET memorycircuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced byutilizing PMOS access transistors. The read stabilityis enhanced byup to 62% while reducing the leakage power byup to 22% as compared to a standard tied-gate FinFET SRAM cell with the same size transistors. One gate of each pull-up FinFET of the cross-coupled inverters is permanentlydisabled in order to achieve write-abilitywith minimum sized transistors. The proposed independent-gate FinFET SRAM circuit with P-type data access transistors reduces the idle mode leakage power, the write power, and the cell area byup to 62%, 16.5%, and 25.53%, respectively , as compared to a standard tied-gate FinFET SRAM cell sized for similar data stabilityin a 32 nm FinFET technology .

High performance ferroelectric memory with grounded-plate PMOS-gate cell technology

A new FRAM architecture utilising a grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: a V/sub DD/-precharged bit-line, a negative-voltage word-line technique and negative-pulse restoration. Because this configuration does not need the plate control circuitry, it greatly increases the memory cell efficiency. In addition, unlike other reported common-plate cells, this scheme can supply a sufficient voltage of V/sub DD/ to the ferroelectric capacitor while detecting and storing the polarisation on the cell. Thus, there is no restriction on low-voltage operation. Furthermore, by employing a compact column-path circuitry which only activates the required 8-bit data, this architecture minimises the current consumption of the memory array. A 2.5-V, 2-Mbit prototype chip has been developed with 0.5-/spl mu/m CMOS technology, and the possibility of the realisation of GPPG cell architecture has been confirmed.

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 /spl mu/m BiCMOS technology.

A high-density MOS static RAM cell using the lambda bipolar transistor

Abstnrcr–Based upon the common-collector lambda bipolar transistor (LBT), which is built with p-well NMOS, and the Parasitic w-n BJT in a CMOS IC, a novel MOS static RAM eelf catled the LBT celf is proposed. In this new cell, the LBT and two poly-Si resistors form a bktable element with a PMOS access transistor. With the minimum feature size F, the optimal cell area of 32 F2 can be reaJized by using the silicide contact and smnlf p-weff spacing. The REAWWRITE operation is simulated. Due to the need of precharging before reading and the rather slow recovery after reading, suitable peripheral circuits should be designed. (a) Compared with dynamic MOS RAM, static MOS random access memory (RAM) has the advantages of simple operation with no refreshing required. However, the static RAM suffers from low packing density which is caused by the complex cell circuitry. This problem becomes more severe as the memory bit capacity increases. Two methods are applied to solve the problem. One is the use of advanced fabrication technologies to reduce the chip area. The other is the use of new devices or circuits for the cell. The latter method is effective since the total cell area usually occupies 60-70 percent of the total memory chip area. Therefore the efforts of searching for a new cell which has high packing density and good speed-power performance have been increased recently [1] -[ 6]. This correspondence describes a new MOS static RAM cell which is constructed by using a negative resistance device called the lambda bipolar transistor (LBT) [71, [81. The proposed new cell, which is called the LBT cell, consists of one PMOS access transistor and one bistable storage element. The storage element is designed by using two poly-Si resistors and one common-collector type n-p-n lambda bipolar transistor, which consists of an NMOS merged with an n-p-n bipolar junction transistor (BJT). Since the PMOS, NMOS, and n-p-n BJT are compactly merged, the LBT cell has the highest packing density among all MOS static RAM cells. Moreover, it gives a good balance between process complexity, operation complexity, and performance. The proposed new static RAM cell circuit is shown in Fig. 1(a) where the BJT Q2 and the NMOSFET Ml form a lambda bipolar transistor [7] -[8 ] as marked by the dashed line, The collector of the LBT is connected to VDD, while the base and the emitter are connected to VDD and ground through poly-Si resistors R 1 and Rz, respectively. This common-collector type of LBT, together with K I and K2, serves as a bistable storage element which is accessed through the PMOSFET lf3. The typical integrated structure of the LBT cell is shown in Fig. 1(b). It may be seen that the p-well in lkfl also serves as the base of Q2 and the source of the lf3. The bistable characteristics of the storage element in the cell can be understood by superimposing the current-voltage