Plug Technology Research Articles

Study of the step coverage and contact resistance by using two-step TiN barrier and evolve simulation

Device aspect ratios and dimensions at the contact and via levels for old and new technologies are driving PVD/WCVD-based metallization to its full limit at integrated circuits (ICs) fabrication sites (Wilson et al., 1993). Contact and via This work describes the work performed at ST Microelectronics regarding the TiN barrier film properties with respect to process variables. Single-step and dual-step TiN barrier processes were studied for contact and via step coverage profiles used for aluminum and tungsten plug technologies. Electrical contact resistance values were evaluated using single and dual step TiN barrier processes. EVOLVE, a topography simulation program was used to study the step coverages and deposited film profiles for single and dual steps TiN barrier processes. In this work we prove that dual step TiN barrier process is superior to single step TiN barrier process in terms of step coverage, current leakage, film stress and contact resistance values.

ＪＯＧＭＥＣによる金属鉱物資源の探査・環境事業と技術開発 坑廃水処理コストの分析と鉱害防止技術開発

In this study, operating costs of mine drainage treatment plant in Japan were analyzed by using the Japan Oil, Gas and Metals National Corporation (JOGMEC) database, and the effectiveness of the technologies developed by MMAJ/JOGMEC was evaluated.Mine drainage treatment cost analysis showed that,-the unit operating cost (yen/m3) of the plants on ferrous mine drainage correlates with both the volume of treatment water (m3/min.) and the acidity (CaCO3 mg/L).-it is possible to make trial calculation on the change of annual treatment cost depending on the change of treatment water volume and the change of acidity.The technologies developed, so far, by the former Metal Mining Agency of Japan (MMAJ) and the JOGMEC were evaluated in view of effectiveness. The results showed that the vegetation technology, tunnel plugging technology, sludge backfill technology, and sludge densification technology were most effective.This study provided a basic data set to consider more effective ways on mine drainage control and treatment, but still the data to be improved. It is recommended that more detailed mine drainage data and analysis is required to improve technologies to prevent and treat the mining related pollution.

Integration technology for ferroelectric memory devices

Ferroelectric devices have been developed for future memory devices due to their ideal memory properties such as non-volatility, fast access time, and low power consumption. Several integration issues for commercial ferroelectric devices have been overcome or are being resolved by novel process technology and design technology. The process technology is combined with ferroelectric material technology, electrode technology, etching technology, hydrogen barrier technology, barrier and plug technology, and backend technology. The advanced process technologies are enhanced by developing its own design technology. In recent few years, low density ferroelectric random access memory (FRAM) products start to gradually but progressively penetrate into memory and smart card market, and the ferroelectric devices are developed to 32 Mb FRAM with 0.25 μm design rule and triple metallization. In this paper, it is reviewed how to integrate the ferroelectric devices for producing commercial products.

Evaluation of Contact and Via Step Coverage Using a Novel Two-Step Titanium Nitride Barrier Deposition Process

AbstractAluminum plug technologies are still used for many different semiconductor device applications and are cost-effective processes. However, there are some disadvantages associated with them. The key disadvantage is aluminum junction spiking caused by aluminum diffusing down into the silicon substrate and silicon diffusing up into the aluminum plug due to a poor titanium nitride (TiN) barrier [1]. The tungsten plug process is primarily used for 0.5mm and smaller technologies. Titanium nitride barrier material plays an important role as an underlayer for tungsten plugs to prevent tungsten hexafluoride (WF6) from attacking the titanium (Ti) film [2]. The role of the TiN barrier is to retard or prevent diffusion of the materials that the TiN layer separates [3]. In this work, the authors investigated the TiN barrier film properties with respect to nitrogen flows at two different power set points and argon gas flows. Different experiments were performed to understand the properties of the TiN film with respect to process variables. Single-step and dual-step TiN barrier processes were studied for contact and via step coverage profiles used for aluminum and tungsten plug technologies.

Home networking with Universal Plug and Play

We present an overview of the Universal Plug and Play (UPnP/sup TM/) technology and the UPnP Forum, the multicompany organization that develops parts of the architecture. A technical description of the technology is presented, followed by three illustrative usage cases where it could be applied in home networking environments. Finally, the authors describe the benefits UPnP technology can provide in home networking and discuss potential future work in this area.

The origin and elimination of random single-bit failure in high density 1t1c fram

The COB (capacitor-over-bit line) structure is essential for integrating high density FRAM (ferroelectric random access memory) device. It is very difficult in the COB cell structure to maintain low contact resistance between plug material and bottom electrode during the integration processes. We have used CoSix/poly-Si and Pt/IrO2/Ir as plug materials and bottom electrode stack, respectively. However, random single-bit failure was observed due to the high contact resistance, which was caused by the formation of amorphous oxide layer, especially, during high temperature anneal for PZT (Pb[Tix,Zr1-x]O3) crystallization. It was observed that silicon atoms diffuse even into Ir oxygen barrier, thus leading to the oxide formation between the plug and Ir oxygen barrier. The approach we have taken to prevent contact resistance failure is to optimize the plug material that has high endurance against oxidation reaction. In this study, we developed tungsten plug technology to eliminate the random single-bit failure. It is expected that this tungsten plug technology can provide highly reliable COB structure for 32Mb FRAM device and beyond.

Sub-half micron metallization using high-pressure Al: Invited lecture

The continuing drive towards smaller feature sizes increases the demand on multi-level metallization. The industry is looking for higher operating speeds, reduced RC delay and increased reliability. Besides meeting the technology goals the metallization process must be cost effective. Aluminium (Al) plug technology has clear advantages over W-Plug. These include lower resistance vias, fewer overall process steps and better electromigration performance. Conventional Al reflow processes have not gained wide acceptance at or beyond 0.35 μm technology due to their sensitivities to surface conditions and hole profile. High-pressure Al filling (Forcefill®), developed by Electrotech, is now becoming the preferred technique for the filling of high aspect ratio structures.

Integrated plasma-promoted chemical vapor deposition route to aluminum interconnect and plug technologies for emerging computer chip metallization

A low temperature plasma-promoted chemical vapor deposition (CVD) process was developed for the formation of reliable aluminum interconnect and plug metallization schemes for applications in and beyond 0.25 μm integrated chip device technology. The process employs aluminum source precursors that are based on amine adducts of alane, such as dimethylethylamine alane, where the lack of a direct aluminum–carbon bond provides a clean chemical pathway by which to eliminate the precursor’s hydrocarbon groups at relatively low temperatures and yield pure aluminum films. The formation of dense and thick aluminum films at low temperature and that have a smooth surface morphology is achieved by combining a radio-frequency hydrogen plasma at low power densities (below 0.1 W/cm2) with a low frequency (<400 kHz) substrate bias. The use of a low power density plasma is designed to activate a uniform nucleation of aluminum grains, thus eliminating the inherent problem of surface roughness that plagues thermal CVD processing, while avoiding undesirable precursor gas phase decomposition and film contamination. Additionally, the application of a substrate bias enhances the impingement rate of precursor species on the substrate, and lead to an increase in the re-emission probability of such species inside via and trench structures, leading to conformal step coverage and complete fill. The aluminum interconnect and plug structures produced were specular to thicknesses above 1 μm, exhibited contamination levels below the 1 at. % detection limit of x-ray photoelectron spectroscopy and Auger electron spectroscopy, and displayed postanneal resistivity of 3.38 μΩ cm. Conformal fill of 0.25 μm structures was achieved at growth rates in excess of 1000 Å/min.

Barrier Properties of Titanium Nitride Films Grown by Low Temperature Chemical Vapor Deposition from Titanium Tetraiodide

Results are presented from a systematic study of the composition, texture, and electrical properties of titanium nitride (TiN) films and their performance as diffusion barrier in multilevel interconnect schemes of ultralarge scale integration (ULSI) computer chip device structures. The films were grown by low temperature (<450°C) inorganic chemical vapor deposition using titanium tetraiodide as source precursor and ammonia and hydrogen as co‐reactants. The TiN films were nitrogen‐rich., with iodine concentrations below 2 atom percent, displayed resistivities in the range 100 to 150 μΩ cm depending on thickness, and exhibited excellent step coverage with better than 90% conformality in both nominal 0.45 μm, 3:1 aspect ratio and 0.25 μm, 4:1 aspect ratio contact structures. A comparison of the properties of chemical vapor deposited (CVD) TiN with equivalent physical vapor deposited (PVD) TiN showed that reactivity with Al‐0.5 a/o Cu alloys was equivalent in both cases. In particular, a 10% increase in the Al‐Cu/TiN stack sheet resistance was observed for both types of TiN after a 450°C, 30 min sinter. Similarly, the characteristics of CVD tungsten and reflow plug fills were identical on both types of TiN films. However, barrier performance for CVD TiN in aluminum and tungsten plug technologies was superior to that of PVD TiN, as evidenced by lower contact diode leakage for CVD TiN in comparison with PVD TiN films of equal thickness. This improved barrier performance could be attributed to a combination of factors, which include the nitrogen‐rich composition, higher density, and enhanced conformality of the CVD TiN phase in comparison with the PVD TiN. In view of the superior step coverage and diffusion barrier characteristics, the low temperature inorganic CVD route to TiN seems to provide an adequate replacement for conventional PVD TiN in emerging ULSI metallization interconnect schemes.

Optimization of PVD Ti/CVD TiN Liner for 0.35 μm Tungsten Plug Technology

AbstractA novel plasma enhanced CVD TiN process was integrated with high density plasma sputter etch preclean (PCII) and 1:1.5 collimated PVD Ti (c-PVD Ti) process to deposit a Ti/TiN liner for tungsten contact and via plugs. The integrated liner process was optimized for a 0.35 μm nonsalicide CMOS device application. RF power and sputter depth used for contact preclean were the major process variants affecting the contact resistance, junction leakage and transistor threshold voltage. Low contact resistance was obtained for a c-PVD Ti thickness of ∼375 Å. Via resistance was significantly lower with c-PVD Ti/CVD TiN liner as compared to only a TiN liner. Contact resistance for c-PVD Ti/c-PVD TiN and c-PVD Ti/CVD TiN liners were comparable while contacts with conventional PVD Ti/TiN liner showed significantly higher values due to poor step coverage. Low junction leakage current was obtained for integrated c- PVD Ti/CVD TiN stack.

Post Metallization Damage Recovery Using Rapid Thermal Processing (RTP)

AbstractFurnace annealing after plasma processing and other process steps such as implantation and contact formation in advanced CMOS processing are extensively used to improve the overall device characteristics. With an ever emerging trend towards lower thermal budget processing and the unique capabilities of RTP to provide that along with flexibility to change process ambients, we present the results of our experiments to do low temperature mixed gas and pure hydrogen anneals in RTP and study its effects on junction leakage and transistor characteristics.Recently, with the advent of the contact plug technology, the sintering function is not as important as the alloy effect on the transistor and junction device parameters. Therefore, the requirements for the alloy are more related to threshold voltage, (Vt) uniformity and reduced junction leakage. The key is that the hydrogen atoms diffuse far into the silicon to reach the dangling bonds at the field edge and by the transistors. The hydrogen rapid thermal processor (HRTP) can accomplish the basic device annealing function as long as there is sufficient time for hydrogen diffusion and reaction time. The aluminum metallization limits the temperature to 500°C due to increased metal roughness and increased metal resistance. Also, the hotter temperatures compete in the reaction by breaking hydrogen bonds as well as satisfying the dangling silicon bonds. The best ambient gas was at 100% hydrogen flow at low pressure with HRTP times in excess of one minute.

The Effect of Post W-Etchback Cleaning Treatments and Implementation of Refractory Metal Buffer Layers on the Electromigration Performance of TiN/AlCu/TiN/Ti Metallization Systems

AbstractTiN/Ti films employed as glue layers for a blanket/etchback W plug technology show a significant surface contamination after the W-etchback process. An Al film deposited directly on a contaminated TiN/Ti underlayer exhibits a very weak texture, increasing the susceptibility to electromigration. Reliability tests confirm that the electromigration performance of a TiN/AlCu/TiN/Ti metallization system with a W plug technology, is significantly inferior to interconnecs that do not employ this plug technology. To improve the electromigration performance of this metallization system, several TiN surface cleaning treatments were evaluated. Also, the impact of the implementation of refractory metal buffer layers, before Al deposition was investigated. Analysis was performed by means of several surface analysis techniques, Al texture measurements and wafer-level reliability tests. It has been demonstrated that the contamination needs to be removed completely, or to be covered by a refractory buffer layer in order to restore the Al texture and to recover the proper electromigration resistance.

Conventional contact interconnect technology as an alternative to contact plug (W) technology for 0.85 μm CMOS EPROM IC devices

The conventional (plug-less) and tungsten (W) plug contact interconnect technologies were studied for the fabrication of 0.85 /spl mu/m CMOS EPROM integrated circuit devices. 4 Mbit EPROM devices and appropriate test structures were fabricated using these two interconnect architectures and were evaluated for process simplicity, associated problems/solutions, contact electrical characteristics, and circuit yield and speed. The most important process issue for the conventional contact technology was the overlay accuracy of the stepper used for printing the contacts. It was found that a misalignment of <0.3 /spl mu/m was essential if contacts were to be reflowed after the contact etch process in a way that: a) did not violate the geometrical design rules, and b) did not result in bulging of the contacts, or an increase in the contact profile angle which would degrade metal step coverage. Electrical characteristics of the contacts were studied through contact resistance, specific contact resistivity, contact failure rate, and junction leakage measurements for both contact interconnect architectures. The data presented indicated that both processes produced contacts with similar characteristics. Finally, the results of this work indicated that the conventional contact interconnect technology could be reliably used for fabrication of 0.85 /spl mu/m CMOS EPROM devices. This process was simpler, less expensive, and as structurally reliable as the W contact plug technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effect of TiW As Adhesion Layer And Underlying Metal On Electromigration Characteristics of Tungsten Via Plugs

AbstractThe use of Tungsten plug technology to obtain good step coverage in vias and contacts is a well know fact. The effect of TiW as an adhesion layer between the plug and the overlying Aluminum is shown in this paper to have a significant impact on the electromigration characteristics of this scheme. A comparison between plug and non-plug technology is also made keeping the aspect ratios the same. Also discussed in this paper will be the effect of the first metal (Tungsten vs Aluminum) on electromigration characteristics. Constant current DC electromigration stressing was performed on via chains and the results are discussed. Discussed, also, are SEM cross sections (XSEM) of the stressed vias indicating the failure modes. An idealized metal scheme will be presented and discussed.

Antireflection coatings for advanced semiconductor device metallization using laser reflow and chemical mechanical planarization

We have investigated titanium tungsten (TiW), titanium nitride (TiN), and chemical vapor deposited (CVD) tungsten (W) films as antireflection coatings (ARC) on aluminum (Al) alloy films to widen the laser planarization process window for contact via filling. ARCs lowered the minimum laser fluence required to accomplish complete contact filling and the maximum laser fluence before the onset of optical ablation, resulting in a significant increase in the process window. This increase closely correlated with the optical and thermal properties of the ARCs. The observed increase in resistivity of laser processed Al films due to intermixing with the ARCs does not preclude its use as via stud metal. A newly developed Al plug technology utilizing chemical mechanical polishing to remove the laser processed film from the surface is presented.

UTILIZATION OF PLUGS IN PRAIRIE RESTORATION

The preservation/restoration of prairie ecosystems is part of our responsibility as stewards of the earth. Success in reestablishing prairie plant communities has been quite variable and far from optimum. This cooperative project between the University of Wisconsin-River Falls (UWRF) and Carpenter Nature Center examine the use of horticulture plug technology as a means of improving the quality, availability, production efficiency and transplant survivability of herbaceous frob prairie species for use in prairie restoration efforts.Data on growth rates and winter survival of bare-root seedlings and plug seedlings of Rudbeckia hirta, Ratibida pinnata and Zizea aurea in prairie test plots will be presented. The plug seedlings were stockier plants, had well developed root systems, and demonstrated excellent performance as transplants in prairie restoration efforts.

Tungsten plug technology using substitution of W for Si

Novel W plug technology that is compatible with a conventional poly Si filling has been developed. In this technology, low-pressure chemical vapor deposition (LPCVD) poly Si is embedded in contacts and vias using etchback, and tungsten (W) is substituted for poly Si using Si reduction of WF/sub 6/. This plug technology has been successfully applied to a 0.6- mu m contact and a via filling. The specific contact resistivity was 2*10/sup -7/ and 4*10/sup -7/ Omega -cm/sup 2/ for n/sup +/ and p/sup +/ contacts, respectively. For vias on W and WSi/sub 2/ polycide interconnections, the contact resistivity is found to be less than 1*10/sup -8/ Omega -cm/sup 2/. The amount of W substituted for Si by this reaction is determined by several process parameters: thin oxides on Si surfaces, deposition temperature, and partial pressure of WF/sub 6/. W films that are more than 1.5- mu m thick can be substituted for Si in this technology. >

Implementation of tungsten metallization in multilevel interconnection technologies

The techniques of experimental design and response-surface methodology have been used to produce empirical models of the deposition and etchback of tungsten in commercially available reactors for a tungsten plug technology. Deposition was carried out in a Genus 8402 LPCVD (low-pressure chemical vapor deposition) batch reactor by the H/sub 2/ reduction of WF/sub 6/. Response-surfaces for deposition rate, sheet resistance uniformity, resistivity, and film stress were developed as a function of reactor pressure, reactor temperature, and flow rate of WF/sub 6/ at a fixed H/sub 2/ flow rate using linear-interactive models. A thin layer of TiN was used to ensure adhesion of tungsten to SiO/sub 2/. Etchback of the composite layer of W/TiN to form via plugs was performed in a Tegal 804 single-wafer system with a two-step process using mixtures of SF/sub 6/ with C/sub 2/F/sub 6/ and He with Cl/sub 2/ in step 1 and step 2, respectively. Process parameters for both steps were obtained from quadratic models of etch rate and etch uniformity.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>