PLL Loop Research Articles

Induction Generator with Direct Control and a Limited Number of Measurements on the Side of the Converter Connected to the Power Grid

The article presents an induction generator connected to the power grid using the AC/DC/AC converter and LCL coupling filter. Three-level inverters were used in the converter, both from the generator side and the power grid side. The algorithm realizing Pulse Width Modulation (PWM) in inverters has been simplified to the maximum. Control of the induction generator was based on the Direct Field-Oriented Control (DFOC) method. At the same time, voltage control has been used for this solution. The MPPT algorithm has been extended to include the variable pitch range of wind turbine blades. The active voltage balancing circuit has been used in the inverter DC voltage circuit. In the control system of the grid converter with an LCL filter, the number of measurements was limited to the measurement of power grid currents and voltages. Synchronization of control from the power grid side is ensured by the use of a PLL loop with the system of preliminary suppression of undesired harmonics.

Reduced-Order Generalized Integrator-Based Phase-Locked Loop: Performance Improvement for Grid Synchronization of Single-Phase Inverters

Generalized integrator-based orthogonal signal generator phase-locked loops (GI-OSG PLLs) are very popular in single-phase grid synchronization. Generally speaking, the OSG of this PLL is realized from a second-order integrator perspective. As a result, the OSG implementation impacts the PLL dynamics. Improving the PLL performance by employing a reduced-order OSG implementation is the main motivation for this paper. Therefore, a reduced order-OSG PLL is proposed. In the proposed PLL, a single state and two output equations are employed to obtain a pair of orthogonal signals. This results in the loss of orthogonality between the OSG outputs and the single-phase supply voltage. Also, harmonic filtering capability provided by SOGI-OSG becomes non-existent. These issues are resolved by incorporating steady-state phase angle-offset error compensation at the PLL output and a moving average filter (MAF) within the PLL loop. To counteract the influence of MAF on the PLL’s stability and dynamics performance, a phase-lead compensator is designed. Through experimental studies, it is shown that the proposed reduced order-OSG PLL offers excellent dynamic performance. Also, the proposed PLL achieves minimal fluctuation of PV power when employed for grid synchronization of a PV system.

A NEW APPROACH TO CREATING A HIGHLY STABLE RANGE MICROWAVE GENERATOR

A range microwave generator is considered. A frequency multiplier is installed in the PLL loop of the generator. There is no frequency divider in the generator. It has increased stability due to low output phase noise. The proposed device can be used in telecommunications and radio equipment. The microwave generator consists of an autogenerator, three multipliers, a bandpass filter, two low-pass filters, a reference frequency unit, a harmonic generator, and a control unit. Auxiliary units of the generator are two adders, a key and two controllers. The first multiplier together with the bandpass filter works as a stroboscopic transducer, the second – as a quadrator, the third with a low-pass filter – as a phase detector. The inputs of the stroboscopic converter receive two voltages from the harmonic generator. The frequencies of the first voltage harmonics are close. Voltages have the form of short pulses and are enriched with harmonics. After the signal at the output of the first low-pass filter, the first controller opens the key, switches the reference frequency node and through the second controller closes the PLL loop. The control unit sets the reference frequencies and changes the frequency of the autogenerator. The main nodes of the PLL loop are the third multiplier with the second low-pass filter. Auto-tuning of the generator begins with the appearance of the control signal from the quadrator. The signal appears after the strobe conversion frequency at the output of the bandpass filter coincides with the center frequency. The frequency instability of the range generator decreases. It is approaching the instability of the reference frequency. The stability of the reference frequencies determines the relative frequency error of the range of the microwave generator. The maximum frequency depends on the parameters and dynamic properties of the autogenerator, stroboscopic transducer and harmonic generator. A high-quality harmonic generator will provide a low level of phase noise. The structural scheme of the microwave generator is offered and its work is explained. The analysis of the mathematical model of the microwave generator is performed. The formulas of interrelation of voltages of knots with initial oscillation of the generator are received. Computer simulations have confirmed that the output frequency can be stabilized in the generator.

ALGORITHM OF RANDOM START PHASE CORRECTION AND FREQUENCY OFFSET IN THE COMMUNICATION SYSTEM WITH THE QUADRATURE MODULATION

The goal of the work is to find a solution, realization, and modelling of the algorithm for the compensation of a start random phase error of a quadrature signal, which began at the input of the receiver’s digital part. This algorithm also solves the problem of carrier frequency error offset. These errors have enough values for the lock-band of Costas PLL using minimum hardware resources. To complete this task, the realization and modelling algorithm problems of phase and frequency offset error corrections in Matlab Simulink IDE, arising from Costas PLL, were solved. This algorithm sets values errors for Costas PLL work stability. From the results of calculation and modelling obtained in the article, it follows that the developed model of the receiving path completely eliminates the probability of the error of a random initial phase and frequency offset in the receiver model of a QPSK signal, before the PLL loop is switched on, which significantly reduces the time of readiness for operation of this model.

A 24 GHz FMCW/Doppler Dual-Mode Frequency Synthesizer With 68.8 kHz RMS FM Error and 1.25 GHz Chirp Bandwidth

This brief presents a 24 GHz dual-mode frequency synthesizer designed in a 55-nm CMOS technology supporting both Doppler and frequency modulated continuous wave (FMCW) radars. The effects of chirp linearity and delta-sigma modulation (DSM) resolution on the rms FM error is analyzed. A design procedure for the PLL loop bandwidth and time interval of the frequency step to reduce the rms FM error is proposed. A voltage-controlled oscillator (VCO) featuring a four-coil transformer load is developed providing differential local oscillation (LO) signals for the transmitter (TX) and quadrature LO signals for the 2-channel receiver (RX). The prototype is designed with a loop bandwidth of 350 kHz, a frequency step time interval of <inline-formula> <tex-math notation="LaTeX">$2 ~\mu s$ </tex-math></inline-formula>, and a VCO tuning linearity of 26&#x0025;. In the FMCW mode, it achieved an rms FM error of 68.8 kHz over a 1.25 GHz chirp bandwidth. In the Doppler mode, the VCO operates in the free-running mode to save power consumption. An 8-bit digital-to-analog converter (DAC) is used to provide the VCO control voltage compensating process and voltage variations. The free-running VCO operates at a 24.125 GHz and has a frequency error of less than 1 MHz.

A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO

This brief presents an all-digital PLL (AD-PLL) for a DDR5 registering clock driver (RCD) with a self-biased supply-noise-compensation (SNC) technique. By combining two Nagata current sources that have opposite dependency on supply variations, it offers a constant current to a ring oscillator over a wide range of supply voltage. Thereby, the dynamic voltage droop due to variations in workload is compensated while a voltage margin for mass production is improved. Since the SNC technique operates independently of the PLL loop bandwidth without using feedback, the proposed AD-PLL is free from the stability problem associated with bandwidth overlapping. Quantitative analyses on static and dynamic characteristics of the proposed SNC technique and relevant design considerations are addressed. Fabricated in the 28-nm CMOS technology, the AD-PLL occupies an active area of 0.06 mm2 and consumes 12.1 mW at 3.0 GHz with a 1.1 V supply voltage. The power-supply-noise-attenuation (PSNA) is measured as 40 dB and the integrated rms jitter of 271 fs is observed.

Phase noise simulation of a hybrid frequency synthesizer based on a PLL loop without division of the VCO frequency

Phase noise simulation of a hybrid frequency synthesizer based on a PLL loop without division of the VCO frequency

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

Modeling PLL Loop with Nonlinearity

A model of a pulse phase-locked loop multiplying ring in a MicroCap11 medium is considered. The analysis uses a nonlinear model of a voltage-controlled oscillator with a user-defined control characteristic. An RS-trigger is used as a pulse-phase detector, a pulse counter in the negative feedback circuit is implemented on JK-triggers. Transient processes in the ring, as well as the spectrum of the output oscillations in the steady (stationary) mode are considered.

Prediction of Phase Noise and Spurs in a Nonlinear Fractional-${N}$ Frequency Synthesizer

Integer boundary spurs appear in the passband of the loop response of fractional- ${N}$ phase lock loops and are, therefore, a potentially significant component of the phase noise. In spite of measures guaranteeing spur-free modulator outputs, the interaction of the modulation noise from a divider controller with inevitable loop nonlinearities produces such spurs. This paper presents analytical predictions of the locations and amplitudes of the spurs and accompanying noise floor levels produced by interaction between a divider controller output and a PLL loop with a static nonlinearity. A key finding is that the spur locations and amplitudes can be estimated by using only the knowledge of the structure and pdf of the accumulated modulator noise and the nonlinearity. These predictions also offer new insights into why the spurs appear.

A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

A 2.5–5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs) require additional circuitry for resolving a phase alignment mismatch between the PLL loop and injection path, the presented ILPLL exhibits a simplified architecture owing to the proposed injection technique and sub-sampling bang-bang phase detector (SSBBPD). Because the proposed injection technique exploits dual-edge injection, we analyze the performance impact of dual-edge injection when inaccurate injection timing occurs. This paper also offers an analysis of the injection technique based on the charge transfer and derives the realignment factor of the injection. With the proposed injection technique and the direct connection of the digitally controlled oscillator (DCO) clock to the SSBBPD, the timing mismatch between the PLL loop and injection path becomes insensitive to voltage and temperature drift. The proposed ILPLL prototype is fabricated in a 65-nm CMOS process and achieves a 168-fs integrated rms jitter over 1 kHz to 40 MHz at a 5-GHz output frequency with 156.25-MHz reference clock while consuming 15.4 mW with an active area of 0.06 mm2.

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6–200 MHz) and output (0.15–5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high −3dB PLL bandwidth (>40% of $f_{\mathrm{ REF}}=19.2$ MHz), and the proposed reference current generator (IrefGen) provides accurate current with <4% tolerance without the need for external components or on-chip precision resistors. IrefGen decouples PLL loop dynamics from feedback divide ratio and provides immunity to systematic capacitor variation. Power gating of switched-cap loop filter’s bias circuits results in more than 10% PLL total power savings. The PLL achieves 1.6-ps integrated RMS jitter at 4 GHz using 100-MHz reference while consuming 2.6 mW from 0.95 V. The PLL performance satisfies the stringent PCIe Gen2/3 jitter specifications without resorting to inductors.

Impedance-Phased Dynamic Control Method for Grid-Connected Inverters in a Weak Grid

A power distribution grid exhibits the characteristics of a weak grid owing to the existence of scattered high-power distributed power-generation devices. The grid impedance affects the robust stability of grid-connected inverters, leading to harmonic resonance, or even instability in the system. Therefore, a study of the stability of grid-connected inverters with high grid impedance based on impedance analysis is presented in this paper. The output impedance modeling of an LCL -type single-phase grid-connected inverter is derived, where the effects of the PLL loop and the digital control delays on the output impedance characteristics have been taken into account. To enhance the stability of grid-connected inverters with different grid impedance, a novel impedance-phased compensation control strategy is proposed by increasing the phase margin of the grid-connected inverters. Specifically, a detailed implementation and parameter design of the impedance-phased compensation control method is depicted. Finally, an impedance-phased dynamic control scheme combined with online grid impedance measurement is introduced and also verified by the experiment results.

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO

This paper presents the first published fully-integrated digital fractional- N PLL based on a second-order frequency-to-digital converter (FDC) instead of a time-to-digital converter (TDC). The PLL's quantization noise is nearly identical to that of a conventional analog delta-sigma modulator based PLL (ΔΣ-PLL). Hence, the quantization noise is highpass shaped and is suppressed by the PLL's loop filter to the point where it is not a dominant contributor to the PLL's output phase noise. However, in contrast to a ΔΣ-PLL, the new PLL has an entirely digital loop filter and its analog components are relatively insensitive to non-ideal analog circuit behavior. Therefore, it offers the performance benefits of a ΔΣ-PLL and the area and scalability benefits of a TDC-based digital PLL. Additionally, the PLL's digitally controlled oscillator (DCO) incorporates a new switched-capacitor frequency control element that is insensitive to supply noise and parasitic coupling. The PLL is implemented in 65 nm CMOS technology, has an active area of 0.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , dissipates 21 mW from 1.0 and 1.2 V supplies, and its measured phase noise at 3.5 GHz is -123, -135, and -150 dBc/Hz at offsets of 1, 3, and 20 MHz, respectively. The PLL's power consumption is lower than previously published digital PLLs with comparable phase noise performance.

PETA4: a multi-channel TDC/ADC ASIC for SiPM readout

The PETA4 ASIC is the latest member of a family of chips targeted mainly at the readout of Silicon Photomultipliers in PET, with possible use in other detector applications. PETA4 houses 36 channels on a 5 × 5mm2 die and is fabricated in the UMC 180nm technology.It uses bump bonds with a convenient pitch of ≈ 270μm to allow the construction of very compact modules at moderate substrate cost. The chip requires nearly no external components by integrating everything (PLL loop filter, bandgap reference, bias DACs,…) on chip. Power consumption is ⩽ 40mW per channel, depending on digital speed and bias settings.Every channel has two independent frontends: an established differential amplifier which has shown to be insensitive to pickup in the target application of PET/MRI, and a single-ended frontend with very low input impedance (Zin ≈ 7Ω) for high channel count operation. A fast discriminator with tunable threshold and a noise of ⩽ 300μV self-triggers time stamping with a bin width of 50ps as well as an integratorwith programmable integration time. The amplitude signal is converted by a ≈ 9-bit SAR ADC. After conversion, events with sufficient amplitude arequeued for serial readout. The previous chip version PETA3 has achieved a CRT time resolution of ≈ 200ps when reading out scintillation lightfrom a 3 × 3×5mm3 LYSO crystal coupled at room temperature to a 3 × 3mm2 SiPM from FBK. Energy resolution for LYSO is ≈ 12.5%FWHM. LYSO crystals of 1.3mm size could be clearly identified with SiPMs of 4 × 4mm2 when using a light spreader.The architecture of PETA4 and its performance in the lab and with SiPMs will be presented.

Flying-Adder Fractional Divider Based Integer-N PLL: 2nd Generation FAPLL as On-Chip Frequency Generator for SoC

Flying-Adder direct period synthesis is a technology that directly constructs output clock period from a known base time unit Δ. In the past, it is mainly used for driving digital load. In this work, a new scheme is proposed to produce spectrally pure clock signal at certain frequencies which can be used to drive devices such as SoC on-chip ADC, DAC and etc. This scheme utilizes a Flying-Adder synthesizer as a fractional divider placed inside the PLL loop. Additionally, a PDFR technique is used to help improve the frequency resolution. Moreover, a unique accumulator is used to boost circuit speed. A 55 nm implementation is fabricated and is used to validate the architecture of this 2nd generation Flying-Adder PLL. The resolution of this enhanced integer-N PLL is 1.5 MHz across the entire VCO operating range with a 12 MHz input and loop bandwidth of 1 MHz. The power consumed is 8.3 mW at 2.3 GHz and the area is 0.16 mm2 . The significance of this fractional divider is discussed at the end. A brief comparison between this clock generator and others is given at the end as well.

Design and Research of Improved Digital Phase-Locked Loop Based on FPGA

In order to improve anti-jamming performance of the sensor, fast lock digital PLL is proposed and the PLL is used in the sensor. Digital PLL with a simple structure, flexible control, high tracking accuracy, loop performance and easy integration of features; while PLL loop automatic variable in the model control technology to speed up the rate locked loop to reduce Phase jitter. In this paper, the arithmetic average and moving average value of the software filter scheme to solve the sensor can filter out high frequency interference filter design problems and improve robustness.

Design and Research of Improved Digital Phase-Locked Loop Based on FPGA

In order to improve anti-jamming performance of the sensor, fast lock digital PLL is proposed and the PLL is used in the sensor. Digital PLL with a simple structure, flexible control, high tracking accuracy, loop performance and easy integration of features; while PLL loop automatic variable in the model control technology to speed up the rate locked loop to reduce Phase jitter. In this paper, the arithmetic average and moving average value of the software filter scheme to solve the sensor can filter out high frequency interference filter design problems and improve robustness.

Band-III T-DMB/DAB 모바일 TV용 저전력 CMOS RF 튜너 칩 설계

본 논문에서는 Band-III 지상파 디지털 멀티미디어 방송 수신용 저전력 CMOS RF 튜너 칩에 대해 기술한다. 제안된 RF 튜너 칩은 저전력의 소형 휴대단말기 개발에 적합한 Low-IF 수신 구조로 설계되었으며, 174~240 MHz의 RF 방송 신호를 수신하여 1.536 MHz 대역폭의 2.048 MHz IF 신호를 출력한다. RF 튜너 칩은 저잡음 증폭기, 이미지 신호 제거 믹스, 채널 필터, LC-VCO, PLL과 Band-gap 기준 전압 생성기 등의 모든 수신부 기능 블록들을 포함하고 있으며, 0.18 um RF CMOS 기술을 이용하여 단일 칩으로 제작되었다. 또한 전력 소모를 줄이기 위한 4단계 이득 가변이 가능한 저잡음 증폭기를 제안하였으며, Schmoock's 선형화 기법과 Current bleeding 회로 등을 이용하여 수신 성능을 개선하였다. 제작된 RF 튜너 칩의 이득 제어 범위는 -25~+88 dB, 잡음 특성(NF)은 Band-III 전체 대역에서 약 4.02~5.13 dB, 선형 특성(IIP3)은 약 +2.3 dBm 그리고 이미지 신호 제거비는 최대 63.4 dB로 측정되었다. 총 전력 소모는 1.8 V 단일 전원에서 약 54 mW로 우수하며, 칩 면적은 약 <TEX>$3.0{\times}2.5mm^2$</TEX>이다. This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is <TEX>$3.0{\times}2.5mm^2$</TEX>.

A 1 mhz bandwidth, 6 ghz 0.18 μm cmos type-i Δ Σ fractional-n synthesizer for wimax applications

A 6 GHz Type-I fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLL with noise-cancelling DAC and discrete-time sample and hold loop-filter is presented. The 1 MHz bandwidth PLL utilizes an inherently linear PFD and noise-cancelling charge-pump DAC circuit to reduce quantization noise by more than 25 dB. The worst case near-integer in-band spur is measured at -61 dBc and the integrated RMS phase error is - 42 dBc. The measured in-band phase noise at 300 kHz offset from the 6.12 GHz carrier is -102 dBc/Hz and out-of-band phase noise at 3 MHz offset is -130 dBc/Hz. The PLL loop settling time for an accuracy of 0.01 ppm and a frequency step of 60 MHz is less than 11 ¿ s. The synthesizer is fabricated in a 0.18 ¿m CMOS technology with 6 metal layers and consumes 26 mA from a 1.8 V power supply.