PLL Circuit Research Articles

Frequency Tuning of Bipolar Ring Oscillators using Complementary Inverters and Current Mirror Inverters

Complementary bipolar devices are extensively used in analog/digital VLSI circuits. Three inverters, namely, Complementary Inverters (CI), Complementary Current Mirror Inverters (CCMI) and Diode Loaded Complementary Inverters (DLCI) which appear to be attractive for realization of ring oscillators have been simulated. Ring oscillators have been made using different combinations of high gain CI and large bandwidth CCMI. Various techniques of frequency tuning of such oscillators have been studied and the results presented. A PLL circuit has been implemented using a current controlled ring oscillator.

A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2/sup 23/-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A complete single chip AM stereo/FM stereo radio IC

For the first time in the world, a complete single chip AM stereo/FM stereo radio IC which can be used for the portable radio has been developed. It has a PLL circuit for pilot detection that makes high quality AM stereo reception possible. >

A new method for clock distribution

A new alternative is described for the clock-distribution problem. The main feature of the new scheme is that a number of stations arbitrarily located on a single reference line independently derive a clock that is aligned to a common systemwide phase. The central principle is that the midtime between appearances of an isolated pulse traveling down and back on a reference line is the same, regardless of the point of observation. This principle is adapted for clock distribution by the periodic injection of a reference pulse onto a single conductor, reflection of this pulse at the end of the reference line, and generation of a local clock at all stations (such clock being phase-locked to the interval midtime by a special PLL circuit). The paper describes the method and gives a theoretical performance analysis and measured results from an experimental system. The experiments achieve a subnanosecond skew over 30 m on a coaxial cable that has an uncompensated delay of 147 ns. This method should be considered for applications from the millimeter scale on chip to the kilometer scale in radio astronomy antenna arrays. Possible advantages include reduced wiring, reduced tuning, reduced EMI, and/or power consumption and easier in-service growth, relative to conventional methods for the same performance objectives. >

Digital costas loop-like PLL for the carrier recovery of a QPSK signal

A new digital PLL (DPLL) circuit is proposed primarily conceived for QPSK carrier recovery. It is proved that this DPLL can acquire or track the phase of the carrier even when a significant frequency deviation exists. The resulting phase error and the effects of the frequency deviation on it have been also evaluated.

A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit in silicon bipolar technology

A monolithic clock and data recovery PLL circuit is implemented in a digital silicon bipolar technology without modification. The only external component used is the loop filter capacitor. A self-aligned data recovery architecture combined with a novel phase-detector design eliminates the need for nonlinear processing and phase shifter stages. This enables a simpler design with low power and reduced dependence on the bit rate. At 2.3 Gb/s, the test chip consumes 100 mW from a -3.6-V supply, excluding the input and output buffers. The worst-case rms jitter of the recovered clock is less than 14 ps with 2/sup 23/-1 pseudorandom bit sequence.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Si bipolar technology

An all-band TV tuner IC with an on-chip PLL and a high-voltage output stage is developed. The use of a self-aligned bipolar technology called high-voltage compatible sidewall base contact structure (HV-SICOS) allows the integration of 1-GHz analog circuits, 1-GHz low-power ECL-I/sup 2/L PLL circuits, and a 0.5- to 30-V tuning diode bias current on the same chip. The analog block has a VCO and mixer pair for the VHF/CATV and another pair for the UHF bands, a UHF input amplifier, an IF amplifier, and a VCO signal switching circuit. To suppress the digital noise level for mixed analog/digital mode operation, the PLL is constructed with high-speed ECL circuits for divide-by-four and dual modulus prescalers, and low-power I/sup 2/L circuits. An isolation area is placed between the analog and digital blocks. Conversion gain of 24 dB for VHF/CATV and 33 dB for UHF, a noise figure of 10 dB, and 1% cross modulation of 95 dB- mu V are obtained. This IC operates with a total power dissipation of 200 mW on a 3-mm*4-mm chip. >

An all digital Costas loop-like PLL circuit with a wide locking range

Abstract An algorithm is proposed for the construction of an all digital phase locked loop (DPLL) which is conceived primarily for binary PSK carrier recovery. A wide locking range technique is used in constructing a digital implementation of the Costas loop with small phase error and the ability to track and acquire the phases of carriers with significant frequency deviation. This implementation is digitally simulated, its performance under bandpass gaussian noise is tested and the resulting phase error is measured. The results are compared with those of already existing simple implementations.

Tractive Effort and Wheel Slip Control of Locomotive Type 120

The locomotive type 120 is an ac electric locomotive equipped with 3-phase traction motors. For the transmission of the high tractive efforts an optimal use of the available adhesion is required. For this purpose, a wheel slip control is integrated into the tractive effort control system. According to the unpredictability and diversity of the friction/creep relationship several wheel slip detecting criteria are implemented. For the operation at low available adhesion a tractive effort maximization is provided. Wheel creep is stabilized by means of parallel connection of traction motors and use of a PLL circuit. The wheel slip control is realized by use of a microprocessor system and a special control language adapted to controlling requirements. Extensive road tests have been carried out to optimize the various wheel slip control features.

Method for measurement of shear-wave impedance in the MHz region for liquid samples of approximately 1 ml

A method for measuring both the real and imaginary parts of complex shear-wave impedance Zs* for low viscosity liquids using a planar AT-quartz resonator (thickness shear) in an RF bridge network between 2 and 34 MHz, is described. This technique employs a PLL circuit and permits continuous quantitative recording of the sample impedance (probe volume below 1 ml). The mechanical vibration amplitude at the transducer-liquid interface is in the Angstrom range, preventing any heating and structural damage effects. Incremental Zs-resolution is better than 50 kg m-2 s-1 ( approximately 1% of water impedance at 6 MHz), as is demonstrated by test measurements on different newtonian liquids. These measurements show that Zs* values determine quantitatively the shear quartz resonator parameters. This method permits measurements of interface and surface layer properties.

A 150-mW subscriber-line-board controller

A line circuit-board controller for digital exchanges is presented. The system, circuit, and technological aspects of the design are discussed. The dual-processor terminal controller (DPTC) interfaces serially with two independent exchange processors and up to 16 subscriber-line circuits. The device interfaces to time-division multiplex links, handles control and signaling in dedicated channels, has the ability to sense change in the subscriber-line status, and provides data switching for the 16 subscriber-line circuits. An analog PLL circuit builds the 4-MHz local timing out of the two asynchronous exchange clocks. In order to achieve low power consumption and minimal area, all the circuitry is implemented using clocked dynamic CMOS.

HVDC Transmission Control Equipment with High Reliability

A triplicated digital control equipment has been developed to improve reliability and performance of HVDC transmission. For improved reliability, DDC is used which is best suited to triplicated systems. The triplicated control equipment made up of three digital control equipments utilizes the self-diagnostic function of microcomputer to the maximum extent. It also employs an intermediate value selection as a signal selection method. The computation in the three control systems is performed in synchronism with the ac system to minimize signal transfer among the three systems and thereby facilitate maintenance. A new PLL circuit for synchronism detection is used to protect the HVDC transmission against ac system disturbances. An Operating System (OS) specially programed for HVDC transmission control is incorporated in the microcomputer to perform ac system control. The developed digital control equipment was tested in the simulated transmission facility. The simulation test showed that the control system has improved performance and reliability.

A single-chip FM modem baseband CMOS LSI for land mobile telephone radio units

A single-chip FM modulator/demodulator (modem) based LSI for the 800-MHz band land mobile radio unit has been developed. This LSI contains both digital and analog function blocks. The digital function block consists of high-speed digital PLL circuits such as a dual modulus prescaler, a programmable counter, and a phase frequency comparator for a 145 MHz direct FM modulator. The analog one consists of transmit and receive analog baseband circuits such as a voice limiter and various kinds of filters. In order to realize a high-speed and low power dissipation LSI, the pulse swallow method and switched capacitor technology have been used in the digital and analog circuits, respectively. The LSI chip is fabricated using a double polysilicon gate CMOS process with an effective channel length of 2 /spl mu/m. The chip size is 5.2 mm/spl times/5.8 mm. The circuit operates with a single voltage supply of 5 V. Typical power dissipation is 90 mW.

Fiber-Optic Link Design Considerations for Applications in Noisy Industrial Environments

Industrial system considerations suggest the need for fiberoptic data links that have the ability to reduce susceptibility to noise from EMI or RFI, to isolate a system from high voltages and transmit reliable data. This paper deals with the design aspects of a fiber-optic system link, suitable for industrial process applications, and addresses process environments with slowly changing parameters such as: pressure, temperature, position (both rotary and linear), etc., available at the output of system interfacing sensors in the form of voltages, where less attention has been paid thus far. The approach used involves a voltage-pulse frequencyvoltage conversion technique with a VCO in the modulator and a PLL circuit in the demodulator. By changing a few components, the system can be converted into a simplex intercommunication optical link.

Switched-capacitor implementations of phase-locked loops

Novel configurations of PLL circuits consisting of capacitors, switches and active elements are investigated. Three topologies of phase loops are discussed. The phase loops derived show a number of attractive features. Design examples are provided, and illustrative experimental results are included.

A 120 MHz AM/FM PLL-IC with Dual On-Chip Programmable Charge Pump/Filter OP-AMP

In the past single chip frequency synthesizer tuning systems have been developed which are suitable for simple radio sets, but bring problems if designed into more sophisticated radios. Separation of the control and display functions from the tuning function allow the PLL circuit to be situated near the tuners and the control and display function near the front of the receiver. This minimises internal radiation as well as the number and length of internal interconnections.