Plastic Leaded Chip Carrier Packages Research Articles

Whisker Formation on SAC305 Soldered Assemblies

This article describes the results of a whisker formation study on SAC305 assemblies, evaluating the effects of lead-frame materials and cleanliness in different environments: low-stress simulated power cycling (50–85°C thermal cycling), thermal shock (–55°C to 85°C), and high temperature/high humidity (85°C/85% RH). Cleaned and contaminated small outline transistors, large leaded quad flat packs (QFP), plastic leaded chip carrier packages, and solder balls with and without rare earth elements (REE) were soldered to custom designed test boards with Sn3Ag0.5Cu (SAC305) solder. After assembly, all the boards were cleaned, and half of them were recontaminated (1.56 µg/cm2 Cl−). Whisker length, diameter, and density were measured. Detailed metallurgical analysis on components before assembly and on solder joints before and after testing was performed. It was found that whiskers grow from solder joint fillets, where the thickness is less than 25 µm, unless REE was present. The influence of lead-frame and solder ball material, microstructure, cleanliness, and environment on whisker characteristics is discussed. This article provides detailed metallurgical observations and select whisker length data obtained during this multiyear testing program.

The Comparison between Four PLCC Packages and Eight PLCC Packages in Personal Computer (PC) Using Computational Fluid Dynamic (CFD), FLUENT Software<sup>TM</sup> Using Epoxy Moulding Compound Material (EMC)

The paper present the three dimensional numerical analysis of heat and fluid flow through Plastic Leaded Chip Carrier (PLCC) packages in inline orientation horizontally mounted on a printed circuit board in a wind tunnel is carried out using a commercial CFD code, FLUENTTMby using Epoxy Moulding Compound (EMC) as a main material. The study was made for four and eight packages with different Reynolds Number and package chip powers. The results are presented in term of junction temperature for four and eight PLCC package under different conditions. It is observed the chip temperatures of eight PLCC packages have higher junction temperature compare to four PLCC packages due to effect of other PLCC because of space and gap between PLCC that have more number of PLCC is smaller. Hence it makes junction temperature of eight PLCC higher compare to four PLCC packages. Moreover, the junction temperature of the packages decreases with increase in Reynolds Number.

Numerical Investigation of Heat Transfer of Twelve Plastic Leaded Chip Carrier (PLCC) by Using Computational Fluid Dynamic, FLUENT<sup>TM</sup> Software

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for 12 PLCC under different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial.

Numerical investigation of heat transfer in Plastic Leaded Chip Carrier (PLCC) packages in in-line arrangement

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for three configurations such as 4PLCC, 8PLCC and 12PLCC under natural, mixed and forced convection modes with different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial. Keywords: PLCC package, Thermal management, Numerical simulation, Average junction temperature

3-D conjugate heat transfer analysis of PLCC packages mounted in-line on a Printed Circuit Board

This paper presents a three dimensional heat and fluid flow analysis of two Plastic Leaded Chip Carrier (PLCC) packages mounted in tandem arrangement on a Printed Circuit Board (PCB) exposed to the free stream velocity. The numerical simulation was done using FLUENT 6.3 and the experiments were performed by using an air chamber with nozzle, at different approach air velocities to emulate the forced convection heat transfer phenomena. Parameters such as junction temperature, thermal resistance and top surface average Nusselt number have been studied for each package by varying the chip power, spacing between the packages and approach air velocities. The decrease in the junction temperature of the packages with the increase in approach air velocity is clearly observed. Furthermore, the Nusselt number of PLCC 1 is always slightly higher than PLCC 2 for all approach velocities considered. The results also show that the spacing between packages influences the thermal resistance and average Nusselt number for both packages at a particular approach air velocity. The simulation results obtained are found in satisfactory agreement with the experimental results.

A practical assessment of current plastic encapsulated microelectronic devices

AbstractThe use of plastic encapsulated devices (PEDs) for a variety of market sectors has been the subject of much discussion over the past two decades. The advantages of lower cost together with the inherent mechanical ruggedness of these non‐cavity packages have been weighed against the concerns over quality and reliability and, in particular, electrical operation at extremes of temperature. This paper presents the results of some practical work undertaken on a modern LSI device in a plastic leaded chip carrier package. It then discusses British Telecom's experience with PEDs to date and concludes with some general considerations on the quality assurance requirements a purchaser may place on vendors of such devices.

A dynamic programming processor for speech recognition

A dynamic programming processor with parallel and pipeline architecture is described. A 2- mu m CMOS technology was applied to the DP processor, which is composed of 127309 transistors on a 7.17*8.62-mm/sup 2/ die and is housed in an 84-pin PLCC (plastic leaded chip carrier) or PGA (pin grid array) package. The clock frequency is 20 MHz, and the instruction cycle time is 100 ns. Precise electrical simulations permitted the safe use of nonstandard logic and area and power reduction. Implementation of a direct access to all internal registers has proven useful for chip test and software development. A system using one DP processor has given very good results on a wide variety of applications and 0.48% error rate on tests with standard NATO tapes. These results are significantly better than those published for other systems on the same tests. >

Nonlinear thermal behavior of a plastic leaded chip carrier package

A finite-element simulation of the steady-state thermal field in a freely suspended plastic package of the plastic leaded chip carrier type is presented. Numerical results are reported and compared with the corresponding experimental ones. The nonlinear dependence of thermal resistance on dissipated power is shown. >