Plasma-enhanced Tetraethylorthosilicate Research Articles

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and the stress problem becomes more and more serious. Therefore, the low cost and low stress plasma enhanced tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP) oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer. In our experiment both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase protection. There is not any void found in the two oxide structures. However, oxide pitting is spotted in the subsequent diluted hydrofluoric acid wet etching in the PE TEOS split. Moreover, we observe that the top silicon nitride corrodes in hot phosphoric acid. We study the mechanism of PE TEOS oxide pitting and silicon nitride corroding, propose two solutions: (1) HDP oxide + PE TEOS, and (2) PE TEOS + dry etching. Experimental results demonstrate that our solutions can well address the issue of PE TEOS oxide pitting and effectively protect the staircase structure. This work extends the application of PE TEOS oxide of which the cost and the stress are both low in 3D NAND.

Precision Au Electrocoating of Double Sided Aligned Si Gratings for High Energy X-Ray Phase Contrast Imaging

State of the art grating fabrication currently limits the maximum source energy that can be used in lab based x-ray phase contrast imaging (XPCI) systems. In order to move to higher source energies, and image thicker and more dense materials, new grating fabrication methods are needed. In previous work we developed a differentiating mold construction technique that replaces photodefinable organic templates1 with high aspect ratio silicon (Si) deep reactive ion etching (DRIE) followed by precision electrodeposition of gold (Au)2. Combining DRIE with precision electro-coating enabled the fabrication of un-supported Au absorption gratings with aspect ratios as high as 50:1 and grating areas as large as 100 cm2. Further pushing this grating fabrication to enable the use of higher energy x-ray sources, we developed a new modality for grating fabrication that involves precision alignment of etched features on both sides of a substrate, effectively doubling the thickness of the. This double sided grating fabrication approach was applied to make a phase grating out of DRIE Si. In this work, we couple double sided Si DRIE with precision gold (Au) electrodeposition to fabricate absorption gratings for high energy lab based XPCI. A 250 µm deep, 2 µm wide, and 4 µm pitch absorption grating was fabricated by aligning and etching 125 µm deep grating features on both sides of a Si wafer. The Si grating features are patterned and etched on an 8 µm pitch with the width of the Si features patterned at 2 µm. Fabricating uniform, high aspect ratio features across large areas on both sides of a substrate is difficult due to the need to temporarily protect one side of the grating while processing on the opposite side of the substrate. After both sides are processed, this temporary support material must be removed without damaging the gratings on either side of the substrate. At these feature sizes, surface tension forces after wet processing are strong enough to collapse the grating features and must be carefully avoided. Our integration approach for accommodating these challenges is illustrated in Figure 1. Alignment features are first patterned and etched into both sides of the substrate. The front side gratings are then patterned with reference to the front side field image alignment marks and etched into the Si. Plasma enhanced tetraethylorthosilicate (PETEOS) SiO2 is then deposited to protect the front side gratings during backside processing. The backside gratings are similarly aligned using the alignment marks on the backside of the substrate. After the gratings on both sides of the substrate are etched, a selective wet etch is used to remove the supportive oxide and a critical point dryer is used to prevent surface tension forces from damaging the Si bars. A conformal platinum (Pt) plating seed metal is deposited by atomic layer deposition (ALD) and Au is precisely electroplated at a uniform thickness of 2 μm throughout the depth of the Si grating. The Au serves as a high x-ray absorbing material finalizing the fabrication process. In this work, we provide details on our fabrication approach and measurements of our final grating geometries. Supported by the Laboratory Directed Research and Development program at Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. [1] - High Aspect Ratio Gratings for X-Ray Phase Contrast Imaging: J. Mohr, T. Grund, D. Kunka, J. Kenntner, J. Leuthold, J. Meiser, J. Schulz and M. Walter, International Workshop on X-Ray and Neutron Phase Imaging with Gratings, Tokyo, Japan, 2012; [2] - Extensively long high aspect ratio gold analyzer gratings: A. E., Hollowell, C. L. Arrington, J. J. Coleman, P. S. Finnegan, A. M. Rowen, and A. L. Dagel, X-ray and Neutron Phase Imaging with Gratings, Bethesda, MD, 2015 [3] – Double Sided Grating Fabrication for High Energy X-Ray Phase Contrast Imaging: A. E. Hollowell, C. L. Arrington, P. Finnegan, K. Musick, P. Resnick, S. Volk, and A. L. Dagel, Material Science in Semiconductor Processing, 2018, under review. Figure 1

Mechanism of void formation in TiN/AlSiCu/TiN/plasma-enhanced tetraethyl orthosilicate SiO2 multi-layer structures via high-temperature stress migration

In this study, the mechanism of void formation in the Al metal lines of TiN/Al-1%Si-0.5%Cu/TiN anti-refraction coating multi-layer structures has been investigated. The produced voids exhibited distinct characteristics (such as the presence of silicon nodules) and did not possess conventional shapes (such as notch-type or wedge-type ones). In addition, the influence of the nitriding temperature of the TiN barrier film and stress generated in the upper plasma-enhanced tetraethyl orthosilicate (PE-TEOS) SiO2 layer on the void formation process was examined. When the compression stress of the upper PE-TEOS SiO2 layer was below that of the lower Al film during annealing, multiple dislocations were generated in the Al layer followed by the formation of vacancies during the recovery stage. Furthermore, the TiN barrier films formed by the nitriding of Ti layers via rapid thermal annealing at a temperature of 760 °C did not exhibit sufficient thermal stability and easily underwent plastic deformation during annealing, which promoted the formation of voids.

Effect of Silicon Dioxide Hardness on Scratches in Interlevel Dielectric Chemical–Mechanical Polishing

In the silicon dioxide chemical–mechanical polishing (CMP) process, one of the most challenging issues is the formation of defects such as scratches. In this study, scratch formation behavior and CMP performance were evaluated on high-density plasma oxide (HDP), plasma-enhanced tetraethylorthosilicate (PETEOS), and borophosphosilicate glass (BPSG) wafers. To evaluate the number of scratches after the CMP process, contaminated abrasive particles were removed using an optimized post-CMP cleaning process consisting of scrubber cleaning and dilute SC1 megasonic cleaning. The oxide wafers were then treated with dilute hydrogen fluoride (HF) in order to improve the visibility of the generated scratches. The number and shape of the scratches were investigated as a function of oxide film hardness. The results show that a decrease in film hardness correlates with an increase in the number of scratches. Three different types of scratches (chatter marks, line, and rolling) were observed on the oxide surfaces. The dominant scratch shape on all three oxide films was chatter mark–type scratches. This could be attributed to the stick–slip phenomenon. However, the overall fraction of chatter marks compared to other types of scratches (especially line scratches) was proportional to the film hardness. It was also found that scratch depth was strongly influenced by the polishing pressure during CMP. The results clearly show that the mechanical pro- perties of the surface play a critical role in scratch generation.

Functions of Trilon® P as a polyamine in copper chemical mechanical polishing

In this paper, as a representative of the polyamines, Trilon® P was used as a critical additive in copper slurries to improve the copper chemical mechanical polishing (CMP) performance, and high copper removal rate (RR), low copper static etching rate (SER), low dishing and low dielectric erosion were realized by CMP tests on the copper patterned wafers. The chelating reactions between Trilon® P and cupric ions are revealed, and it is found that the reaction product Cu–Trilon® P complex has dual functions for copper RR and SER: the negative one is from the weak passivation and the lubrication while the positive one is from the complexation with cupric ions and the facilitation of (*OH) formation, and the final polishing result depends on the competition between the above two functions. In addition, the adsorption of Trilon® P on the plasma enhanced tetraethylorthosilicate (PETEOS) surface helps form a lubricating thin film, which relieves the severe mechanical stress on the PETEOS pattern, and thus results in low dielectric erosion.

Through Silicon Via Fabrication with Low-κ Dielectric Liner and Its Implications on Parasitic Capacitance and Leakage Current

Through silicon via (TSV) has emerged as an essential enabler for three-dimensional integrated circuit (3D IC). The basic TSV structure consisting of a via hole in the Si substrate filled with metal such as copper and lined with a dielectric liner, forms a metal–oxide–silicon (MOS) capacitor structure. To benefit the performance of 3D IC, the TSV used to interconnect vertically stacked dies must introduce small electrical parasitic, such as capacitance. The isolation property of the dielectric liner must also be preserved to control the leakage current. In this work, TSV with acceptable sidewall roughness is achieved and lined with low-κ material with an effective dielectric constant of ∼2.8. Low-κ liner with conformal step coverage is successfully achieved in our fabrication process. Based on electrical measurement, it is found that the integration of the low-κ liner reduces the TSV capacitance by ∼27.6% as compared with the conventional plasma-enhanced tetraethylorthosilicate (PETEOS) oxide liner. In addition, current–voltage (I–V) measurement is carried out to monitor and study the leakage of the low-κ liner. No abrupt breakdown is observed until at least at an electric field of 3 MV/cm which corresponds to 60 V. Annealing of the TSV structure in forming gas (N2/H2) at 350 °C for 30 min successfully reduces the leakage current density by ∼1.6×, to a mid-distribution value of ∼6.8×10-6 A/cm2.

PE-TEOS Wafer Bonding Enhancement at Low Temperature with a High- κ Dielectric Capping Layer of Al2O3

The bond strength of plasma-enhanced tetraethyl-orthosilicate (PE-TEOS) oxide wafers, bonded and annealed at low temperatures ( and below), is enhanced by using a thin layer of high-κ dielectric at the bonding interface. Prior to bonding, a thin capping layer of high-κ dielectric was deposited using atomic layer deposition on polished PE-TEOS wafers, followed by surface activation. It was found that after a anneal in ambient for , the bond strength of a wafer pair bonded with /PE-TEOS oxide was enhanced by 73.3%. The bonding interface is stable and seamless with no presence of a microvoid.

(Invited) PE-TEOS Wafer Bonding Enhancement at Low Temperature with a High-k Dielectric Capping Layer

The bond strength of plasma-enhanced tetraethyl-orthosilicate (PE-TEOS) oxide bonded and annealed at low temperature (300 oC and below) is enhanced using a thin layer of high-K dielectric at the bonding interface. Prior to bonding, thin (~5 nm) capping layer of Al2O3 high-K dielectric is deposited using atomic layer deposition (ALD) on polished PE-TEOS wafers followed by surface activation. It is found that after 300 oC anneal in N2 ambient for 3 h, bond strength of wafer pair bonded with PE-TEOS oxide is enhanced by 73.3%. The bonding interface is seamless with no presences of micro-void.

Low Temperature PE-TEOS Oxide Bonding Assisted by a Thin Layer of High-κ Dielectric

The bond strength of plasma-enhanced tetraethyl-orthosilicate (PE-TEOS) oxide, bonded and annealed at low temperatures (300°C and below), is enhanced using a thin layer of high-κ dielectric at the bonding interface. Before bonding, various thin ( ~5 nm) capping layers of high-κ dielectrics (Al 2 O 3 , HfO 2 , and TiO 2 ) are deposited separately on polished PE-TEOS wafers, followed by surface activation. After a 300°C anneal in N 2 ambient for 3 h, the bond strength of wafer pairs bonded with PE-TEOS oxide is enhanced by 97.9, 73.3, and 31.0%, respectively, with TiO 2 , Al 2 O 3 , and HfO 2 layers at the interface.

Temperature effect on low-k dielectric thin films studied by ERDA

Low-k dielectric materials are becoming increasingly interesting as alternative to SiO2 with device geometries shrinking beyond the 65 nm technology node. At elevated temperatures hydrogen migration becomes an important degradation mechanism for conductivity breakdown in semiconductor devices. The possibility of hydrogen release during the fabrication process is, therefore, of great interest in the understanding of device reliability. In this study, various low-k dielectric films were subjected to thermal annealing at temperatures that are generally used for device fabrication. Elastic recoil detection analysis (ERDA) was used to investigate compositional changes and hydrogen redistribution in thin films of plasma-enhanced tetraethylortho-silicate (PETEOS), phosphorus doped silicon glass (PSG), silicon nitride (SiN) and silicon oxynitride (SiON). Except for an initial hydrogen release from the surface region in films of PETEOS and PSG, the results indicate that the elemental composition of the films was stable for at least 2 hours at 450°C.

Self-assembled single walled carbon nanotubes on multi-layered polyelectrolyte layer

The assembly behavior of single walled carbon nanotubes (SWCNTs) on the functionalized plasma enhanced tetraethylorthosilicate (PETEOS) substrate was investigated. A poly(diallyldimethylammonium chloride) (PDDA)/poly(acrylic acid) (PAA)/PDDA layered structure was formed to functionalize the substrate utilizing polyelectrolyte layer-by-layer (LBL) assembly technique, and it was identified by attenuated total reflection (ATR) infrared spectroscopy and atomic force microscopy (AFM). The surface morphology of polyelectrolyte layer was manipulated by the polyelectrolyte concentration. It was found that the PDDA/PAA/PDDA multilayer with higher charge stability leads to the improvement of assembly behavior of SWCNTs, compared to PDDA single layer. These results guaranteed high reproducibility of the assembly behavior of CNTs.

Atomic force microscopy study of the role of molecular weight of poly(acrylic acid) in chemical mechanical planarization for shallow trench isolation

The influence of the molecular weight of poly(acrylic acid) (PAA) on chemical mechanical planarization (CMP) for shallow trench isolation (STI) was investigated. The adsorption behaviors of PAA as a function of molecular weight on deposited plasma-enhanced tetraethylorthosilicate and chemical vapor deposition Si3N4 films were analyzed by the force measurement using atomic force microscopy (AFM). The AFM results revealed that the affinity of PAA with the nitride film is higher than the affinity with the oxide film, and thus a denser adsorption layer on the nitride film is formed with higher molecular weight of PAA, which leads to higher selectivity in STI CMP. Additionally, to determine the correlation between the dispersion stability of the CeO2 resulting from the presence of PAA with different molecular weight and CMP performance, the colloidal properties of the slurry as a function of the molecular weight of PAA were examined.

Low-Temperature PETEOS-to-PETEOS Wafer Bonding Using Titanium as Bonding Intermediate

AbstractBonding of pre-processed silicon wafers at back-end-of-the-line (BEOL) compatible conditions is one of the attractive approaches for three-dimensional (3D) integration. Among various technologies being evaluated, bonding of low temperature oxides (e.g., plasma-enhanced tetraethylorthosilicate (PETEOS)) is of great interest. In this work, we report low-temperature PETEOS-to-PETEOS wafer bonding, using a thin layer of titanium (Ti) as bonding intermediate. The bonding strength is evaluated qualitatively, while the bonding interface is examined by Auger electron spectroscopy (AES) and scanning electron microscopy (SEM). Preliminary results of PETEOS/Ti/PETEOS bonding on patterned wafers with single-level Cu damascene structures are also discussed.

Agglomerated Large Particles under Various Slurry Preparation Conditions and Their Influence on Shallow Trench Isolation Chemical Mechanical Polishing

The effects of various slurry manufacturing conditions, such as suspension pH, abrasive contents, and the calcination temperature of abrasive ceramic particles on the formation of agglomerated large particles of ceria slurry were investigated. The agglomerated large particles in slurry have much influence on the micro-scratches on the wafer surface in shallow trench isolation chemical mechanical polishing (STI CMP). The formation of large agglomerated particles is affected by the conformation of the organic additives in the slurry as a function of the suspension pH and the specific surface area of the abrasive particle. Regarding the solid content, abrasive particles are more easily dispersed at lower solid loading, which prevents additional agglomeration even under acidic conditions. The influence of agglomerated large particles on STI CMP was investigated through a polishing experiment with plasma-enhanced tetra-ethyl-ortho-silicate (PETEOS) and a low-pressure chemical vapor deposition (LPCVD) nitride layer.

A Reverse Selectivity Ceria Slurry for the Damascene Gate Chemical Mechanical Planarization Process

The reverse selectivity of nanosized ceria slurry for the damascene gate chemical mechanical planarization (CMP) process has been investigated. The relationship between the electrokinetic behaviors of abrasive ceria particles and the plasma-enhanced tetraethylorthosilicate (PETEOS), and CVD Si3N4 films in an aqueous medium were observed to determine the reverse selectivity performance in the CMP process. The surface potentials of abrasive and PETEOS/CVD Si3N4 films were found to have different surface charges in certain pH regions and these differences were found to be key parameters in the selective removal performance of damascene gate CMP process. The ceria slurry with polymeric additives showed reverse selectivity with a low PETEOS removal rate and a high CVD Si3N4 film removal rate.

Influence of Physical Characteristics of Ceria Particles on Polishing Rate of Chemical Mechanical Planarization for Shallow Trench Isolation

By considering the physical characteristics of ceria particles, the factors affecting the chemical mechanical planarization (CMP) performance for shallow trench isolation (STI) were investigated. Ceria powders were synthesized by calcination at temperatures of 400, 600, 700, 800, and 900°C. The influence of the calcination temperature on the physical characteristics, such as the crystallinity, grain size, porosity, morphology and high-resolution lattice images of the ceria particles, were investigated, and a correlation between the physical characteristics and the electrokinetic behaviors of the ceria particles in aqueous suspending media was also investigated to identify the relationship with CMP performance. Grain size increased with calcination temperature, as did the removal rate of plasma-enhanced tetraethylorthosilicate (PETEOS) film with slurries including these particles. The results indicate that the grain size of ceria particles is one of the key parameters controlling the removal rate and uniformity of PETEOS film.

Influence of the electrokinetic behaviors of abrasive ceria particles and the deposited plasma-enhanced tetraethylorthosilicate and chemically vapor deposited Si3N4 films in an aqueous medium on chemical mechanical planarization for shallow trench isolation

The effects of the electrokinetic behavior of abrasive ceria particles suspended in an aqueous medium and the deposited plasma-enhanced tetraethylorthosilicate (PETEOS) and chemical vapor deposition (CVD) Si3N4 films on chemical mechanical planarization (CMP) for shallow trench isolation were investigated. The colloidal characteristics of ceria slurries, such as their stability and surface potential, in acidic, neutral, and alkaline suspensions were examined to determine the correlation between the colloidal properties of ceria slurry and CMP performance. The surface potentials of the ceria particles and the PETEOS and CVD Si3N4 films in an aqueous suspending medium were dependent on the pH of the suspending medium. The differences in surface charges of ceria particles and the PETEOS and CVD Si3N4 films have a profound effect on the removal rate and oxide-to-nitride selectivity of CMP performance.

Effects of the Physical Characteristics of Cerium Oxide on Plasma-Enhanced Tetraethylorthosiliate Removal Rate of Chemical Mechanical Polishing for Shallow Trench Isolation

Ceria powders were synthesized by two different methods, solid-state displacement reaction and wet chemical precipitation, and the influence of the physical characteristics of cerium oxide on the removal rate of plasma-enhanced tetraethylorthosilicate (PETEOS) and chemical vapor deposition (CVD) nitride films in chemical mechanical planarization (CMP) was investigated. The fundamental physicochemical property and electrokinetic behavior of ceria particles in aqueous suspending media were investigated to identify the correlation between the colloidal property of ceria and the CMP performance. The surface potentials of two different ceria particles are found to have different isoelectric point (pHiep) values and differences in physical properties of ceria particles such as porosity and density were found to be the key parameters in CMP of PETEOS films. Ceria powders synthesized by the solid-state displacement reaction method yielded a higher removal rate of PETEOS and higher selectivity than powders synthesized by the wet chemical precipitation method.

Correlation analysis between pattern and non-pattern wafer for characterization of shallow trench isolation–chemical–mechanical polishing (STI–CMP) process

This study is about control of oxide removal amounts on the shallow trench isolation (STI) patterned wafers using removal rate and thickness of blanket (non-patterned) wafers. At first, the removal properties of plasma enhanced tetra-ethyl ortho-silicate (PETEOS) blanket wafers was investigated, and then it was compared with the removal properties and the planarization (step height) as a function of polishing time of the specific STI patterned wafers. We found that there is a relationship between the amount of oxide removal by blanket and patterned wafers. We analyzed this relationship, and the post-CMP thickness of patterned wafers could be controlled by removal rate and removal target thickness of blanket wafers. As the result of correlation analysis, we confirmed that there was the strong correlation between patterned and blanket wafers (correlation factor: 0.7109). So, we could confirm the repeatability as applying to STI CMP process from the linear formula obtained.

Pattern density and deposition profile effects on oxide chemical-mechanical polishing and chip-level modeling

Test masks for characterizing pattern-dependent variation of the remained thickness after chemical-mechanical polishing (CMP) were designed by taking the experimentally obtained interaction distance into consideration. Polishing behaviors were characterized by taking into consideration layout pattern density and pitch variations using these masks. Deposition profile effects were also compared between plasma-enhanced tetra ethyl ortho silicate (PETEOS) and high-density plasma (HDP) oxide. Both the measured post-CMP thickness and the expected oxide pattern density after the consideration of deposition profile effects showed a good correlation with respect to the pitch variation for a constant layout pattern density. Also, the relationship between remained thickness and true layout pattern density was deduced. Chip-level CMP modeling was investigated to obtain the post-CMP thickness distributions across a die from its design layout and a few oxide film and CMP parameters. The experimental CMP results agreed well with the modeling results. The effective dummy filling results were shown to achieve a smaller pattern density variation, which resulted in better post-CMP thickness uniformity. Whether the resulting oxide thickness could be predicted for any location on a die for an arbitrary layout, if the effective pattern density distributions are calculated, was discussed.