We introduce a deep-recessed gate architecture in β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> delta-doped field-effect transistors (FETs) for improvement in dispersion and breakdown properties. The device design incorporates an unintentionally doped (UID) β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer as the passivation dielectric. To fabricate the device, the deep-recess geometry was developed using BCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma-based etching at 5 W reactive ion etching (RIE) power to ensure minimal plasma damage. Etch damage incurred with plasma etching was mitigated by annealing in vacuum at temperatures above 600 °C. A gate-connected field-plate edge termination was implemented for efficient field management. Negligible surface dispersion with lower knee walkout at high VDS, and better breakdown characteristics compared to their unpassivated counterparts were achieved. A three-terminal OFF-state breakdown voltage of 315 V, corresponding to an average breakdown field of 2.3 MV/cm was measured. The device breakdown was limited by the field-plate/passivation edge and presents scope for further improvement. This demonstration of epitaxially passivated FET is a significant step for β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> technology since the structure simultaneously provides control of surface-related dispersion and excellent field management.