Planar Metal Oxide Research Articles

Tunneling Current Calculation Using the Linear‐Bound Potential Model

A model of the tunneling current through an ultrathin insulating barrier coming from carriers in an inversion layer using a simple linear potential model is presented. This model provides analytical expressions for the wavefunctions of these carriers and simple equations to obtain numerically their corresponding eigenvalues. These expressions can be inserted in the tunneling current equation allowing a more simple understanding of the physics involved in this tunneling problem. As an example, one can fit the experimental results for the leakage current obtained by different authors in planar metal oxide semiconductor field effect transistors and also in a LaAlO3/SrTiO3 and a HfO2/Ge bilayer. The modification of the tunneling current when the dielectric constant is increased, a subject of interest in device applications, is explored.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

3D lithography enable ultrathin flat compound eye for moving object imaging

With a hemispherical surface, the compound eye cameras inspired by arthropod eyes provide a large field of view (FOV), low aberration, and a large depth of field. However, to match the hemisphere-imaging plane, the cameras require a hemisphere-photoelectric sensor instead of a standard planar complementary metal oxide semiconductor (CMOS) sensor. Additionally, the hemispheric shape of the imaging system restricts the miniaturization of high-performance compound eye cameras at the millimeter scale. Here, inspired by the working principle of the Fresnel lens, an ultrathin flat compound eye (UFCE) composed of an off-axis microlens array (OMLA) was developed. 3D lithography enabled the fabrication of the UFCE with a complex morphology. Compared to the traditional artificial compound eye (ACE), the thickness of the UFCE was greatly reduced. Meanwhile, a flat substrate and ultrathin structure allowed for direct integration of the UFCE into the surface of a CMOS. The resultant UFCE had a FOV of up to 110° and a resolution close to the diffraction limit and low dispersion. Furthermore, the UFCE allowed for fast imaging of mobile objects in any plane within the depth of field, which is the unique function of the UFCE. In brief, the fabricated UFCE based on OMLA reduces the complexity of constructing compound eye cameras while significantly optimizing the volume, suggesting an alternative method for creating high-performing optical elements with the possibility of simple integration and miniaturization.

Unified Modeling of Gate Insulator Capacitance of Nonplanar MOSFETs Including the Impact of Inclined Sidewalls and Rounded-Corners

The conventional method of calculating the effective oxide thickness (EOT) of planar metal oxide semiconductor field-effect transistor (MOSFET) holds invalid for nonplanar devices such as gate-all-around (GAA) MOSFETs and trigate MOSFETs. In this work, a unified model for the gate insulator capacitance of various cross sections (either deliberate or process-induced) of GAA MOSFETs and trigate MOSFETs have been obtained using an approximate model of metal-insulator-metal (MIM) capacitors. We have identified four geometrical parameters of the device [Fin top width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W}_{\text {top}}$ </tex-math></inline-formula> ), Fin height ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${H}_{\text {Fin}}$ </tex-math></inline-formula> ), the normalized radius of curvature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${r}$ </tex-math></inline-formula> ), and inclination angle ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\theta $ </tex-math></inline-formula> )], varying which multiple cross sections of GAA and trigate MOSFET are obtained. Through semi-analytical approach, we have improved the existing insulator capacitance models for square and rectangular cross sections GAA to include process-induced inclined sidewalls and rounded corners in a unified expression, valid for elliptical, trapezoidal, and triangular cross sections as well. In addition, by following the same approach, we have also formulated a unified semi-analytical model for insulator capacitance of trigate MOSFETs, valid for all the above-mentioned cross sections. The proposed model has been verified to accurately reproduce the electron density for a wide range of device dimensions and applied biases.

Robust Logic Circuits Design Using SOI Shorted-Gate FinFETs

The scaling of planar Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology has reached to its extremity. Double Gate (DG) device was introduced to derive the benefits of scaling gate lengths. Fin-shaped Field Effect Transistors (FinFETs) proved to be the best architecture to realize a double gate structure. In this paper, a static leakage control technique is proposed and a ring-oscillator of five inverters based on shorted gate (SG) FinFETs is simulated using the technique. The basic logic gates like Inverter, 2-input NAND gate, and 2-input NOR gate are simulated using the proposed technique. Leakage power and Power Delay Product (PDP) optimization of 93.46% and 97.78% has been found in 2-input SG FinFET-based proposed NAND gate compared to that of 2-input SG FinFET-based conventional NAND gate.Also, SG FinFET-based proposed 2-input NOR gate shows 98.03% and 98% optimization of leakage power and PDP,respectively compared to the SG FinFET-based conventional 2-input NOR gate. The proposed SG FinFET-based ring-oscillator shows a leakage power and PDP optimization of 62.12% and 35.56%, respectively in comparison to theconventional SG FinFET-based ring-oscillator. The reliability of the proposed circuit is calculated, which came out to be thehighest at 0.7V supply and 16nm process node for a 10% deviation in operating parameters. Also, the process parametervariation of leakage power, delay, and PDP of the proposed circuit came out to be proper and stable thus maintaining thefunctionality of the proposed circuit.

Sodium‐Containing Surface Film Formation on Planar Metal–Oxide Electrodes with Potential Application for Sodium‐Ion and Sodium–Oxygen Batteries

Excellent, self‐improving sodiation rate capabilities in combination with high capacity retention upon galvanostatic charge/discharge cycling are found for oxygen‐deficient, carburized, and self‐organized titanium dioxide (TiO2−x) nanotubes (NTs). The sodiation mechanism is attributed to the formation of an acicular surface film as the active storage material with sodium (Na) peroxide (Na2O2) being the main component. Whether the proposed surface chemistry is unique for TiO2 NTs or serves as a common scheme for Na‐ion storage at metal oxide surfaces, in general, is not clear by now. Herein, three different materials, titanium(IV) oxide in the anatase and rutile phase and molybdenum(IV) oxide, are investigated in a planar electrode geometry toward their capability for Na‐ion storage. It is shown that all three materials under investigation demonstrate a significant progression of capacity increase upon cycling in combination with the formation of a Na‐oxide containing surface film. These “self‐improving” characteristics are found to significantly enhance the Na‐ion storage performance of the electrodes during long‐term galvanostatic cycling in a Na‐containing electrolyte.

A physical insight into variation aware minimum V DD for deep subthreshold operation of FinFET

Several ultra-low power applications, that do not require high performance, can benefit from operation at the lowest possible supply voltage. Scaling of supply voltage is an effective method to reduce the energy consumption in digital circuits. The fundamental limit for supply voltage has been established as 36 mV for planar complementary metal oxide semiconductor (CMOS) circuits based on Shannon’s channel capacity theorem. Owing to its near ideal sub-threshold characteristics, fin field effect transistor (FinFET) devices are a better fit for ultra-low voltage applications than planar devices. In this work, the fundamental limit on supply voltage for FinFET based logic circuits has been established for the first time. This theoretical limit is found to be significantly lower than the limit for planar CMOS circuits. The effect of variation of temperature and device design parameters on this fundamental limit is also explored. The analysis is extended to other logic gates such as NAND gate. Since the operation of a FinFET device in the ultra-low voltage domain is quite different from its planar counterpart, a novel physics based, semi-empirical current equation valid for supply voltage below 100 mV has been proposed for a FinFET device to calculate this fundamental limit. Such a current model is of great importance to a circuit designer because of the ease it offers for the back of the envelope calculations. The logic gates operating in this regime are then analyzed using this proposed model.

Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique.

Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.

Whale Optimization Algorithm Approach for Performance Optimization of Novel Xmas Tree-Shaped FinFET

Today, Fin shaped Field Effect Transistors (FinFETs) are the framework of the sub-nanometer technology node. The leading semiconductor industry deploys it in low-power (LP) and high-performance (HP) applications due to its better electrostatic control and exceptional scalability. In this paper, a novel optimized and miniaturized Xmas tree-shaped FinFET was designed that provides reduced short channel effects and better analog parameters as compared to the planar Metal Oxide Semiconductor Field Effect transistor. This proposed structure was devised with the Genetic Algorithm (GA) and Whale optimization Algorithm (WOA) along with the Artificial Neural Network (ANN). The dataset used in ANN training was created through designing and simulating the Xmas tree shaped FinFET structure by varying its Fin-width (WFin) and Fin-height (HFin). Through ANN-GA and ANN-WOA optimization, the optimal value of WFin and HFin was calculated at the minimum Subthreshold Swing (SS) and off-current (IOFF) along with maximum on-current (ION). The proposed Xmas tree shaped FinFET structure was designed and simulated with the optimal value of WFin and HFin that resulted in superior performance parameters. SS, IOFF, and ION values were 63.3 mV/dec, 77.3pA, and 0.51 μA respectively; suggesting that the optimized structure has more control over undesired Short Channel Effects. The deviation of less than 5% between optimized and simulated performance parameters substantiates the effectiveness of the optimization process. It has been estimated that the novel device consumes 40% lesser area than the rectzoidal structures designed in literature. A notable improvement has been observed in the area consumption due to the usage of multiple substrates.

Bright Single Photon Emission from Quantum Dots Embedded in a Broadband Planar Optical Antenna (Advanced Optical Materials 7/2021)

A planar metal–oxide–semiconductor structure, capable of beaming the photons emitted by epitaxial quantum dots into free space, has been designed and implemented by Huying Huang, Santanu Manna, Armando Rastelli and co-workers (see article number 2001490). The structure is tolerant to fabrication imperfections and allows the photon outcoupling efficiency to be greatly enhanced without any deterministic positioning of the quantum emitters.

Performance Measures of Different Gate Oxide Materials in Gate All Around Fet

The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by oxidation of a semiconductor namely Silicon. In this generation, an advanced technique called 3D system architecture FETs, are introduced for high performance and low power quality of devices. Based on the limitations of Short Channel Effect (SCE), Silicon (Si) FET cannot be scaled under 10nm. Hence various performing measures like methods, principles, and geometrics are done to upscale the semiconductor. CMOS using alternate channel materials like GE and III-Vs on substrates is a highly anticipated technique for developing nanowire structures. By considering these issues, in this paper, we developed a simulation model that provides accurate results basing on Gate layout and multi-gate NW FET’s so that the scaling can be increased few nanometers long and performance limits gradually increases. The model developed is SILVACO that tests the action of FET with different gate oxide materials.

Electric potential and surface oxygen ion density for planar, spherical and cylindrical metal oxide grains

In this article, the mathematical model presented by Barami and Ghafarinia (Sensors and Actuators B: Chemical 293 (2019) 31–40) for metal oxide grains is discussed. The nonlinear governing model, which is a Poisson-Boltzmann-type equation, is solved by a simple and efficient method. Analytical expressions for the electrical potential and oxygen ion density within the planar, cylindrical and spherical metal oxide grains are expressed in terms of the absolute value of the electric potential and grain thickness. In addition, an investigation of the effects of parameters such as grain diameter, grain thickness, and uniform distribution of single donors on the performance. The validity of the derived analytical expression is established by direct comparison with computer-generated numerical simulations in addition to previously available limiting cases’ results (low and high oxygen adsorption on the grain).

Reply to comments on the article “Calculation of the electric potential and surface oxygen ion density for planar and spherical metal oxide grains by numerical solution of the Poisson equation coupled with Boltzmann and Fermi-Dirac statistics” (Sensors and Actuators B: Chemical, 293 (2019))

Trakhtenberg, Ilegbusi and Kozhushner, have kindly stated issues and concerns regarding the underlying assumption of our paper entitled “Calculation of the electric potential and surface oxygen ion density for planar and spherical metal oxide grains by numerical solution of the Poisson equation coupled with Boltzmann and Fermi-Dirac statistics”. We believe that this comment is the result of misunderstanding of the contribution of our paper beyond the existing literature. This reply tries to clearly show the motivations and objectives of our paper.

Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics

Following the downscaling road map for planar metal–oxide–semiconductor field-effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate scaling of complementary metal–oxide–semiconductor devices. Gate-all-around (nanowire) field-effect transistors have proven to be the most suitable below-22 nm technology nodes. Hence the reliability of these devices is of great concern. Negative-bias temperature instability (NBTI) and hot-carrier degradation (HCD) are the key device reliability issues that exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) under direct-current and alternating-current stress were investigated. When stressed, the NBTI behavior in SNWTs showed fast initial degradation, quick degradation saturation and then a special recovery behavior. Along with that, the effects of hot-carrier stress on n-channel SNWTs were studied. Due to the surrounded gate structure, it was observed that the effects of HCD were significant in the nanowire transistors.

Dual Selective Gas Sensing Characteristics of 2D α-MoO3-x via a Facile Transfer Process.

Metal oxide-based gas sensor technology is promising due to their practical applications in toxic and hazardous gas detection. Orthorhombic α-MoO3 is a planar metal oxide with a unique layered structure, which can be obtained in a two-dimensional (2D) form. In the 2D form, the larger surface area-to-volume ratio of the material facilitates significantly higher interaction with gas molecules while exhibiting exceptional transport properties. The presence of oxygen vacancies results in nonstoichiometric MoO3 (MoO3-x), which further enhances the charge carrier mobility. Here, we study dual gas sensing characteristics and mechanism of 2D α-MoO3-x. Herein, conductometric dual gas sensors based on chemical vapor deposited 2D α-MoO3-x are developed and demonstrated. A facile transfer process is established to integrate the material into any arbitrary substrate. The sensors show high selectivity toward NO2 and H2S gases with response and recovery rates of 295.0 and 276.0 kΩ/s toward NO2 and 28.5 and 48.0 kΩ/s toward H2S, respectively. These gas sensors also show excellent cyclic endurance with a variation in ΔR ∼ 112 ± 1.64 and 19.5 ± 1.13 MΩ for NO2 and H2S, respectively. As such, this work presents the viability of planar 2D α-MoO3-x as a dual selective gas sensor.

Comments on the article “Calculation of the electric potential and surface oxygen ion density for planar and spherical metal oxide grains by numerical solution of the Poisson equation coupled with Boltzmann and Fermi-Dirac statistics” (Sensors and Actuators B: Chemical, 293 (2019) 31–40)

The article by Barami, and Ghafarinia (Sensors and Actuators B: Chemical, 293 (2019) 31–40) considers the electric potential and surface oxygen ion density in metal oxide grains. However the problem was solved using the wrong assumptions. Specifically, the density of ionized (positively charged) donors along the nanoparticle radius was assumed to be constant, equal to the density in the massive semiconductor, and the concentration of negatively charged oxygen ions on the surface of the nanoparticle was chosen arbitrarily. The implication of the assumptions are discussed and suggestions are made for the correct approach.

Calculation of the electric potential and surface oxygen ion density for planar and spherical metal oxide grains by numerical solution of the Poisson equation coupled with Boltzmann and Fermi-Dirac statistics

Chemiresistive metal oxides are widely used in the fabrication of gas sensors. The theory of gas sensitivity of metal oxide sensors has been developed based on the gas-solid interactions on the metal oxide surface. These interactions led to a charge transfer that is well described by the Poisson-Boltzmann equation. The receptor function of metal oxides can be modeled based on this differential equation. Here, the precise results of numerical solution of the Poisson equation coupled with Fermi-Dirac statistics and its approximated version that is the Poisson-Boltzmann equation is calculated to find the exact spatial variation of the electrical potential inside the metal oxide grain. The results are utilized to derive characteristic curves that relate surface oxygen ion density to the surface electrical potential and near surface electron density. The effects of grain size, grain shape and doping level on the results are also studied. It is shown that approximated solutions are only valid in limited range of conditions and the numerical solution should be used when a valid receptor function is sought.

Reversible resistive switching behaviour in CVD grown, large area MoOx.

Non-volatile resistive memory devices are theorized to be the most promising pathway towards analog memory and neuromorphic computing. Two-dimensional MoO3 is a versatile planar transition metal oxide, whose properties can be readily tuned, making it anywhere from a wide bandgap semiconductor to a semi-metal. Successful integration of such a planar metal oxide into resistive memory can enable adaptive and low power memory applications. Here, we investigate the non-volatile and reversible resistive switching behaviour of oxygen deficient MoOx in a cross-point metal/insulator/metal (MIM) architecture. Layered MoOx films are synthesised using chemical vapour deposition (CVD) and reveal excellent resistive switching performance with relatively low electroforming and operating voltages. Switching ratios of ∼103 and stable data retention of >104 s are achieved. As such, this work demonstrates the viability of MoOx as a resistive memory element and paves the way for future two-dimensional resistive memory technologies.

High performance multi-finger MOSFET on SOI for RF amplifiers

In this paper, we propose structural modifications in the conventional planar metal–oxide–semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

Nanoscale shaping and focusing of visible light in planar metal–oxide–silicon waveguides

Focusing light at the nanoscale has become a key factor in super-resolution applications. Dynamic control of this focusing can open new avenues in nanoelectronics and bioimaging, but it requires a platform that merges electronics with super-resolution capabilities. We present a planar metal–oxide–silicon (MOS) platform that allows us to shape, tune, and focus visible light at the nanoscale by compressing the wavelength of light fourfold, resulting in a scaled diffraction limit of 65 nm. We exemplify the control and flexibility by demonstrating nanovortex beams and short-wavelength super-oscillations of light that further enhance resolution toward 35 nm. Our platform achieves focusing strength similar to nanoantennas but without structural hotspots; hence it is possible to scan the focus via optical wavefront-shaping techniques. Super-resolution scanning without mechanical translations in a MOS platform can provide a building block for bioimaging, nanolithography, and lab-on-a-chip applications.