Abstract

The conventional method of calculating the effective oxide thickness (EOT) of planar metal oxide semiconductor field-effect transistor (MOSFET) holds invalid for nonplanar devices such as gate-all-around (GAA) MOSFETs and trigate MOSFETs. In this work, a unified model for the gate insulator capacitance of various cross sections (either deliberate or process-induced) of GAA MOSFETs and trigate MOSFETs have been obtained using an approximate model of metal-insulator-metal (MIM) capacitors. We have identified four geometrical parameters of the device [Fin top width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W}_{\text {top}}$ </tex-math></inline-formula> ), Fin height ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${H}_{\text {Fin}}$ </tex-math></inline-formula> ), the normalized radius of curvature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${r}$ </tex-math></inline-formula> ), and inclination angle ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\theta $ </tex-math></inline-formula> )], varying which multiple cross sections of GAA and trigate MOSFET are obtained. Through semi-analytical approach, we have improved the existing insulator capacitance models for square and rectangular cross sections GAA to include process-induced inclined sidewalls and rounded corners in a unified expression, valid for elliptical, trapezoidal, and triangular cross sections as well. In addition, by following the same approach, we have also formulated a unified semi-analytical model for insulator capacitance of trigate MOSFETs, valid for all the above-mentioned cross sections. The proposed model has been verified to accurately reproduce the electron density for a wide range of device dimensions and applied biases.

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