Planar Metal-oxide-semiconductor Field-effect Transistors Research Articles

Advantages, manufacturing processes and challenges of FinFET technology

Abstract As an emerging cutting-edge integrated circuit technology, Fin Field Effect Transistor (FinFET) has not only successfully broken through the limitations of the 22nm node since its development in 1998, but it still maintains considerable vitality and is developing into smaller sizes. As an improvement over traditional MOSFET technology, FinFET offers many technical advantages, which practically solve the challenges encountered by traditional MOSFET. The FinFET process technology is incompatible with planar MOSFET process technology. Moreover, since the development of Finfet technology, there have been many technical challenges. The first half of this article mainly introduces the differences and advantages between FinFET and traditional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), and briefly outlines its manufacturing process. The second half explains the challenges and hopes on the development path of FinFET technology. I believe this article can provide a reference for integrated circuit designers when understanding FinFET technology, and provide guidance and reference for beginners.

The correlation of the drain-source capacitance variation and the P-pillar structures in a 4H-SiC quasi super junction MOSFET

In order to improve the trade-off between the 4H-SiC planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and super junction MOSFET (SJ-MOSFET), particularly on the drain to source capacitance (Cds) which affects the switching performance, this study investigates the Cds of the quasi SJ-MOSFETs with various P-pillar widths, depths, and concentrations. The measured results show (1) when the N-type region between the P-pillars (Epi-1 region) is fully depleted, the Cds value abruptly drops, (2) when the N-type drift region beneath the P-pillar (Epi-2 region) is fully depleted, the slope of the Cds-Vds curve slowly changes because of the small extension of the depletion region in the P-type region. This is because the wider P-pillar width will increase the magnitude of the abrupt drop of the Cds and make the drop occur earlier; the abrupt drop of the Cds will occur later and the magnitude increases when the P-pillar depth is deeper due to the larger P-type region; Moreover, increasing the P-pillar concentration not only initiates the abrupt drop earlier and increases the magnitude, but also increases the minimum saturation value of the Cds at a higher reverse bias. This study also reveals that the mechanism of the Cds formation in a quasi SJ-MOSFET is different from the planar MOSFET and SJ-MOSFET. Finally, the simulated results are used to validate the influence of the P-pillar structures on the Cds – Vds curves in a quasi SJ-MOSFET.

The Effects of a Gate Bias Condition on 1.2 kV SiC MOSFETs during Irradiating Gamma-Radiation.

We investigated the effects of gate bias regarding the degradation of electrical characteristics during gamma irradiation. Moreover, we observed the punch through failure of 1.2 kV rated commercial Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) due to the influence of gate bias. In addition, the threshold voltage (VT) and on-resistance (Ron) of the SiC MOSFETs decreased significantly by the influence of gate bias during gamma irradiation. We extracted the concentration of carriers and fixed charge (QF) in oxide using N-type SiC MOS capacitors and Transmission Line Measurement (TLM) patterns to analyze the effects of gamma irradiation. The Total Ionizing Dose (TID) effect caused by high-energy gamma-ray irradiation resulted in an increase in the concentration of holes and QF in both SiC and oxide. To analyze the phenomenon for increment of hole concentration in the device under gate bias, we extracted the subthreshold swing of SiC MOSFETs and verified the origin of TID effects accelerated by the gate bias. The QF and doping concentration of p-well values extracted from the experiments were used in TCAD simulations (version 2022.03) of the planar SiC MOSFET. As a result of analyzing the energy band diagram at the channel region of 1.2 kV SiC MOSFETs, it was verified that punch-through can occur in 1.2 kV SiC MOSFETs when the gate bias is applied, as the TID effect is accelerated by the gate bias.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Mechanisms of negative bias instability of commercial SiC MOSFETs observed by current transients

This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results reveal that near-interface traps (NITs) with energy levels aligned to the valence band trap holes from the valence band by tunneling, which is different from published results about NITs with energy levels aligned to the energy gap. The impact of the aluminium implantation process of the p-type region on hole trapping is also demonstrated. The presented analysis also reveals that the hole trapping by NITs is limited to the p-type region, indicating that the aluminium implantation process is responsible for the detected NITs.

Review of the Nanoscale FinFET Device for the Applications in Nano-regime

Background:The insatiable need for low-power and high-performance integrated circuit (IC) results in the development of alternative options for metal oxide semiconductor field effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of transistors whose size must be scaled while increasing performance. As the size of the transistor shrinks for the new technology node, the control of the gate over the channel also reduces, leading to sub-threshold leakage. The non-planar technology is the potential methodology to design the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the most valuable non-planar technology. High sub-threshold slope, better short channel effect (SCE) control, high current drive strength, low dopant-prompted variations, and decreased power dissipation are the prominent features of FinFET technology.Objective:FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore, in this review paper, the different geometrical structures, working operations, design challenges, future aspects, and the different configurations of FinFETs are presented. The performance of the different configurations of a 1-bit full adder is evaluated and compared.Methods:An overview of FinFET evolution from the planar MOSFET, along with its architecture supported by the requisite equations, is presented in the paper. Besides this, it also gives an insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT) variations, width quantization, design challenges, and the future of FinFETs. A comparative study of FinFET-based 1-bit full adder using various techniques is done to compute and compare the leakage power, delay, and power delay product (PDP).Results:The full adders using FinFETs show less leakage power and PDP. The AND-OR logicbased hybrid full adder using FinFETs shows the least energy consumption per switching. Fin- FET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to the full adder using MOSFET technology. The low power FinFET-based full adder shows a 54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results signify the effect of multi-gates in curbing the leakage power dissipation.Conclusion:MOSFET faces the practical challenge of device scaling and SCEs at lower technology nodes. It initiates the multi-gate technology for future system generation. FinFET has the capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The geometrical structure of FinFET plays a key role to improve the performance metrics in an ultrananoscale regime.

Temperature dependent characteristics of β -Ga2O3 FinFETs by MacEtch

Understanding the thermal stability and degradation mechanism of β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) is crucial for their high-power electronics applications. This work examines the high temperature performance of the junctionless lateral β-Ga2O3 FinFET grown on a native β-Ga2O3 substrate, fabricated by metal-assisted chemical etching with Al2O3 gate oxide and Ti/Au gate metal. The thermal exposure effect on threshold voltage (Vth), subthreshold swing (SS), hysteresis, and specific on-resistance (Ron,sp), as a function of temperature up to 298 °C, is measured and analyzed. SS and Ron,sp increased with increasing temperatures, similar to the planar MOSFETs, while a more severe negative shift of Vth was observed for the high aspect-ratio FinFETs here. Despite employing a much thicker epilayer (∼2 μm) for the channel, the high temperature performance of Ion/Ioff ratios and SS of the FinFET in this work remains comparable to that of the planar β-Ga2O3 MOSFETs reported using epilayers ∼10–30× thinner. This work paves the way for further investigation into the stability and promise of β-Ga2O3 FinFETs compared to their planar counterparts.

Comparison of Gamma Irradiation Effects on Short Circuit Characteristics of SiC MOSFET Power Devices between Planar and Trench Structures

The short circuit withstand energy (SCWE) variations, and short circuit withstand time (SCWT) variations, of planar and trench silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices are studied after exposure to a total ionizing dose (TID). The results for ON bias are explored. The SCWE and SCWT are studied for planar and trench SiC MOSFET power devices tested for TID with gamma irradiation. A higher degradation phenomenon for the SCWE and SCWT are observed for the planar SiC MOSFET. The physical mechanisms for these variations are analyzed and confirmed by technology computer-aided design (TCAD) simulation.

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.

A Figure of Merit for Selection of the Best Family of SiC Power MOSFETs

This paper proposes a criterion to select the best family of commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) that provides the highest quality and reliability. Applying a recently published integrated-charge method, a newly proposed figure of merit is correlated to the density of near-interface traps that degrade the quality and reliability of SiC MOSFETs. The applicability of the proposed figure of merit is experimentally demonstrated with the most widely used and commercially available planar and trench MOSFETs from different manufacturers.

Attainment of low subthreshold slope in planar inversion-channel InGaAs MOSFET with in situ deposited Al2O3/Y2O3 as a gate dielectric

We have demonstrated a record low 85 mV dec−1 subthreshold slope (SS) at 300 K among the planar inversion-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). Our MOSFETs using in situ deposited Al2O3/Y2O3 as a gate dielectric were fabricated with a self-aligned inversion-channel gate-first process. The temperature-dependent transfer characteristics showed a linear reduction of SS versus temperature, with the attainment of an SS of 22 mV dec−1 at 77 K; the value is comparable to that of the state-of-the-art InGaAs FinFET. The slope factor of SS with temperature (m) is 1.33, which is lower than those reported in the planar InGaAs MOSFETs.

Ballistic transport in sub-10 nm monolayer planar GaN transistors for high-performance and low-power applications

With the constant scaling down of transistors, “More Moore” has put forward requirements for channel materials. Two-dimensional materials are considered as potential next-generation channel materials due to their unique physical properties. Herein, we study the ballistic transport characteristics of sub-10 nm monolayer (ML) planar GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) based on density functional theory and the non-equilibrium Green's function method. The calculation results indicate that n-type ML planar GaN MOSFETs with gate lengths not less than 5 nm exhibit excellent subthreshold characteristics, fast switching speeds, and low switching energies, and the corresponding parameters (off-current, on-current, delay time, and power-delay product) can simultaneously meet the requirements of the International Roadmap for Devices and Systems for the 2028 horizon for high-performance and low-power applications. Therefore, ML planar GaN is predicted to be a reliable next-generation channel material to extend Moore's law.

Thickness Modeling of Short-Channel Cylindrical Surrounding Double- Gate MOSFET at Strong Inversion Using Depletion Depth Analysis

Aims: The semiconductor technology has a great impact on consistent growth in the Very-Large- Scale Integrated (VLSI) devices. The transistor size has been scaled down from micron to submicron and towards the nanometer regime in the past 30 years due to technological advancements. The most reliable solid-state device is Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) but this rapid decrease in the device dimensions with the advent of Moore's law follows several problems, such as Short Channel Effects (SCE's) and Hot Carrier Effects. The channel becomes too small at short channel effects that necessitate the analysis of the optimum device designs, in particular in the operating conditions. The charge-sheet model that can quickly analyze a long-channel device, currently in the subthreshold to saturation regime without any discontinuity, turns out to be inappropriate at reduced channel size. Objectives: At the nano-scaling of the device, since the accumulation layer thickness is comparable to the device, the assumption of the channel as a thin sheet of charge vanishes. Though the depletion layers or zone are the regions of the absentia of charges mostly, the existence affects the device behavior and the channel thickness. Therefore, channel thickness modeling becomes essential at various bias conditions to define the specifics of device operation and the channel dependence of the structural parameters. In this work, the objective is to develop an analytical model and numerical analysis of the Cylindrical Surrounding Double-Gate (CSDG) MOSFET, including the thickness, derived based on the formation of depletion depth to analyze the device performance at reducing dimensions. Methods: The analysis is built upon the device's physical and electrical parameters, such as capacitance, electric field, thickness, threshold voltage, effective channel dimensions, drain current, are considered in this research. The depletion region in a MOSFET structure accounts for the inclusion of the source and drain depletion regions, divided primarily into three separate sub-regions as a junction between the diffused source/drain and the substrate depletion under the channel and by region induced by lateral source and drain diffusion. The condition of a planar MOSFET in channel formation, i.e., for strong inversion, and when VGS > VTH has been considered for this mathematical analysis. Results: The computed results of device thickness and depending parameters for a planar MOSFET and the CSDG MOSFET have been obtained. Based on this analysis, the silicon thickness of the typical CSDG MOSFET computed is 180 nm, 281 nm, and 327 nm at VDS 0.2 V, 0.8 V, and 1.2 V, respectively. The achieved results, through the thickness modeling proposed in this work, show that nanoscale CSDG MOSFET can be deployed for the improvements in the device performance and novel design modifications. Conclusion: The analysis presented in this work significantly contributes to understanding the dependence of semiconductor thickness in CSDG MOSFET and serves as a guide for future modifications in the structure for the device compactness.

A Study on Optimization of Planar Gate Type Metal-Oxide-Semiconductor Field-Effect-Transistors Multi Epitaxial Process in Super-Junction Structure

Power metal-oxide-semiconductor field-effect-transistors (MOSFET) is a high voltage control device that requires high reliability and efficiency and is used to improve efficiency in areas such as renewable energy generators, electric vehicles, power supply unit, converters and motor control. Electrical characteristics of the MOSFET include a Threshold voltage which is a voltage for operating the device, an On-resistance which is a device resistance in an on-state, and a breakdown voltage which means a device withstand voltage. A Super-Junction structure is proposed to design the device with a high breakdown voltage and a low on-resistance. A multi-epitaxial Super-Junction MOSFET forms a Pillar layers by injecting continuously P-type impurity at edge on stacked N-Pillar layer. By forming the Pillar region which is higher doping concentration than N-drift, the on resistance can be reduced. In the forward blocking mode, the depletion layer of the Pillar region is extended to both vertical and horizontal sides, for a high breakdown voltage can be obtained. By using a T-CAD tool which is a process simulator, electrical characteristics of 1,200 V class super-junction MOSFET are analyzed along process variables (pillar lateral length, pillar concentration). When the breakdown voltage of the super junction MOSFET and the Planar MOSFET are equal, On-resistance (based on 10 A) has a gain of approximately 20% by a difference of 0.189 ohm×cm. It is believed that this can contribute to the development of super junction MOSFET with improved reliability and electrical characteristics.

Characteristics and mechanisms of subthreshold voltage hysteresis in 4H-SiC MOSFETs* *Project supported by the National Key Research and Development Program of China (Grant No. 2017YFB0903203), the National Natural Science Foundation of China (Grant No. 62004033), and China Postdoctoral Science Foundation (Grant No. 2020M683287).

In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis (ΔV th,sub) of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), 4H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal–oxide-semiconductor (MOS) capacitors are fabricated and characterized. Compared with planar MOSFEF, the trench MOSFET shows hardly larger ΔV th,sub in wide temperature range from 25 °C to 300 °C. When operating temperature range is from 25 °C to 300 °C, the off-state negative V gs of planar and trench MOSFETs should be safely above –4 V and –2 V, respectively, to alleviate the effect of ΔV th,sub on the normal operation. With the help of P-type planar and trench MOS capacitors, it is confirmed that the obvious ΔV th,sub of 4H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level (E i) and valence band (E v). The maximum ΔV th,sub of trench MOSFET is about twelve times larger than that of planar MOSFET, owing to higher density of interface states (D it) between E i and E v. These research results will be very helpful for the application of 4H-SiC MOSFET and the improvement of ΔV th,sub of 4H-SiC MOSFET, especially in 4H-SiC trench MOSFET.

Demonstration of 1200 V/1.4 mΩ cm2 vertical GaN planar MOSFET fabricated by an all ion implantation process

We present a vertical GaN planar metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated by an all ion implantation process. The fabricated MOSFET shows an on-resistance of 2.78 mΩ cm2 and a breakdown voltage of 1200 V, by applying the short cell pitch design to reduce the on-resistance and a Mg and N sequential implantation to improve the breakdown voltage of the pn-junction. By evaluating each on-resistance component in the fabricated vertical GaN planar MOSFET using the simultaneously formed test structures, an effective on-resistance of the active region excluding the source parasitic resistance is 1.4 mΩ cm2. Consequently, it was demonstrated that an all ion implantation process can fabricate a vertical GaN planar MOSFET with a high breakdown voltage and low on-resistance. This result will greatly contribute to the realization of GaN power devices.

Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps

The random telegraph noise (RTN) in gate-all-around (GAA) silicon (Si) nanowire (NW) metal–oxide–semiconductor field-effect transistors (MOSFETs) induced by a single charge trap (SCT) or random interface traps (RITs) is studied for the first time. An experimentally validated three-dimensional quantum-mechanically-corrected device simulation is advanced to investigate the explored devices. The magnitude of the RTN decreases with increasing gate voltage to different extents for the planar MOSFET, bulk FinFET, and GAA Si NW MOSFET devices, owing to the reduction in the conducting carriers along the channel. For the GAA Si NW MOSFET, the reduction of the fluctuation of threshold voltage in the presence of RITs is about 25 and 3 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 6 and 2.6 times, respectively. For the GAA Si NW MOSFET, the reduction of the RTN in the presence of RITs is about 7.5 and 4.7 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 22 and 6 times, respectively. At given threshold voltage, compared with the results for the planar MOSFETs and bulk FinFET, the GAA Si NW MOSFET exhibits minimal characteristic variability and RTN owing to the ultimate electrostatic control of the gate from the point of view of electrostatic integrity.

Lateral Power Fin MOSFET With a High-k Passivation for Ultra-Low On-Resistance

A novel lateral power fin metal-oxide-semiconductor field-effect transistor (MOSFET) made on a silicon-on-insulator substrate is proposed. The fin silicon drift region of the proposed device is surrounded by a high-k (HK) passivation. The HK passivation enables the proposed device to realize a three-dimensional (3D) enhanced reduced-surface-field action and a 3D accumulation layer. According to the simulation results, when compared to a lateral power planar MOSFET with an HK passivation, the proposed device offers a 78% reduction in specific on-resistance at the same 100-V breakdown voltage. More comparative studies indicate that the static characteristic of the proposed device not only overcomes the silicon limit but also presents a significant advantage when compared to the prior art.

Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications

We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.

Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics

Following the downscaling road map for planar metal–oxide–semiconductor field-effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate scaling of complementary metal–oxide–semiconductor devices. Gate-all-around (nanowire) field-effect transistors have proven to be the most suitable below-22 nm technology nodes. Hence the reliability of these devices is of great concern. Negative-bias temperature instability (NBTI) and hot-carrier degradation (HCD) are the key device reliability issues that exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) under direct-current and alternating-current stress were investigated. When stressed, the NBTI behavior in SNWTs showed fast initial degradation, quick degradation saturation and then a special recovery behavior. Along with that, the effects of hot-carrier stress on n-channel SNWTs were studied. Due to the surrounded gate structure, it was observed that the effects of HCD were significant in the nanowire transistors.