Plan-view Transmission Electron Microscopy Research Articles

Defects and their reduction in Ge selective epitaxy and coalescence layer on Si with semicylindrical voids on SiO<formula> <tex>$_{2}$</tex> </formula> masks

Formation of semicylindrical voids on SiO2 masks in Ge layers selectively grown on Si has positive impacts for reduction of threading dislocation density (TDD). Semicylindrical voids are formed through selective epitaxial growth (SEG) and coalescence of SEG Ge layers. A cross-sectional transmission electron microscope (TEM) observation reveals that a threading dislocation (TD) is terminated at a semicylindrical void, resulting in the reduction of TDD. The semicylindrical voids also contribute to the suppression of two-dimensional defects generated at the coalesced interfaces between the SEG Ge layers, which were widely observed in previous reports. Plan-view TEM observations reveal that there are TDs inclined to be parallel to the semicylindrical voids, and plan-view TEM observations show a large (4 μm × 4 μm) TD-free area in the Ge layer with the semicylindrical voids.

Intrinsic microstructure of Si/GaAs heterointerfaces fabricated by surface-activated bonding at room temperature

The intrinsic microstructure of Si/GaAs heterointerfaces fabricated by surface-activated bonding at room temperature is examined by plane-view transmission electron microscopy (TEM) and cross-sectional scanning TEM using damage-free TEM specimens prepared only by mechanochemical etching. The bonded heterointerfaces include an As-deficient crystalline GaAs layer with a thickness of less than 1 nm and an amorphous Si layer with a thickness of approximately 3 nm, introduced by the irradiation of an Ar atom beam for surface activation before bonding. It is speculated that the interface resistance mainly originates from the As-deficient defects in the former layer.

Low threading dislocation density aluminum nitride on silicon carbide through the use of reduced temperature interlayers

In this work, reduced threading dislocation density AlN on (0001) 6H-SiC was realized through the use of reduced temperature AlN interlayers in the metalorganic chemical vapor deposition growth. We explored the dependence of the interlayer growth temperature on the AlN crystal quality, defect density, and surface morphology. The crystal quality was characterized using omega rocking curve scans and the threading dislocation density was determined by plan view transmission electron microscopy. The growth resulted in a threading dislocation density of 7 × 108 cm−2 indicating a significant reduction in the defect density of AlN in comparison to direct growth of AlN on SiC (∼1010 cm−2). Atomic force microscopy images demonstrated a clear step-terrace morphology that is consistent with step flow growth at high temperature. Reducing the interlayer growth temperature increased the TD inclination and thus enhanced TD-TD interactions. The TDD was decreased via fusion and annihilation reactions.

Control wafer bow of InGaP on 200 mm Si by strain engineering

When epitaxially growing III–V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III–V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III–V semiconductors on large size Si substrates.

Effect of composition in Si1−xGex seed layer on the solid phase crystallization of ultrathin amorphous silicon layer

The effect of top silicon-germanium (Si1−xGex) layers on the crystallization of underlying amorphous Si (a-Si) films was investigated for various Ge compositions in Si1−xGex. Si and Si1−xGex films were sequentially deposited on thermal SiO2 by using SiH4 and GeH4 source gases in reduced pressure chemical vapor deposition. The fraction and the microstructure of underlying crystallized Si were characterized by plan-view transmission electron microscopy. Scanning nanobeam diffraction was performed to investigate the grain size of crystallized Si films. The crystallization of the underlying a-Si thin film in a-Si1−xGex/Si bilayer stack gradually increased with the increasing Ge composition of the top Si1−xGex layer. The grain size of underlying crystallized Si films showed a dependence on the Ge composition of top Si1−xGex. For Si1−xGex with 22% Ge, microtwins were observed to be the dominant defect, while stacking faults were dominant for Si1−xGex with 47% Ge. The Ge composition and the thickness of Si1−xGex are important factors to obtain the optimized crystallization time and grain size of ultrathin a-Si with a reduced density of intragrain defects.

Effects of Buffer Layer Growth Temperature on Micro-Structures in the Cubic GaN Films Grown on GaAs (001) Substrates by MOVPE

c-GaN films on GaAs (001) substrates were investigated using TEM to verify effects of buffer layer growth temperature on micro-structures. Growth temperature of the GaN buffer layer was varied in a range of 550 to 600°C and GaN film was grown at high temperature (∼900°C). For GaN buffer layer at 550°C, the plan-view TEM micrographs of c-GaN films show high density of stacking faults (SFs) and dislocations. At the GaN/GaAs interface, the electron diffraction (ED) pattern demonstrated different type of single diffraction spots which include the high intensity of streaking. This results indicated that the high density of SFs become dense into hexagonal phase single crystal. For 575°C GaN buffer layer, the wide SFs are observed that these broad lines are not expanding to the GaN surface and the dislocations are less found than the other temperature. Moreover, cross-sectional TEM micrographs and the ED pattern at interface show pyramid like structure and less intensity of the steak lines, respectively. There are no diffraction spots related to hexagonal structure. For 600°C GaN buffer layer, there are the steaking of diffraction spots which represent hexagonal phase inclusions at interface. V-shape voids defects are penetrating in the GaAs surface which were caused the thermal decomposition of As. Our results indicated that, the high quality of GaN film with cubic phase purity grown on GaAs (001) are achieved from the optimum growth temperature GaN buffer layer of 575°C.

Structural analysis of double-layer Shockley stacking faults formed in heavily-nitrogen-doped 4H-SiC during annealing

We investigated the structures and expansion behavior of double-Shockley stacking faults (DSFs) formed in heavily nitrogen-doped 4H-SiC during annealing. Heavily doped epilayers prepared as specimens were successively annealed. Various types of DSFs showing different shapes and dislocation contrasts were found in photoluminescence and synchrotron X-ray topography images. Taking account of every possible stacking sequence forming DSFs, the structures of various types of DSFs were determined from observations by plan-view transmission electron microscopy (TEM) and cross-sectional high-angle annular dark-field scanning TEM. We found that a bounding dislocation enclosing a DSF splits into two partial dislocations (PDs), and their Burgers vectors are identical, while the distance of the two PDs depended on their core structures (30° Si-, 30° C- or 90° C-core). We also discussed the contrast rule for the dislocation consisting of two PDs in the synchrotron X-ray topography images and the mobile PDs for the DSF expansion in the epilayers with different nitrogen concentrations.

A Plan-view TEM Specimen Preparation Method Using Focused Ion Beam

A Plan-view TEM Specimen Preparation Method Using Focused Ion Beam

Strain relaxation induced surface morphology of heterogeneous GaInNAs layers grown on GaAs substrate

The partially-relaxed heterogeneous GaInNAs layers grown on GaAs substrate by atmospheric pressure vapor phase epitaxy (AP-MOVPE) were investigated by transmission electron microscopy (TEM) and atomic force microscopy (AFM). The planar-view TEM image shows a regular 2D network of misfit dislocations oriented in two orthogonal 〈110〉 crystallographic directions at the (001) layer interface. Moreover, the cross-sectional view TEM image reveals InAs-rich and V-shaped precipitates in the near surface region of the GaInNAs epitaxial layer. The resultant undulating surface morphology, known as a cross-hatch pattern, is formed as observed by AFM. The numerical analysis of the AFM image of the GaInNAs layer surface with the well-defined cross-hatch morphology enabled us to determine a lower bound of actual density of misfit dislocations. However, a close correspondence between the asymmetric distribution of interfacial misfit dislocations and undulating surface morphology is observed.

Elimination and Quantification of Oxidation Induced Interstitial Injection via Ge Implants

The presence of Silicon-Germanium (SiGe) alloys at the Si/SiO2 interface during an oxidation is known to suppress the injection of silicon self interstitials that normally accompanies silicon oxidation and leads to observed effects such as Oxidation Enhanced Diffusion (OED) and stacking fault growth. To measure interstitial injection, a layer of implantation induced dislocation loops was introduced and the interstitial fluxes measured via quantitative plan-view TEM. Germanium was introduced via a second implant at 3keV over a range of doses between 1.7 x1014 cm-2 and 1.4 x1015 cm-2. We show that partial suppression can be observed for sub-monolayer quantities of germanium, and that more than three monolayers of SiGe are necessary to suppress interstitial injection below the detection limit during oxidation. This study shows that low energy implantation of germanium can be used to eliminate or modulate injection of interstitials. Additional results suggest the mechanism is related to stopping interstitial formation, not migration. Figure 1

Atomic structure and electronic properties of MgO grain boundaries in tunnelling magnetoresistive devices

Polycrystalline metal oxides find diverse applications in areas such as nanoelectronics, photovoltaics and catalysis. Although grain boundary defects are ubiquitous their structure and electronic properties are very poorly understood since it is extremely challenging to probe the structure of buried interfaces directly. In this paper we combine novel plan-view high-resolution transmission electron microscopy and first principles calculations to provide atomic level understanding of the structure and properties of grain boundaries in the barrier layer of a magnetic tunnel junction. We show that the highly [001] textured MgO films contain numerous tilt grain boundaries. First principles calculations reveal how these grain boundaries are associated with locally reduced band gaps (by up to 3 eV). Using a simple model we show how shunting a proportion of the tunnelling current through grain boundaries imposes limits on the maximum magnetoresistance that can be achieved in devices.

Role of oxygen in wetting of copper nanoparticles on silicon surfaces at elevated temperature.

Copper nanoparticles have been deposited on silicon surfaces by a simple galvanic displacement reaction, and rapid thermal annealing has been performed under various atmospheric conditions. In spite of the general tendency of the agglomeration of nanoparticles to lower the surface energy at elevated temperatures, our plan-view and cross-sectional transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (EDX) and X-ray diffraction (XRD) analysis shows that the thermal oxidation of the copper nanoparticles and formation of cupric oxide (CuO) on silicon surfaces leads to wetting rather than agglomeration. In contrast, agglomeration has been observed when copper nanoparticles were annealed in a nitrogen environment. The lattice transformation from cubic Cu to monoclinic CuO, and hence the change in surface energy of the particles, assists the wetting process. The occurrence of wetting during the oxidation step implies a strong interaction between the oxidized film and the silicon surface.

Use of a buried loop layer as a detector of interstitial flux during oxidation of SiGe heterostructures

The injection of interstitials from oxidation of Si and SiGe has been investigated quantitatively using transmission electron microscope (TEM) to monitor the growth of a layer of implantation induced dislocation loops. The layer of loops was introduced via a 50 keV P implant at a dose of 2 × 1014/cm2 followed by annealing at 750 °C. Subsequently, silicon–germanium containing heterostructures, consisting of a 5 nm silicon cap on top of either a 20 nm Si0.7Ge0.3 layer or 25 nm Si layer were grown on the implanted wafers. The wafers were then oxidized, and the trapped interstitials in the dislocation loops were determined via quantitative plan view TEM. It is shown that the SiGe layer and the inherent epitaxial interfaces are fully transparent to a flux of interstitials arising from the oxidizing interface. As expected, oxidation of the Si control and Si on SiGe result in strong interstitial injection. However, for the latter sample, as the oxidation front proceeds into the SiGe layer, interstitial injection is reduced and eventually halts as the Ge accumulates at the oxidizing SiGe interface. At 900 °C after 2 h in dry O2, the oxidizing interface injects 3 × 1014/cm2 of interstitials and this value drops to below 1 × 1013/cm2 after oxidation of SiGe. These finding are consistent with the concept that the presence of Ge decreases the strain at the interface, reducing interstitial injection.

Novel method for measurement of transistor gate length using energy-filtered transmission electron microscopy

As the feature size of devices continues to decrease, transmission electron microscopy (TEM) is becoming indispensable for measuring the critical dimension (CD) of structures. Semiconductors consist primarily of silicon-based materials such as silicon, silicon dioxide, and silicon nitride, and the electrons transmitted through a plan-view TEM sample provide diverse information about various overlapped silicon-based materials. This information is exceedingly complex, which makes it difficult to clarify the boundary to be measured. Therefore, we propose a simple measurement method using energy-filtered TEM (EF-TEM). A precise and effective measurement condition was obtained by determining the maximum value of the integrated area ratio of the electron energy loss spectrum at the boundary to be measured. This method employs an adjustable slit allowing only electrons with a certain energy range to pass. EF-TEM imaging showed a sharp transition at the boundary when the energy-filter’s passband centre was set at 90 eV, with a slit width of 40 eV. This was the optimum condition for the CD measurement of silicon-based materials involving silicon nitride. Electron energy loss spectroscopy (EELS) and EF-TEM images were used to verify this method, which makes it possible to measure the transistor gate length in a dynamic random access memory manufactured using 35 nm process technology. This method can be adapted to measure the CD of other non-silicon-based materials using the EELS area ratio of the boundary materials.

Characterization of Basal Plane Dislocations in PVT-Grown SiC by Transmission Electron Microscopy

4H- and 6H-SiC grown by physical vapor transport method were investigated by transmission electron microscopy (TEM). From the TEM diffraction patterns observed along the [11-20] zone axis, 4H- and 6H-SiC were identified due to their additional diffraction spots, indicating atomic stacking sequences. However, identification was not possible in the [10-10] zone axis due to the absence of additional diffraction spots. Basal plane dislocations (BPDs) were investigated in the TEM specimen prepared along the [10-10] zone axis using the two-beam technique. BPDs were two Shockley partial dislocations with a stacking fault (SF) between them. Shockley partial BPDs arrayed along the [0001] growth direction were observed in the investigated 4H-SiC. This arrayed configuration of Shockley partial BPDs cannot be recognized from the plan view TEM with the [0001] zone axis. The evaluated distances between the two Shockley partial dislocations for the investigated samples were similar to the equilibrium distance, with values of several hundreds of nanometers or even values as large as over a few micrometers.

Investigation of Surface Defects in AlInSb Metamorphic Buffer (MB) Grown on GaSb

We have conducted an investigation of the different surface defects observed on InAlSb metamorphic buffers grown on GaSb. There are two different defect modes found in this system: crystallographic surface features and surface cross-hatching. We have characterized both defect modes using optical microscopy, scanning electron microscopy, and plan-view and cross-sectional transmission electron microscopy. It is found that particulates from polishing slurry or incomplete oxide desorption on the substrate before the growth are the root of the crystallographic defects. Surface crosshatching is shown to be caused by the coalescence of strained islands formed at the onset of buffer layer growth. Despite the presence of these defects, we have shown that substantial areas of the surface are defect-free and can be effectively used for realizing devices on this platform. Threading dislocation and crystallographic defect densities are found to be ∼1 × 107/cm2 and ∼5 × 104/cm2, respectively.

Influence of MgO underlayers on the structure and magnetic properties of FePt-C nanogranular films for heat-assisted magnetic recording media

In order to optimize the nanogranular structure of FePt-C for heat-assisted magnetic recording media, we investigated the influence of MgO underlayers on the growth of FePt grains in the FePt-C layer. The FePt-C layer was deposited by using the alternating sputtering method, by which FePt and FePt-C layers were alternately deposited. To understand the growth mechanism of the FePt-C layer on the MgO underlayers deposited under various conditions, detailed plan-view and cross sectional transmission electron microscopy observations were made for different film thicknesses. We found that columnar FePt grains grow only when the deposition conditions of the MgO underlayer are optimal. Direct TEM observation of the growth process of the FePt-C layer revealed that the number density of nuclei is sufficient in the initial stage of the film deposition; however, coarsening of the grains after grain impingement causes a substantial decrease in the number density of the FePt grains.

Strain Relaxed Silicon Germanium Buffer Layers: From Growth to Integration Challenges

Silicon germanium (SiGe) strain relaxed buffers (SRB) have been an active area of investigation both in academia as well as the semiconductor industry for a number of years [1, 2]. These relaxed epitaxial layers act as virtual substrates or templates for subsequent growth of tensile or compressively strained layers that can serve as N and PMOS channels for continued scaling of Si CMOS technology. The most well established methodology, proposed by Fitzgerald et al. [1], for growing SiGe SRB’s is by grading the Ge concentration throughout the layer, typically 2-3 µm thick, which leads to the creation of a series of low lattice mismatched interfaces. By managing the lattice mismatch using this grading method the threading dislocation density (TDD) can be reduced significantly. In the work reported here, we have studied thick graded SRB layers from a holistic perspective that involves growth, defect density optimization followed by the growth of strained Si/SiGe layers on these virtual substrates. The focus during this study was on the high temperature growth regime (> 900 oC) which helps reduce TDD due to the higher dislocation velocity resulting in a higher number of dislocation annihilation events. Depicted in Fig. 1 is one such example, where a 2 µm graded layer (0-20 % Ge grading) was grown followed by a 1 µm layer at 20 % Ge analyzed using SIMS. The growth for this sample was carried out using Dichlorosilane (SiH2Cl2 or DCS) and Germane (GeH4) at 900 oC and 80 Torr under H2 ambient in an Applied Materials CenturaTM RP Epi reactor. From a morphology perspective these films are extremely rough after growth due to the well-known cross hatch pattern formation as shown in the AFM scan in Fig. 2 (a). In order to enable growth of strained and atomically smooth channel layers on top of this SRB, a chemical-mechanical planarization (CMP) step is required to remove the cross-hatch and leave behind a much smoother template. As shown in Fig. 2(b), Applied Materials ReflexionTM LK CMP tool was able to polish these substrates down to an RMS roughness of ~ 1.3 Å, compared to a starting RMS roughness of ~ 66 Å, after ~ 0.2 µm removal of the 20 % Ge constant composition layer. To characterize the TDD for this layer, plan view transmission electron microscopy (PV-TEM) was performed and the results are shown in Fig. 3. As seen in this case, 2 threading dislocations are visible in a 100 µm2 area which translates to a TDD of ~ 2 x 10 6 /cm2. PV-TEM however, has limited resolution and led us to explore large area defect etching utilizing vapor phase hydrochloric acid (HCl) in the epi reactor itself [3]. HCl based defect etching was done on SRB samples grown at various temperatures in the 900 – 1100 oC range after they had gone through CMP. The resulting etch pits, which in essence are highlighted threading dislocations, were inspected optically on a 300 µm2 area as shown in Table 1 where 1100 oC growth resulted in the lowest TDD ~ 5 x 10 4 /cm2. For temperatures greater than 1000 oC, GeCl4 was used instead of GeH4 in order to keep the process chamber walls clean. Another critical aspect of SRB integration is the growth of strained Si or SiGe layers on top of this relaxed layer. These strained layers serve as the channel material for N or PMOS transistors. Figure 4 represents one such illustration in the form of a cross-section TEM where we have grown a Si layer under tensile strain, 436 Å in thickness, on a 30 % Ge graded SRB layer post CMP. This Si layer appears to be defect free, and based on the (224) reciprocal space map (RSM: In Fig. 5) acquired using X-ray diffraction techniques, it is < 5 % relaxed with respect to the underlying SRB. A systematic optimization of epi pre-clean and H2 pre-bake had to be performed to achieve defect free Si or SiGe (~ 60-70 % Ge) growth on SRB templates. In summary, we have explored the growth and integration of SiGe SRB layers in order to enable scaling for future generation CMOS technology beyond 7 nm. Higher growth temperatures (> 1000 oC) were effective in improving the TDD by almost two orders of magnitude. Pseudomorphically strained N and P channel growth on SiGe SRB has also been achieved by optimizing the pre-clean and prebake conditions.

Investigation of the Low Temperature / High Temperature Approach to Produce Si0.5Ge0.5 and Pure Ge Strain Relaxed Buffers

Several microns thick, constant composition SiGe layers (with Ge contents typically in the 20% to 50% range) grown directly on Si(001), with sometimes thick Ge layers on top, are coming back in force as the core materials of mid and long infra-red waveguides. The impact of growth parameters and thickness on surface roughness, degree of strain relaxation and threading dislocations density (TDD) are not that well known, however. SiGe Virtual Substrates (VS), with several microns thick SiGe graded layers capped by constant composition layers or pure Ge grown directly on Si(001) are indeed preferentially used as templates for sSi layers, donors for GeOI fabrication or active media in near IR photo-detectors. We have thus explored whether or not the Low Temperature / High Temperature (LT/HT) approach (+ Thermal Cycling) used for pure Ge growth on Si yielded high quality Si0.5Ge0.5 Strain-Relaxed Buffers (SRBs) that could serve afterwards as templates for thick Ge layers. To that end, we have grown various thickness Si0.48Ge0.52 layers at 550°C, 20 Torr and with a SiH4 + GeH4 chemistry, in order to have a satisfying Growth Rate (GR = 48 nm min.-1) at such a low temperature. As soon as those layers were relaxed (88% for 380 nm), the growth temperature was increased to 850°C and Si0.50Ge0.50 layers grown on top thanks to SiH2Cl2 + GeH4 (GR = 151 nm min.-1at 20 Torr). As soon as the 1.7 µm thick Si0.5Ge0.5 SRBs were completed, a 3 x (850°C, 10s / 975°C, 10s) TC was used to minimize defect density. Then, the growth temperature was reduced to 400°C and 130 nm of pure Ge grown at 100 Torr thanks to GeH4 (GR = 17 nm min.-1). The growth temperature was then ramped up to 750°C (and the growth pressure down to 20 Torr) and various thickness Ge layers grown on top (GR = 55 nm min.-1) until 1.3 µm was reached. Finally, another 3 x (750°C, 10s / 875°C, 10s) TC was used to minimize defect density and smoothen the surface. 20 µm x 20 µm Atomic Force Microscopy (AFM) images of the surfaces of our stacks at various stages of their completion can be found in Figure 1. Omega-2Theta scans around the (004) X-Ray Diffraction order for the same samples are provided in Figure 2, together with a (004) Reciprocal Space Map of a whole {1.7 µm thick Si0.5Ge0.5 SRB / 1.3 µm Ge} stack with the 2 aforementioned TCs. What is easily seen is that the surface of the Si0.48Ge0.52 layers is rough. The spatial wavelength of that roughness increases when the Si0.50Ge0.50 HT layer thickness increases and when a TC is used. The surface morphology definitely changes when Ge is added, first at LT then at HT. Large diameter hills are then formed and a cross-hatch appears when a TC is used. We have plotted in Figure 3 the surface root mean square roughness and the macroscopic degree of strain relaxation associated with our stacks as a function of the SiGe + Ge thickness, in order to see what is happening. We have, as soon as the Si0.48Ge0.52 layers plastically relax, a surface roughening which is not recovered by the HT growth of Si0.5Ge0.5 (rms roughness: 5 nm). Adding Ge @ LT roughens the surface even more. Thickening it with Ge @ HT and using a TC yields a slight surface roughness decrease, however (down to 3.5 nm). Those roughness values are in-between those associated with cross-hatched Si0.5Ge0.5 VS (12 nm) and pure Ge layers (1 nm). What is also noticeable is that the HT Si0.5Ge0.5and pure Ge layers are slightly tensily strained. This is due to thermal expansion coefficient differences between Si and SiGe (Ge) which come into play during the cooling-down to room temperature. We have otherwise used the Ayers theory (J. Cryst. Growth 125 (1992) 329) in order to convert the full widths at half maximum of SiGe and Ge omega scans (from XRD RSMs) into actual TDDs. We would then have, for 60° misfit dislocations in our stacks, the following values: 6.0x108 cm-2 (3.5x108 cm-2) in as-grown (annealed) 1.7 µm thick Si0.5Ge0.5 SRBs and 2.8x108 cm-2 (1.6x108 cm-2) in as-grown (annealed) 1.3 µm thick Ge layers on top. Those values are definitely higher than those in 1.4 µm thick, cyclically annealed pure Ge layers grown directly on Si (3.8x107 cm-2) and in ~ 6 µm thick Si0.5Ge0.5 VS (2x105 cm-2). Plane view and cross-sectional Transmission Electron Microscopy is underway to confirm those TDDs. Figure 1

Fault isolation at P/N junction by nanoprober

Precise location of leakage in a P-well/N-well junction has been identified by an AFM (atomic force microscope)-based nanoprober. In order to provide the accurate position of the failure for further analysis, a new method was proposed by combining nanoprobing I–V results on each P-well/N-well contact together with semi-empirical calculation to identify the possible leakage path. Further plan view TEM analysis confirms our result.