Plan-view Transmission Electron Microscopy Research Articles

Improved crystallographic order of ScAlN/GaN heterostructures grown at low temperatures under metal rich surface conditions

Sc0.18Al0.82N/GaN with state-of-the-art x-ray diffraction figures of merit grown by metal modulated epitaxy under metal-rich conditions and a low substrate temperature of 400 °C is demonstrated to have improved crystalline order [250 arc sec for the (0002) reflection and 469 arc sec for the (101¯5)] compared to a previous state-of-the-art sample grown at a more conventional temperature of 650 °C. While both samples show a columnar structure, the higher substrate temperature sample has a good symmetric rocking curve (RC) of 229 arc sec, but unlike the lower temperature sample, the RC of the (101¯5) asymmetric reflection could not be measured, indicating a more columnar structure common among ScAlN films. Local lattice constant maps (LLCMs) from 4D-STEM depict abrupt strain relaxation within ∼2 nm from the ScAlN/GaN interface for the sample grown at Tsub = 400 °C. Since these LLCMs suggest a lattice mismatch in the a-lattice constant, and since the films show a sudden roughening, the composition for lattice match to GaN may be less than the accepted 18%–20% Sc, consistent with the average GaN lattice match from lattice constant values reported in the literature of 12%. Compared to traditional III-Nitrides, ScAlN films have substantially more screw and mixed-type threading dislocations, suggesting substantial shear forces that result in significant twist and distortion leading to orthorhombic diffraction patterns as viewed from plan-view TEM in the Tsub = 650 °C sample. These results offer the possibility of ScAlN integration into low-thermal-budget processes including CMOS but further indicate that structural understanding of ScAlN remains lacking.

Atomic vs. sub-atomic layer deposition: impact of growth rate on the optical and structural properties of MoS2 and WS2

MoS2 and WS2 mono- and multilayers were grown on SiO2/Si substrates. Growth by atomic layer deposition (ALD) at fast growth rates is compared to sub-ALD, which is a slow growth rate process with only partial precursor surface coverage per cycle. A Raman spectroscopic analysis of the intensity and frequency difference of the modes reveals different stages of growth from partial to full surface layer coverage followed by layer-by-layer formation. The initial layer thickness and structural quality strongly depend on the growth rate and monolayers only form using sub-ALD. Optical activity is demonstrated by photoluminescence (PL) characterization which shows typical excitonic emission from MoS2 and WS2 monolayers. A chemical analysis confirming the stoichiometry of MoS2 is performed by x-ray photoelectron spectroscopy. The surface morphology of layers grown with different growth rates is studied by atomic force microscopy. Plan-view transmission electron microscopy analysis of MoS2 directly grown on freestanding graphene reveals the local crystalline quality of the layers, in agreement with Raman and PL results.

TEM Image Analysis and Simulation Physics for Two-Step Recrystallization of Discretely Amorphized C3H5-Molecular-Ion-Implanted Silicon Substrate Surface

In this study, we investigate the initial rapid recrystallization of a discretely amorphized C3H5-molecular-ion-implanted silicon (Si) substrate surface in the subsequent thermal annealing treatment through the analysis of plan-view transmission electron microscopy (TEM) images and technology computer-aided design (TCAD) process simulation. In the approach of the analysis of the plan-view TEM image of the Si substrate surface, we found that initial rapid recrystallization occurs in the intermediate regions between the residual crystalline and discrete amorphous regions formed in the C3H5-molecular-ion-implanted Si substrate surface. In addition, the TCAD process simulation results indicate that the intermediate regions correspond to the amorphous pockets formed around the discrete amorphous regions in the C3H5-molecular-ion-implanted Si substrate surface and are recrystallized preferentially during the short thermal annealing time. These plan-view TEM image analysis and TCAD process simulation results reveal a two-step recrystallization of the discretely amorphized C3H5-molecular-ion-implaned Si substrate surface. After the initial rapid recrystallization of amorphous pockets in the 1st step, the recrystallization of discrete amorphous regions starts in the 2nd step. The incubation period between the 1st and 2nd steps is the time required to recrystallize the amorphous pockets around the discrete amorphous regions completely and redefine the amorphous/crystalline interface.

Chemical Vapor Deposition of a Single-Crystalline MoS2 Monolayer through Anisotropic 2D Crystal Growth on Stepped Sapphire Surface.

Recently, a step-flow growth mode has been proposed to break the inherent molybdenum disulfide (MoS2) crystal domain bimodality and yield a single-crystalline MoS2 monolayer on commonly employed sapphire substrates. This work reveals an alternative growth mechanism during the metal-organic chemical vapor deposition (MOCVD) of a single-crystalline MoS2 monolayer through anisotropic 2D crystal growth. During early growth stages, the epitaxial symmetry and commensurability of sapphire terraces rather than the sapphire step inclination ultimately govern the MoS2 crystal orientation. Strikingly, as the MoS2 crystals continue to grow laterally, the sapphire steps transform the MoS2 crystal geometry into diamond-shaped domains presumably by anisotropic diffusion of ad-species and facet development. Even though these MoS2 domains nucleate on sapphire with predominantly bimodal 0 and 60° azimuthal rotation, the individual domains reach lateral dimensions of up to 200 nm before merging seamlessly into a single-crystalline MoS2 monolayer upon coalescence. Plan-view transmission electron microscopy reveals the single-crystalline nature across 50 μm by 50 μm inspection areas. As a result, the median carrier mobility of MoS2 monolayers peaks at 25 cm2 V-1 s-1 with the highest value reaching 28 cm2 V-1 s-1. This work details synthesis-structure correlations and the possibilities to tune the structure and material properties through substrate topography toward various applications in nanoelectronics, catalysis, and nanotechnology. Moreover, shape modulation through anisotropic growth phenomena on stepped surfaces can provide opportunities for nanopatterning for a wide range of materials.

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Nanosheet (NS) gate-all-around (GAA) devices have demonstrated advantages in device performance and area scaling over finFET devices [1-11]. Enablement and future scaling of GAA devices require robust etch processes for Inner Spacer (IS) and Channel Release (CR) for well-controlled device performance and yield (Fig. 1). CR requires an isotropic, complete etch of the sacrificial SiGe layer with extremely high selectivity to the spacer (Sp0), IS, and Si channels. Furthermore, during CR, the Si channels must be released simultaneously for all sheet widths (WNS) [1], which range from 20nm to 100nm, necessitating significant over-etch (OE) on the narrowest sheets. We demonstrated excellent device performance across all WNS with more than 150 % OE on the widest sheets [1]. However, this extreme OE makes the pFET source/drain (S/D) SiGe:B especially vulnerable to damage. In this paper, we explore several mechanisms that result in SiGe:B S/D damage and demonstrate how to prevent the damage with IS, CR, and S/D epitaxial optimization.The S/D Si:B and Si:P used in our high-performance test devices are not susceptible to damage during CR due to high etch selectivity [2]. Thus, SiGe:B S/D is required to evaluate the mechanisms causing S/D damage. To enable these studies, we developed high-quality S/D SiGe:B, which shows substantial device performance improvement over our baseline S/D Si:B, with 150% increase in peak mobility, 50% reduction in Vt, and 45% reduction in Ron (Fig. 2).The ability to target IS thickness allows tuning of device performance through Cov and Ron and is critical for future device scaling. In addition, the IS plays a critical role as a physical barrier to prevent S/D damage during CR [1,2]; reducing IS thickness below a critical value can result in S/D damage. The optimal IS thickness is determined by balancing maximum device performance for all WNS while maintaining S/D integrity during CR. This process window can be maximized by optimizing the CR etch process, and can be further increased by integrating an Si:B buffer in the S/D epitaxy. We have developed four CR processes with different chemistries and evaluated their process windows.We evaluated S/D damage for two CR processes versus IS thickness. We observed no S/D damage with Process A until 4nm IS thickness at 50% OE (Fig. 3a). Process C showed no damage at 4nm IS thickness, even up to 100% OE. The plan-view TEM in Fig. 3a shows that S/D damage occurs at the corners of the S/D region as well as at the center, indicating several mechanisms for S/D damage (see Fig. 4): CR etch gas permeation through the IS, exposed S/D through pinholes in the IS or at the IS edges due to rounded IS shape, and exposed S/D at the intersection of the Si/SiGe fins and gate.To isolate and characterize permeation of the CR etch gas through the IS, we deposited various thicknesses of IS on SiGe/Si multilayers (Fig. 5a), then exposed the structures to CR Process A. The SiGe layers showed no damage until the IS layer was thinned to <1nm. The difference in critical thickness for etch gas permeation on fully integrated structures compared to these test structures (4nm compared to <1nm) could be attributed to the other mechanisms.S/D damage due to IS permeation can be prevented by a better quality IS; by optimizing the CR chemistry to tune the selectivity between the sacrificial SiGe and the S/D SiGe:B (Fig. 5b); or by integrating a Si:B buffer prior to S/D SiGe:B deposition (Fig. 6). The process window then can be maximized by selecting the best CR process since selectivity to Si:B and permeation through the IS varies with the chemistry. Fig. 7 shows the improvement in the process window with a 2nm Si:B buffer on wafers with no IS for Processes A, B and C.The other S/D damage mechanisms highlighted in Fig. 4 are characterized in Fig. 3b. The S/D damage starts at the corners of the active region and the extent of damage increases with CR OE. These failure modes require changes in integration to improve the Sp0 at the fin-gate corner, reducing the IS rounding, or creating a straighter etch front across the sheet [2].S/D damage during CR is a significant issue in NS architecture. This can be mitigated by optimizing the CR etch process, incorporating an Si:B buffer layer, improving the IS quality or shape, and improved integration. Understanding these mechanisms is critical to ensure robust S/D quality with scaling for future technology nodes. Figure 1

Fine structure of the tracks of several-tens-MeV Au ions in YBa2Cu3O7-x studied by cross-sectional transmission electron microscopy

We studied the morphology of the tracks (irradiation damage) of 44, 66, and 84 MeV Au ions in YBa2Cu3O7-x (YBCO) thin films using cross-sectional transmission electron microscopy (TEM). The electronic energy loss (Se = 11.6, 16.7, and 20.1 keV/nm) ranged near the onset of ion-track formation previously determined by plan-view TEM and critical-temperature measurements (about 13 keV/nm). The morphology changed from 1D arrays of large spheres of about 5 to 10 nm diameter in 44-MeV irradiation to their elongated variant (spheroid) that were statistically pierced by thin-lines of about 1 to 2 nm and 3 to 5 nm diameter in 66 and 84 MeV, respectively. In the same series of Au-irradiated YBCO films, we observed a sudden increase in critical current density at self-field and 77 K between 44- and 55-MeV irradiation, in agreement with the appearance of the thin-line damage in TEM (between 44- and 66-MeV).

Artifact-Free Preparation of Plan View TEM Specimens and Its Application to MRAM Devices.

Artifact-Free Preparation of Plan View TEM Specimens and Its Application to MRAM Devices.

Revealing the structure-property relationships of amorphous carbon tribofilms on platinum-gold surfaces

Nanocrystalline metal alloys have shown great promise as electrical contact materials, given their mechanical and tribological properties. In particular, platinum-gold (Pt–Au) nanocrystalline alloys have demonstrated coefficients of friction as low as 0.01 and specific wear rates on the order of 10−9 mm3 N−1 m−1, largely due to the formation of carbon-based tribofilms at the sliding interfaces. In this study, we advance our understanding of the Pt–Au tribofilm structure-property relations and growth mechanisms via high-throughput and high-resolution measurements as a function of Pt–Au composition. As the solute content increased from 0 at. % to 10 at. % Au, cross-sectional and plan-view transmission electron microscopy demonstrated a decrease in average grain size d and an accompanied increase in grain boundary (GB) segregation. The decrease in d and increase in GB solute segregation translated to a decrease in modulus Er and an increase in hardness H as determined via nanoindentation; the Er trend was mainly described using a rule-of-mixtures approximation, whereas the H trend was ascribed to solid solution strengthening and GB stabilization. The steady state-friction μ and wear rate decreased with the addition of Au; low Au-content films showed substrate wear, while high Au-content films showed stable tribofilm growth in both macroscale and nanoscale friction tests. The carbon bonding configuration of the tribofilms was investigated by near-edge X-ray absorption fine structure spectroscopic analyses and found to be similar to that of hydrogenated amorphous carbon films. Altogether, the study provided insight into the mechanistic origins of the tribofilms, thus opening the door to tunable properties ranging from mitigation for electrical contacts to the creation of self-healing films for solid lubricants.

Partial dislocation structures at expansion terminating areas of bar-shaped single Shockley-type stacking faults and basal plane dislocations at the origin in 4H-SiC

Partial dislocation (PD) combinations near the substrate/epilayer interface and the epilayer surface of 4H-SiC are analyzed for bar-shaped single Shockley-type stacking faults (1SSFs) by plan-view transmission electron microscopy (TEM) with the aid of photoluminescence imaging. Although the PDs are found to have a zigzag structure similar to that found in triangular 1SSF by TEM observation, the combination is thought to be different, consisting of a 30° Si-core + 90° Si-core for the triangular 1SSF and 30° Si-core + 30° C-core for the bar-shaped 1SSF. The features of the basal plane dislocation at the origin are speculated by also identifying the converted threading edge dislocation by additional Burgers vector determination of the PD loop by TEM.

Nanocrystallite Seeding of Metastable Ferroelectric Phase Formation in Atomic Layer-Deposited Hafnia-Zirconia Alloys.

Hafnia-based ferroelectric thin films are promising for semiconductor memory and neuromorphic computing applications. Amorphous, as-deposited, thin-film binary alloys of HfO2 and ZrO2 transform to the metastable, orthorhombic ferroelectric phase during post-deposition annealing and cooling. This transformation is generally thought to involve formation of a tetragonal precursor phase that distorts into the orthorhombic phase during cooling. In this work, we systematically study the effects of atomic layer deposition (ALD) temperature on the ferroelectricity of post-deposition-annealed Hf0.5Zr0.5O2 (HZO) thin films. Seed crystallites having interplanar spacings consistent with the polar orthorhombic phase are observed by a plan-view transmission electron microscope in HZO thin films deposited at an elevated ALD temperature. After ALD under conditions that promote formation of these nanocrystallites, high-polarization (Pr > 18 μC/cm2) ferroelectric switching is observed after rapid thermal annealing (RTA) at low temperature (350 °C). These results indicate the presence of minimal non-ferroelectric phases retained in the films after RTA when the ALD process forms nanocrystalline particles that seed subsequent formation of the polar orthorhombic phase.

GaAs on (001) Si templates for near-infrared InP quantum dot lasers

We investigated the effects of thermal cycle annealing (TCA) at high temperatures on the defect density and morphology of GaAs epilayers grown on (001) Si substrates. Several types of TCA combined with dislocation filter layers (DFLs) were introduced to reduce the defect densities in the GaAs grown on Si substrates. Plan-view transmission electron microscopy shows that the defect density of a 2.7 μm-thick GaAs/Si template with optimized TCA and DFLs is 1.4 × 107 cm−2, lower than a 1.1 μm-thick GaAs/Si template by a factor of 40. The surface roughness of the optimized GaAs/Si template is 1.3 nm after insertion of the DFLs. Additionally, optically pumped InP quantum dot micro-disk lasers (MDLs) were fabricated on these GaAs/Si templates to evaluate the template quality. Room-temperature continuous-wave lasing of 1.5 μm-diameter MDLs was observed, with ultralow lasing thresholds ranging from 0.5 to 2 μW.

Structural Defects and Ferromagnetic Signature of V-Doped Sb2Te3 Thin Films Grown on SrTiO3(001) Produced by RF-Magnetron Sputtering.

Thin films of V-doped Sb2Te3 compounds were fabricated by co-deposition of Sb2Te3 and V using rf-magnetron sputtering onto SrTiO3(001) substrates kept at 570 K. The microstructures of the films were characterized using transmission electron microscopy (TEM) and electron diffraction. The crystal structure of the sputtered film (Sb38V2Te60) is the Bi2Te3-type structure with lattice parameters of a = 0.44 ± 0.03 nm and c = 3.02 ± 0.02 nm. A combination of cross-sectional and plan-view TEM observations revealed the preferential orientation of the c axis in the film's normal direction. A thin amorphous layer exists between the Sb2Te3 thin film and the SrTiO3 substrate. The interfacial amorphous layer relaxes the strain between the thin film and the substrate, and hence, it should promote the growth of a low-index atomic plane with a low surface free energy (i.e., (0001) of the Sb2Te3). The onset of ferromagnetic order was detected at temperatures below 70 K. A remarkable increase in magnetization was detected in the film's normal direction, which corresponds to the magnetic easy axis (i.e., c axis of the Sb2Te3). V3+ ions substituting Sb sites should contribute to ferromagnetism at low temperatures.

(G03 - Best Student Presentation Award) Lateral Selective SiGe Growth for Dislocation-Free Virtual Substrate Fabrication

SiGe virtual substrates (VS) having low-surface roughness with less defects are essential for fabricating emerging quantum devices such as qubits. Various techniques to grow VS are reported e.g. conventional graded buffers (1,2) and reverse graded buffers (3). However, these methods require several micrometer-thick buffer layers, having threading dislocations (TDs) network and develop crosshatch patterns resulting in high surface roughness, needing chemical mechanical polishing for planarization. In our previous work, lateral-selective Ge growth (4) was performed in a cavity formed by selective vapor phase etching (VPE) of Si from side of mesa-patterned SiO2 /Si structures fabricated on buried oxide (BOX) to create smooth and dislocation-free local Ge by horizontal aspect ratio trapping (ART). In this work, we demonstrate lateral-selective SiGe growth to realize smooth and dislocation-free local SiGe VS by lateral ART and discuss its surface morphology, strain and dislocations.Lateral-selective SiGe growth is done in a reduced-pressure chemical vapor deposition (RPCVD) system. Thermally oxidized silicon-on-insulator (SOI) wafers with 300 nm SiO2/300 nm Si/2 μm BOX are used. For the sample preparation, 6.3 μm square checkerboard SiO2/Si mesa structure with [110] oriented sidewalls is fabricated by photolithography patterning and reactive ion etching. After standard RCA cleaning followed by HF dip, the wafer is loaded into RPCVD reactor and pre-baked at 850oC in H2 to remove residual oxide. Thereafter, lateral HCl VPE of Si is performed at 850oC from side of mesa. Si pillar remains at center of the mesa. Then, SiGe is selectively deposited in the cavity around the Si pillar using a SiH2Cl2-GeH4-HCl gas mixture at 750oC. Finally, the top SiO2 is removed by HF. Atomic force microscopy (AFM) is used to measure the surface roughness. Energy dispersive X-Ray spectroscopy (EDX) is used for measuring Ge content distribution in SiGe. Micro-Raman spectroscopy is used to analyze strain distribution in Si and SiGe. Nano-beam diffraction (NBD) is employed for estimating the relative change of in- and out-of-plane SiGe lattice parameters. Plan-view transmission electron microscopy (TEM) is used for imaging dislocations.Fig. 1 shows the AFM image for surface morphology of lateral-selective Si0.6Ge0.4 around the Si pillar. SiGe has root mean square roughness of ~0.16 nm, which is similar to blanket Si(001) (~0.14 nm), because the SiGe surface roughness is determined by interface roughness of top SiO2 and sacrificially etched Si. Uniform Ge content of ~40% in SiGe layer is observed by EDX analysis (Fig. 2). In the Si pillar part of Fig. 3, relative uniform tensile-strain of ~0.4% is observed. Since Si is negligibly strained in unpatterned area of SOI (taken as reference), hence during HCl VPE at 850oC, Si pillar/SiO2 interface could slip by higher thermal expansion of Si as interface decreases. Tensile-strain in Si pillar could be formed during cooling process. Ideally, ~1.68% lattice mismatch strain should exist in fully-relaxed ~40% SiGe on Si. However, higher tensile-strain (~2.5%) in SiGe is observed at corners along [010]. To clarify the reason of higher strain at corners, in- and out-of-plane SiGe lattice parameters near Si pillar (as marked in Fig 4(a)) are investigated by NBD. Higher in-plane lattice parameter in [110] is observed in the edge part of the SiGe lamella as compared to the center part (Fig. 4(b)). However, out-of-plane lattice parameter in [001] is homogeneous across entire SiGe (Fig. 4(c)). Because SiGe has uniform Ge concentration as shown in Fig. 2, higher lattice parameter in the edge part of Fig. 4(b) is caused by strain difference. This is because SiGe lamella edge (away from Si pillar) is more relaxed as compared to SiGe lamella center (beside Si pillar) which is confirmed by vertically grown ~700 nm 40% SiGe on blanket Si(110). Symmetric strain distribution does also exist in 90° rotated direction. Therefore, the tensile-strain in [010] is induced from both [110] and [-110]. In Fig. 5, stacking faults of SiGe on (111) plane are observed along [110] and [1-10]. TDs are present along [111], terminated by top SiO2/BOX and located up to first ~400 nm from Si while misfit dislocations are at Si/SiGe interface. Wide dislocation-free area in SiGe is present along [010].This technique enables dislocation-free local SiGe-on-insulator substrate fabrication which can be applied for thin and high quality VS for the quantum devices. References E. A. Fitzgerald et al., J. Appl. Phys., 63, 693 (1988).E. A. Fitzgerald et al., Appl. Phys. Lett., 59, 811 (1991).V. A. Shah et al., Appl. Phys. Lett., 93, 192103 (2008).Y. Yamamoto et al., ECS J. of Solid State Sci. and Technol., 3, 353 (2014). Figure 1

Viewing SiGe Heterostructure for Qubits with Dislocation Theory

SiGe/Si/SiGe heterostructure serves as one of the ideal semiconductor material system to build large scale electron spin qubits[1]. To further push the scalability and extend the coherence times of qubits built on SiGe/Si/SiGe heterostructures, there are several factors to improve, one of that is the lattice homogeneity of strained Si. One source of lattice homogeneity break down are dislocations. Due to the difficulties of high quality SiGe bulk crystal growth [2-3], relaxed SiGe is commonly grown on Si substrates by epitaxy. Viewing the SiGe/Si/SiGe heterostructure on native Si substrate, dislocations half loops form unavoidably because of the misfit between SiGe and the Si substrate. These dislocation half loops consist of threading segments extending through the whole heterostructure (figure 1 (a) and (c)) [4]. Due to the stress caused by the strained Si quantum well layer, the threading dislocations can be driven to glide, resulting in additional misfit segments in the lower interface of strained Si layer when the critical thickness is exceeded (figure 1 (b)) [5]. The extension of these misfit segments is blocked when they meet other perpendicular dislocations (figure 1 (d)) [6]. These misfit dislocations destroy strain uniformity and cause tilt inside the Si layer, resulting in a distortion of the valley splitting and ultimately, reducing the coherence time of qubits [7-8].In this work, we present the observation of dislocations in SiGe/Si/SiGe heterostructures for qubit application by plan-view TEM (Figure 1 (right)). Here, the experimental observations agree with dislocation theory that threading dislocations (some are marked by (b)) will glide and elongate to have misfit segments (some are marked by (c)) in the interface when two requirements are fulfilled: misfit exists between epitaxial layer and substrate; critical thickness is exceeded. When the misfit dislocations meet perpendicular misfit dislocation line, they are blocked since the thickness is not enough to glide over it [6]. This is the case in figure 1 right marked by (d). Due to the misfit segment generation and blocking effects, the misfit dislocation spacing is proportional to the threading dislocation density both theoretically and experimentally. These misfit dislocations bring local strain field around them [9], which disturb the desired homogeneous strain field by misfit. Therefore, misfit dislocation generation needs to be suppressed if one wants to achieve homogeneous strain in Si thin layer in large scale.According to Matthews-Blakeslee theory, one can avoid the formation of misfit dislocations in the Si interface by controlling the strained layer within the critical thickness. The critical thickness of Si on Si0.7Ge0.3 is calculated as 8.5 nm. The Electron channeling contrast images of Si with difference thickness 10 nm and 5 nm grown on high threading dislocation relaxed Si0.7Ge0.3 buffer at 700°C by reduced pressure chemical vapor deposition in Figure 2 are collaborating with theory: obviously misfit dislocation appear in 10 nm Si on relaxed Si0.7Ge0.3 (Figure 2 (left)) and no misfit dislocation are presented in 5 nm Si on Si0.7Ge0.3 (Figure 2 (right)).Our results show that dislocation generation and movement needs to be taken into consideration to further develop SiGe heterostructure based qubits.

Role of critical thickness in SiGe/Si/SiGe heterostructure design for qubits

We study the critical thickness for the plastic relaxation of the Si quantum well layer embedded in a SiGe/Si/SiGe heterostructure for qubits by plan-view transmission electron microscopy and electron channeling contrast imaging. Misfit dislocation segments form due to the glide of pre-existing threading dislocations at the interface of the Si quantum well layer beyond a critical thickness given by the Matthews–Blakeslee criterion. Misfit dislocations are mostly 60° dislocations (b=a/2 &amp;lt;110&amp;gt;) that are split into Shockely partials (b=a/6 &amp;lt;112&amp;gt;) due to the tensile strain field of the Si quantum well layer. By reducing the quantum well thickness below critical thickness, misfit dislocations can be suppressed. A simple model is applied to simulate the misfit dislocation formation and the blocking process. We discuss consequences of our findings for the layer stack design of SiGe/Si/SiGe heterostructures for usage in quantum computing hardware.

Preferential sublimation along threading dislocations in InGaN/GaN single quantum well for improved photoluminescence

InGaN/GaN single quantum wells were grown by molecular beam epitaxy on the silicon substrate onto thin AlN and GaN buffer layers. The InGaN/GaN structure is porosified using a combination of SixNy nanomasking and sublimation and compared with a non-porous reference. The photoluminescence efficiency at room temperature of the porosified sample is improved by a factor reaching 40 compared with the reference sample. Plan-view and cross-sectional transmission electron microscopy images reveal that the remaining material is free of dislocation cores. The regions around dislocations are, thus, preferentially sublimated. This explains the strong photoluminescence improvement of nanoporous InGaN/GaN samples.

Formation of epitaxial 3C-SiC layers on Si by rapid vacuum thermal processing

The results of a study of the structure and phase composition of epitaxial layers of silicon carbide (SiC) formed on silicon substrate with orientation (100) under rapid vacuum thermal processing are presented. Planar-view transmission electron microscopy investigation revealed the formation of epitaxial layers of cubic polytype SiC (3C-SiC) on silicon in the process of carbidisation at 1100 °C during 30 s, using a gas mixture of propane (10 %) and argon (90 %) as a carbon source. The formation of a monocrystalline 3C-SiC with polycrystalline inclusions and twins on all possible planes {111} was found. A rather narrow band of 793 cm–1 transverse optical phonon mode SiC on Raman spectra confirms the formation of a cubic polytype SiC. It is noted that the presence of a 180 cm–1 spectral line and a 793 cm–1 half-width band on Raman spectra indicate the presence of deformation defects in SiC.

In Situ Transmission Electron Microscopy Study of Shrinkage Kinetics of CH4N-Molecular-Ion-Implantation-Induced Extended Defects

The thermal stability of end-of-range (EOR) defects formed in a CH4N-molecular-ion-implanted epitaxial silicon (Si) wafer was studied by transmission electron microscopy (TEM) observation. By plan-view TEM observation, we found that the density and size of the CH4N-ion-implantation-induced EOR defects negligibly changed upon heat treatment at temperatures below 1000 °C, whereas the EOR defect density was drastically reduced by heating at 1100 °C. This result suggests that almost all CH4N-ion-implantation-induced EOR defects were sufficiently thermally stable to maintain their size at temperatures below 1000 °C, and that above 1100 °C, most of the EOR defects lost their stability, shrank and finally dissolved. Additionally, by in situ cross-sectional TEM observation during heat treatment, we found a large difference in the shrinkage rates of the EOR defects between at the beginning of heat treatment and the last minute of just before defect disappearance. We found that the EOR defects began to gradually shrank at the beginning of heat treatment (1st stage), and then the shrinkage rate rapidly increased (2nd stage), finally resulting in the dissolution of the defects. The activation energies for the shrinkage of EOR defects in the 1st and 2nd stages (E D-1 and E D-2) were found to be 7.55 ± 1.03 and 4.57 ± 0.32 eV, respectively. The shrinkage behavior in the 1st stage is likely to be due to the thermally activated desorption of C and N species that segregated along the edge of an EOR defect. On the other hand, from the E D-2 value, the shrinkage behavior in the 2nd stage is deduced to be due to the desorption of interstitial Si atoms. These findings suggest that this two-stage shrinkage behavior is peculiar to the EOR defects formed in the CH4N-ion-implanted epitaxial Si wafer, and that the interaction between the EOR defect and the impurities segregated at the edge of the defect affects the thermal robustness of the molecular-ion-implantation-induced EOR defects.

A user-friendly FIB lift-out technique to prepare plan-view TEM sample of 2D thin film materials

Plan-view transmission electron microscopy (TEM) or electron diffraction imaging of a bulk or 2D material can provide detailed information about the structural or atomic arrangement in the material. A systematic and easily implementable approach to preparing site-specific plan-view TEM samples for 2D thin film materials using FIB is discussed that could be routinely used. The methodology has been successfully applied to prepare samples from 2D materials such as, MoS2 thin film, vertically oriented graphene film (VG), as well as heterostructure material SnTiS3. It is worth mentioning that in contrast to planar conventional graphene, VG grows vertically from the substrate and takes nanosheet arrays. Samples prepared using this methodology provide a simple, faster, and precise course in obtaining valuable structural information. The top-view imaging offers various information about the growth nature of the materials suggesting the efficiency of the sample preparation process.

Plan-view TEM observation of a single-domain κ-Ga2O3 thin film grown on ε-GaFeO3 substrate using GaCl3 precursor by mist chemical vapor deposition

We demonstrated the growth of a single-domain κ-Ga2O3 thin film on ε-GaFeO3 by using an organic-free compound as a precursor for mist chemical vapor deposition. X-ray diffraction analysis revealed that an 86 nm thick κ-Ga2O3 thin film was grown almost coherently with slight lattice relaxation. The surface morphology of the κ-Ga2O3 thin film exhibited a step-terrace structure without island growth. Furthermore, plan-view TEM observations revealed that the κ-Ga2O3 thin film grown on ε-GaFeO3 had a single domain, whereas the previously reported κ-Ga2O3 thin film grown on AlN template had a domain structure.