Placement Algorithm For FPGAs Research Articles

PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing

PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing

Packing and Legalization Free Boolean Satisfiability-based Placement Algorithm for Heterogeneous FPGAs

Packing and Legalization Free Boolean Satisfiability-based Placement Algorithm for Heterogeneous FPGAs

Clock-Aware Placement for Large-Scale Heterogeneous FPGAs

A modern FPGA often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this paper presents a novel clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of three major stages: (1) a nonlinear global placement framework with clock fence region construction, (2) a clock-aware packing scheme, and (3) clock-aware legalization and detailed placement. We evaluate our results based on the 2017 ISPD Clock-Aware Placement Contest benchmark suite. Compared with the top three winners, the results show that our algorithm achieves the best overall routed wirelength. On average, our algorithm outperforms the top-3 winners by 3.6%, 7.5%, and 12.9% in routed wirelength, respectively.

A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform

Reasonable trade-off between the ASIC performance and GPP flexibility is the main objective of reconfigurable computing systems. Dynamic Reconfigurable computing platform using embedded just-in-time (JIT) compilation is the most flexible platform among others. All complex computing kernels can be translated to bitstream to be executed on FPGA using an embedded processor of dedicated specialized hardware. The main challenge in these systems is FPGA design automation time. Executing the CAD algorithms on embedded processor is too time-consuming and normally is not feasible for real applications. Placement is the most computative part of CAD algorithm. Therefore, a new FPGA placement algorithm is proposed in this paper which makes reasonable trade-off between execution time and quality of placement. The proposed algorithm includes two stages: force-directed placement and simulated annealing placement. The proposed algorithm is very low execution time to be useful in JIT compilation without considerable degradation on the quality of placement. Experimental results show $$2.33\times $$2.33A— speedup in execution time in cost of 3Â % overhead in channel tracks numbers.

Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs

As the feature size shrinks to the nanometer scale, SRAM-based FPGAs will become increasingly vulnerable to soft errors. Existing reliability-oriented placement and routing approaches primarily focus on reducing the fault occurrence probability (node error rate) of soft errors. However, our analysis shows that, besides the fault occurrence probability, the propagation probability (error propagation probability) plays an important role and should be taken into consideration. In this paper, we first propose a cube-based analysis algorithm to efficiently and accurately estimate the error propagation probability. Based on such a model, we propose a novel reliability-oriented placement and routing algorithm that combines both the fault occurrence probability and the error propagation probability together to enhance system-level robustness against soft errors. Experimental results show that, compared with the baseline versatile place and route technique, the proposed scheme can reduce the failure rate by 20.73%, and increase the mean time between failures by 39.44%.

Markov Clustering-Based Placement Algorithm for Hierarchical FPGAs

Divide-and-conquer methods for FPGA placement algorithms including partition-based and cluster-based algorithms have shown the importance of good quality-runtime trade-off. This paper describes a cluster-based FPGA placement algorithm targeted to a new commercial hierarchical FPGA device. The algorithm is based on a Markov clustering algorithm that defines a sequence of stochastic matrices operating on a generating matrix from the input FPGA circuit netlist. The core of the algorithm tightly couples a Markov clustering process with a multilevel placement process. Tests show its excellent adaptability to hierarchical FPGAs. The average wirelength results produced by the algorithm are 22.3% shorter than the results produced by the current hierarchical FPGA placer.

Near-linear wirelength estimation for FPGA placement

With rapid advances in integrated circuit technology, wirelength has become one of the most critical and important metrics in all phases of VLSI physical design automation, especially circuit placement. As the precise wirelength for a given placement can only be known after routing, accurate and fast-to-compute wirelength estimates are required by FPGA placement algorithms. In this paper, a new model, called star+, is presented for estimating wirelength during FPGA placement. The proposed model is continuously differentiable and can be used with both analytic and iterative-improvement placement methods. Moreover, the time required to calculate incremental changes in cost incurred by moving/swapping blocks can always be computed in O(1) time. Results show that when incorporated into the well-known VPR framework and tested using the 20 MCNC benchmarks, the star+ model achieves a 6-9% reduction in critical-path delay compared with the half-perimeter wirelength (HPWL) model, while requiring roughly the same amount of computational effort.

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly into the force equations to guide the placement. Slot assignment is then used to move the blocks into valid slot locations on the FPGA chip. The assignment algorithm also makes use of the delay information of nets so that the final placement is able to meet the timing criteria specified for the circuit. The novelty of the approach lies in the formulation of the force equations and the manner in which weights of the nets are dynamically altered to influence the placement. Experiments conducted on industrial test circuits and MCNC circuits give very promising results and indicate that the algorithm succeeds in significantly reducing the maximum delay in the circuit. In addition, routability is not adversely affected and running time is low.